A B C D E

1 1

Compal Confidential
2 2

NAL90/NALG0 M/B Schematics Document

Intel Auburndale/Clarksfield Processor with DDRIII + Ibex Peak-M

3 2009-10-20 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 1 of 60
A B C D E
 A B C D E

Clock Generator
Compal Confidential IDT: 9LRS3199AKLFT
Model Name NALG0 SILEGO: SLG8SP587
133/120/100/96/14.318MHZ to PCH
File Name : LA5681P Fan Control
page 41
48MHZ to CardReader
page 12
1 1

100MHz PCI-E 2.0x16 5GT/s PER LANE

PEG(DIS) Intel Memory BUS(DDRIII)
Nvidia N11MGE1 133MHz Dual Channel 204pin DDRIII-SO-DIMM X2
HDMI(DIS) Auburndale / Clarksfield BANK 0, 1, 2, 3 page 10,11
page LVDS(DIS) 1.5V DDRIII 800/1066/1333
22,23,24,25,26,27 CRT(DIS) (UMA/DIS) (DIS) 6.4G/8.5G/10.6G
100M/133M/166M(CFD)
Processor
rPGA988A
page 4,5,6,7,8,9

USB conn x2 Bluetooth CMOS Finger Card

FDI x8 DMI x4 USB port 8 HS Printer Reader
(UMA) USB Port 2 (eSATA)
Conn Camera
HDMI Conn. CRT Conn. CRT LVDS Conn. LVDS USB port 10 USB port 3 USB port 11 USB port 6
100MHz 100MHz USB port 0 (sub board)
page 30
page 29
SW
page 29 page 28
SW
page 28 2.7GT/s 1GB/s x4
page 35 page 35 page 28 page 35 page 36

2 USBx14 3.3V 48MHz 2

LVDS(UMA)
Intel 3.3V 24MHz
CRT(UMA) HD Audio
Level Shift Ibex Peak-M
HDMI(UMA) SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz
page 30
PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S) 100MHz PCH HDA Codec MDC
page 13,14,15,16,17
18,19,20,21 ALC888 page 39
port 2,4 port 1 SPI page 40

MINI Card x2 LAN(GbE) port 0 port 1 port 4

WLAN, TV BCM57780 SATA HDD SATA ODD eSATA
SPI ROM x2 Audio AMP
page 32 page 33 Conn. Conn. Conn.
page 13 APA2051
page 31 page 31 page 35
page 41

3
RJ45 LPC BUS 3

page 34
33MHz
Int. Speaker
ENE KB926 page 41
page 37
NAL90 Sub-board NALG0 Sub-board
RTC CKT. LS-5682P LS-5682P
page 8 USB/B USB/B
page 35 page 35 Touch Pad Int.KBD
page 38 page 38

Power On/Off CKT. LS-4493P

Media/B
page 8 page 38 BIOS ROM
page 38
LS-5683P LS-5683P
DC/DC Interface CKT. Function/B Function/B
page 38 page 38
4 4
page 42

LS-5681P LS-5681P
Finger Printer/B Finger Printer/B
Power Circuit DC/DC page 35 page 35
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title
page Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 2 of 60
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON ON OFF
+GFX_core Core voltage for CPU ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.1VS_VTT 1.1V switched power rail (1.05 for AUB CPU) ON OFF OFF
+VGA_CORE Core voltage for N11M VGA ON OFF OFF
+1.05VS 1.05V switched power rail for PCH ON OFF OFF Board ID / SKU ID Table for AD channel
+1.5VS 1.5V power rail for DDRIII ON ON OFF Vcc 3.3V +/- 5%
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VS 1.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS 1.8V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW 3.3V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3V_LAN 3.3V power rail for LAN ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VS 3.3V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW 5V always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS 5V switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
BOARD ID Table BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BTO Item BOM Structure
Board ID PCB Revision
0
UMA UMA@
0.1
UMA only UMA only@
External PCI Devices 1 0.2
DIS DIS@
2 0.3
Device IDSEL# REQ#/GNT# Interrupts DIS Only DIS only@
3 1.0
Switchable SG@
4
5
XDP@
6
NonSG@
7
MINI2@
FP@
USB Port Table eDriver@
EC SM Bus1 address EC SM Bus2 address Dmic@
4 External
3 USB 2.0 USB 1.1 Port USB Port 3
Device Address Device Address
Caps@
Smart Battery 0001 011X b PCH 0 Ext4 HS USB
UHCI0 X76@
VGA 1 sub Board
HDCP@
2 AMIC@
UHCI1
S3 power S3@
3 Camera
EHCI1 non S3@
4 1st Min-Card
UHCI2
Ibex SM Bus address 5 2st Min-Card
6 BOM Config
Device Address UHCI3 UMA only
7 UMA@/UMA only@/FP@/Dmic@/XDP@/S3@
Clock Generator 1101 0010b
(9LRS3199AKLFT, SLG8SP587) 8 Ext4 HS USB
DDR DIMM0
UHCI4
1001 000Xb 9 Card Reader
DDR DIMM2
DIS ONLY
1001 010Xb 10 Blue Tooth DIS@/DIS only@/FP@/Dmic@/XDP@/S3@
Mini card
EHCI2 UHCI5
11 Finger Print
12
4 UHCI6 Switchable Graphics 4
13 SG@/UMA@/DIS@/FP@/Dmic@/XDP@/S3@
Note:do cost BOM add X76@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 3 of 60

A B C D E
 5 4 3 2 1

JCPU1E

JCPU1A R520 AJ13

PEG_IRCOMP RSVD32
PEG_ICOMPI B26 1 2 49.9_0402_1% RSVD33 AJ12
PEG_ICOMPO A26
DMI_PTX_HRX_N0 A24 B27 R535 AP25
DMI_PTX_HRX_N1 DMI_RX#[0] PEG_RCOMPO EXP_RBIAS RSVD1
C23 DMI_RX#[1] PEG_RBIAS A25 1 2 750_0402_1% AL25 RSVD2 RSVD34 AH25
DMI_PTX_HRX_N2 B22 AL24 AK26
DMI_PTX_HRX_N3 DMI_RX#[2] PEG_GTX_C_HRX_N15 RSVD3 RSVD35
A21 DMI_RX#[3] PEG_RX#[0] K35 AL22 RSVD4
J34 PEG_GTX_C_HRX_N14 AJ33 AL26
DMI_PTX_HRX_P0 PEG_RX#[1] PEG_GTX_C_HRX_N13 RSVD5 RSVD36
B24 DMI_RX[0] PEG_RX#[2] J33 AG9 RSVD6 RSVD_NCTF_37 AR2
DMI_PTX_HRX_P1 D23 G35 PEG_GTX_C_HRX_N12 M27
DMI_RX[1] PEG_RX#[3] RSVD7

DMI
DMI_PTX_HRX_P2 B23 G32 PEG_GTX_C_HRX_N11 L28 AJ26
DMI_PTX_HRX_P3 DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10 RSVD8 RSVD38
D A22 DMI_RX[3] PEG_RX#[5] F34 10 H_DIMMA_REF J17 SA_DIMM_VREF (CFD Only) RSVD39 AJ27 D
F31 PEG_GTX_C_HRX_N9 H17
PEG_RX#[6] 11 H_DIMMB_REF SB_DIMM_VREF (CFD Only)
DMI_HTX_PRX_N0 D24 D35 PEG_GTX_C_HRX_N8 G25
DMI_HTX_PRX_N1 DMI_TX#[0] PEG_RX#[7] PEG_GTX_C_HRX_N7 RSVD11
G24 DMI_TX#[1] PEG_RX#[8] E33 G17 RSVD12
DMI_HTX_PRX_N2 F23 C33 PEG_GTX_C_HRX_N6 E31 AP1
DMI_HTX_PRX_N3 DMI_TX#[2] PEG_RX#[9] PEG_GTX_C_HRX_N5 RSVD13 RSVD_NCTF_40
H23 DMI_TX#[3] PEG_RX#[10] D32 E30 RSVD14 RSVD_NCTF_41 AT2
B32 PEG_GTX_C_HRX_N4
DMI_HTX_PRX_P0 PEG_RX#[11] PEG_GTX_C_HRX_N3
D25 DMI_TX[0] PEG_RX#[12] C31 RSVD_NCTF_42 AT3
DMI_HTX_PRX_P1 F24 B28 PEG_GTX_C_HRX_N2 AR1
DMI_HTX_PRX_P2 DMI_TX[1] PEG_RX#[13] PEG_GTX_C_HRX_N1 RSVD_NCTF_43
E23 DMI_TX[2] PEG_RX#[14] B30
DMI_HTX_PRX_P3 G23 A31 PEG_GTX_C_HRX_N0
DMI_TX[3] PEG_RX#[15]
J35 PEG_GTX_C_HRX_P15 R74 AL28
PEG_RX[0] PEG_GTX_C_HRX_P14 3.01K_0402_1% RSVD45
PEG_RX[1] H34 1 @ 2 CFG0 AM30 CFG[0] RSVD46 AL29
H33 PEG_GTX_C_HRX_P13 AM28 AP30
H_FDI_TXN0 PEG_RX[2] PEG_GTX_C_HRX_P12 R72 CFG[1] RSVD47
E22 FDI_TX#[0] PEG_RX[3] F35 AP31 CFG[2] RSVD48 AP32
H_FDI_TXN1 D21 G33 PEG_GTX_C_HRX_P11 3.01K_0402_1% 1 DIS@ 2 CFG3 AL32 AL27
H_FDI_TXN2 FDI_TX#[1] PEG_RX[4] PEG_GTX_C_HRX_P10 R75 CFG[3] RSVD49
D19 FDI_TX#[2] PEG_RX[5] E34 1 @ 2 CFG4 AL30 CFG[4] RSVD50 AT31
H_FDI_TXN3 D18 F32 PEG_GTX_C_HRX_P9 3.01K_0402_1% AM31 AT32
H_FDI_TXN4 FDI_TX#[3] PEG_RX[6] PEG_GTX_C_HRX_P8 CFG[5] RSVD51
G21 FDI_TX#[4] PEG_RX[7] D34 AN29 CFG[6] RSVD52 AP33
H_FDI_TXN5 PEG_GTX_C_HRX_P7 R71 1 @ CFG7
H_FDI_TXN6
E19
F21
FDI_TX#[5]
FDI_TX#[6]
PCI EXPRESS -- GRAPHICS PEG_RX[8]
PEG_RX[9]
F33
B33 PEG_GTX_C_HRX_P6 3.01K_0402_1%
2 AM32
AK32
CFG[7]
CFG[8]
RSVD53
RSVD_NCTF_54
AR33
AT33
Intel(R) FDI

H_FDI_TXN7 G18 D31 PEG_GTX_C_HRX_P5 AK31 AT34

RESERVED
FDI_TX#[7] PEG_RX[10] PEG_GTX_C_HRX_P4 CFG[9] RSVD_NCTF_55
PEG_RX[11] A32 AK28 CFG[10] RSVD_NCTF_56 AP35
PEG_RX[12] C30 PEG_GTX_C_HRX_P3 WW41 Recommend not pull down AJ28 CFG[11] RSVD_NCTF_57 AR35
H_FDI_TXP0 D22 A28 PEG_GTX_C_HRX_P2 PCIE2.0 Jitter is over on ES1 AN30 AR32
H_FDI_TXP1 FDI_TX[0] PEG_RX[13] PEG_GTX_C_HRX_P1 CFG[12] RSVD58
C21 FDI_TX[1] PEG_RX[14] B29 AN32 CFG[13]
H_FDI_TXP2 D20 A30 PEG_GTX_C_HRX_P0 AJ32
H_FDI_TXP3 FDI_TX[2] PEG_RX[15] CFG[14]
C18 FDI_TX[3] AJ29 CFG[15] RSVD_TP_59 E15
C H_FDI_TXP4 G22 L33 PEG_HTX_GRX_N15 C473 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N15 AJ30 F15 C
H_FDI_TXP5 FDI_TX[4] PEG_TX#[0] PEG_HTX_GRX_N14 C475 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N14 CFG[16] RSVD_TP_60
E20 FDI_TX[5] PEG_TX#[1] M35 1 2 AK30 CFG[17] KEY A2
H_FDI_TXP6 F20 M33 PEG_HTX_GRX_N13 C470 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N13 H16 D15 R214
H_FDI_TXP7 FDI_TX[6] PEG_TX#[2] PEG_HTX_GRX_N12 C458 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N12 RSVD_TP_86 RSVD62 0_0402_5%
G19 FDI_TX[7] PEG_TX#[3] M30 1 2 RSVD63 C15
L31 PEG_HTX_GRX_N11 C454 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N11 AJ15 RSVD64_R 2 @ 1
PEG_TX#[4] PEG_HTX_GRX_N10 C447 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N10 RSVD64 RSVD65_R 2 @
15 H_FDI_FSYNC0 F17 FDI_FSYNC[0] PEG_TX#[5] K32 1 2 RSVD65 AH15 1
E17 M29 PEG_HTX_GRX_N9 C460 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N9 R213
15 H_FDI_FSYNC1 FDI_FSYNC[1] PEG_TX#[6]
J31 PEG_HTX_GRX_N8 C455 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N8 B19 0_0402_5%
PEG_TX#[7] PEG_HTX_GRX_N7 C448 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N7 R557 RSVD15
15 H_FDI_INT C17 FDI_INT PEG_TX#[8] K29 1 2 A19 RSVD16
H30 PEG_HTX_GRX_N6 C464 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N6 0_0402_5%
PEG_TX#[9] PEG_HTX_GRX_N5 C477 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N5 @ H_RSVD17_R
15 H_FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29 1 2 1 2 A20 RSVD17
D17 F29 PEG_HTX_GRX_N4 C463 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N4 1 @ 2 H_RSVD18_R B20
15 H_FDI_LSYNC1 FDI_LSYNC[1] PEG_TX#[11] RSVD18
E28 PEG_HTX_GRX_N3 C450 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N3 AA5
PEG_TX#[12] PEG_HTX_GRX_N2 C482 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N2 R548 RSVD_TP_66
PEG_TX#[13] D29 1 2 U9 RSVD19 RSVD_TP_67 AA4
D27 PEG_HTX_GRX_N1 C480 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N1 0_0402_5% T9 R8
PEG_TX#[14] PEG_HTX_GRX_N0 C468 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N0 RSVD20 RSVD_TP_68
PEG_TX#[15] C26 1 2 RSVD_TP_69 AD3
AC9 RSVD21 RSVD_TP_70 AD2
L34 PEG_HTX_GRX_P15 C472 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P15 AB9 AA2
PEG_TX[0] PEG_HTX_GRX_P14 C474 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P14 RSVD22 RSVD_TP_71
PEG_TX[1] M34 1 2 RSVD_TP_72 AA1
M32 PEG_HTX_GRX_P13 C471 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P13 R9
PEG_TX[2] DMI_PTX_HRX_N[0..3] 15 RSVD_TP_73
L30 PEG_HTX_GRX_P12 C465 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P12 AG7
PEG_TX[3] DMI_PTX_HRX_P[0..3] 15 RSVD_TP_74
M31 PEG_HTX_GRX_P11 C456 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P11 C1 AE3
PEG_TX[4] PEG_HTX_GRX_P10 C451 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P10 RSVD_NCTF_23 RSVD_TP_75
PEG_TX[5] K31 1 2 DMI_HTX_PRX_N[0..3] 15 A3 RSVD_NCTF_24
M28 PEG_HTX_GRX_P9 C466 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P9
PEG_TX[6] DMI_HTX_PRX_P[0..3] 15
H31 PEG_HTX_GRX_P8 C457 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P8 V4
PEG_TX[7] PEG_HTX_GRX_P7 C452 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P7 RSVD_TP_76
PEG_TX[8] K28 1 2 H_FDI_TXN[0..7] 15 RSVD_TP_77 V5
G30 PEG_HTX_GRX_P6 C469 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P6 N2
PEG_TX[9] H_FDI_TXP[0..7] 15 RSVD_TP_78
G29 PEG_HTX_GRX_P5 C476 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P5 J29 AD5
PEG_TX[10] PEG_HTX_GRX_P4 C462 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P4 RSVD26 RSVD_TP_79
PEG_TX[11] F28 1 2 J28 RSVD27 RSVD_TP_80 AD7
B PEG_HTX_GRX_P3 C449 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P3 B
PEG_TX[12] E27 1 2 PEG_GTX_C_HRX_N[0..15] 22 RSVD_TP_81 W3
D28 PEG_HTX_GRX_P2 C481 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P2 A34 W2
PEG_TX[13] PEG_GTX_C_HRX_P[0..15] 22 RSVD_NCTF_28 RSVD_TP_82
C27 PEG_HTX_GRX_P1 C479 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P1 A33 N3
PEG_TX[14] PEG_HTX_GRX_P0 C467 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P0 RSVD_NCTF_29 RSVD_TP_83
PEG_TX[15] C25 1 2 PEG_HTX_C_GRX_N[0..15] 22 RSVD_TP_84 AE5
PEG_HTX_C_GRX_P[0..15] 22 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
B35 RSVD_NCTF_31
IC,AUB_CFD_rPGA,R1P0 AP34
CONN@ VSS

IC,AUB_CFD_rPGA,R1P0
CONN@

eDP Signals MAPPING CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence

eDP Singal PEG Singals Lane Reversal *1:Single PEG *1:Disabled; No Physical Display Port
eDP_TX0 PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_P0 0:Bifurcation enabled attached to Embedded Display Port
0:Enabled; An external Display Port
eDP_TX#0 PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_N0 H_FDI_FSYNC0 R163 1 DIS only@
2 1K_0402_5%
device is connected to the Embedded
H_FDI_FSYNC1 R166 1 DIS only@
2 1K_0402_5%
Display Port
eDP_TX1 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P1 CFG3 - PCI-Express Static Lane Reversal
H_FDI_INT R171 1 DIS only@
2 1K_0402_5%
eDP_TX#1 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N1 *:Default
A eDP_TX2 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P2 H_FDI_LSYNC0 R167 1 DIS only@
2 1K_0402_5% *1 :Normal Operation A
H_FDI_LSYNC1 R172 1 DIS only@
2 1K_0402_5% 0 :Lane Numbers Reversed
eDP_TX#2 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N2 CheckList0.8 1.22 15 -> 0, 14 -> 1, ...
Auburndale Graphics Disable
eDP_TX3 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P3
eDP_TX#3 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N3 Security Classification Compal Secret Data Compal Electronics, Inc.
eDP_AUX PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P2 Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

eDP_AUX# PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (1/6) DMI,FDI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
eDP_HPD# PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P3 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 4 of 60
5 4 3 2 1
 5 4 3 2 1

JCPU1B
H_COMP3 AT23 COMP3 CLK_CPU_BCLK_R R578 1
BCLK A16 2 0_0402_5% CLK_CPU_BCLK 18

MISC
H_COMP2 AT24 B16 CLK_CPU_BCLK#_R R581 1 2 0_0402_5%
COMP2 BCLK# CLK_CPU_BCLK# 18
H_COMP1 CLK_CPU_ITP_R R506 1 XDP@ 2 0_0402_5% CLK_CPU_XDP

CLOCKS
G16 COMP1 BCLK_ITP AR30
AT30 CLK_CPU_ITP#_R R515 1 XDP@ 2 0_0402_5% CLK_CPU_XDP#
H_COMP0 BCLK_ITP#
AT26 COMP0
E16 CLK_CPU_DMI_R R577 1 2 0_0402_5%
PEG_CLK CLK_CPU_DMI 14
D16 CLK_CPU_DMI#_R R571 1 2 0_0402_5%
PEG_CLK# CLK_CPU_DMI# 14
PAD @ SKTOCC#_R AH24 CLK_CPU_DP_R R561 1 DIS only@
2 0_0402_5%
T5 SKTOCC#
A18 CLK_CPU_DP_R R563 1 UMA@ 2 0_0402_5% CLK_CPU_DP#_R R569 1 DIS only@
2 0_0402_5%
DPLL_REF_SSCLK CLK_CPU_DP 14
D A17 CLK_CPU_DP#_R R568 1 UMA@ 2 0_0402_5% D
DPLL_REF_SSCLK# CLK_CPU_DP# 14
H_CATERR# AK14 CATERR# +1.1VS_VTT

THERMAL
SM_DRAMRST# F6 SM_DRAMRST# 11
R595 1 2 H_PECI_R AT15 XDP_PRDY# R147 1 @ 2 51_0402_5%
18 H_PECI PECI
0_0402_5% AL1 SM_RCOMP_0 XDP_TMS R38 1 @ 2 51_0402_5%
SM_RCOMP[0] SM_RCOMP_1 +1.1VS_VTT XDP_TDI_R R537 @ 51_0402_5%
SM_RCOMP[1] AM1 1 2
AN1 SM_RCOMP_2 XDP_PREQ# R152 1 @ 2 51_0402_5%
H_PROCHOT# SM_RCOMP[2] R591 1
55 H_PROCHOT# AN26 PROCHOT# 2 10K_0402_5% XDP_TCLK R446 1 @ 2 51_0402_5%
AN15 PM_EXTTS#0 R586 1 2 10K_0402_5%
PM_EXT_TS#[0]

DDR3
MISC
AP15 PM_EXTTS#1_R R594 1 2 0_0402_5%
PM_EXT_TS#[1] PM_EXTTS#0_1 10,11
R211 1 2 H_THERMTRIP#_R AK15
18 H_THERMTRIP# THERMTRIP#
0_0402_5%
XDP_TRST# R145 1 2 51_0402_5%
AT28 XDP_PRDY#
PRDY# XDP_PREQ#
PREQ# AP27

AN28 XDP_TCLK
H_CPURST# TCK XDP_TMS
AP26 RESET_OBS# TMS AP28

PWR MANAGEMENT
AT27 XDP_TRST#
TRST# XDP_TDI_R R525 1 2 0_0402_5% XDP_TDI

JTAG & BPM

R212 1 2 H_PM_SYNC_R AL15 AT29 XDP_TDI_R XDP_TDO_M R514 1 @ 2 0_0402_5% XDP_TDO
15 H_PM_SYNC PM_SYNC TDI
0_0402_5% AR27 XDP_TDO_R
TDO

1
AR29 XDP_TDI_M
R215 1 H_CPUPW RGD_1 TDI_M XDP_TDO_M R522
2 AN14 VCCPWRGOOD_1 TDO_M AP29
0_0402_5% 0_0402_5%
AN25 XDP_DBR#_R R151 1 2 0_0402_5% XDP_DBRESET# XDP_DBRESET# 15
C R210 1 H_CPUPW RGD_0 DBR# C
18 H_CPUPW RGD 2 AN27

2
0_0402_5% VCCPWRGOOD_0 XDP_TDI_M 1 @ 2
AJ22 XDP_OBS0 XDP_TDO_R R524 1 2 0_0402_5%
R216 1 PM_DRAM_PW RGD_R BPM#[0] XDP_OBS1 R150 0_0402_5%
15 PM_DRAM_PW RGD 2 AK13 SM_DRAMPWROK BPM#[1] AK22
0_0402_5% AK24 XDP_OBS2
BPM#[2] XDP_OBS3
BPM#[3] AJ24
PM_DRAM_PW RGD_R 1 @ 2 CPU_VTTPW RGD AM15 AJ25 XDP_OBS4
VTTPWRGOOD BPM#[4]
R742 0_0402_5%
BPM#[5] AH22 XDP_OBS5 JTAG MAPPING
AK23 XDP_OBS6
H_PW RGD_XDP R452 1 H_PW RGD_XDP_R BPM#[6] XDP_OBS7
2 AM26 TAPPWRGOOD BPM#[7] AH23
0_0402_5% Scan Chain STUFF -> R653, R657, R662
(Default) NO STUFF -> R655, R660
17,33,37 PLT_RST#
R181 1 2 PLT_RST#_R AL14 2009/2/4
RSTIN#
1.5K_0402_1% Delete dampling resistor for
power noise and Layout space CPU Only STUFF -> R653, R655
1

2009/2/4 issue NO STUFF -> R657, R660, R662

#414044 DG R182 IC,AUB_CFD_rPGA,R1P0
Update Rev1.11 750_0402_1% CONN@
GMCH Only STUFF -> R660, R662
NO STUFF -> R653, R655, R657
2

+3VS
2009/4/13
Intel Suggestion by Desige guide V1.52 JP5
XDP Connector
5

1 GND0 GND1 2
Test: R746 2 H_VTTPW RGD XDP_PREQ# 3 4
P

B CPU_VTTPW RGD B XDP_PRDY# OBSFN_A0 OBSFN_C0 B

1 2 4 5 6
1. change R203 to 750 ohm Y
1 7
OBSFN_A1 OBSFN_C1
8
A GND2 GND3
G
2

2. del R217 2K_0402_5% XDP_OBS0 9 OBSDATA_A0 OBSDATA_C0 10

NC7SZ08P5X_NL_SC70-5 XDP_OBS1 11 12
3. pop R736
3

+1.5V +1.5V_CPU R747 OBSDATA_A1 OBSDATA_C1

U48 13 GND4 GND5 14
1K_0402_1% XDP_OBS2 15 16
XDP_OBS3 OBSDATA_A2 OBSDATA_C2
17 18
1

OBSDATA_A3 OBSDATA_C3
19 GND6 GND7 20
1

+3VS 21 22
R217 R735 OBSFN_B0 OBSFN_D0
23 OBSFN_B1 OBSFN_D1 24
1.1K_0402_1% @ 1.1K_0402_1% 25 26 R49
non S3@ XDP_OBS4 GND8 GND9 1K_0402_5%
27 OBSDATA_B0 OBSDATA_D0 28
5

XDP_OBS5 29 30 1 XDP@ 2 H_CPURST#

2

H_VTTPW RGD OBSDATA_B1 OBSDATA_D1 H_RESET#_R

2 31 32 1 @ 2 PLT_RST#
P

B H_VTTPW RGD 53 GND10 GND11

PM_DRAM_PW RGD_R 1 S3@ 2 4 XDP_OBS6 33 34 R50
R736 1.5K_0402_1% Y R457 XDP_OBS7 OBSDATA_B2 OBSDATA_D2 0_0402_5%
A 1 35 OBSDATA_B3 OBSDATA_D3 36
G

1K_0402_5% 37 38
GND12 GND13
1

NC7SZ08P5X_NL_SC70-5 H_CPUPW RGD 1 XDP@ 2 H_PW RGOOD_R 39 40 CLK_CPU_XDP

3

C713 R203 S3@ PWRGOOD/HOOK0 ITPCLK/HOOK4

1 U46 15,37 PBTN_OUT# 1 XDP@ 2 PBTN_OUT#_XDP 41 HOOK1 ITPCLK#/HOOK5 42 CLK_CPU_XDP#
0.1U_0402_16V4Z 3K_0402_1% +1.1VS_VTT R455 0_0402_5% 43 44 +1.1VS_VTT
@ non S3@ H_PW RGD_XDP VCC_OBS_AB VCC_OBS_CD H_RESET#_R
45 HOOK2 RESET#/HOOK6 46
+1.1VS_VTT C435 47 48 XDP_DBRESET# 1 XDP@ 2 R46 Leakage Issue
1 +3VS
2

2 0.1U_0402_16V4Z HOOK3 DBR#/HOOK7 1K_0402_5%

49 GND14 GND15 50
@ 51 52 XDP_TDO 1 XDP@ 2 R43 +1.1VS_VTT
12 XDP_SDATA SDA TD0
H_CATERR# R204 1 2 49.9_0402_1% 53 54 XDP_TRST# 51_0402_5%
2 12 XDP_SCLK SCL TRST#
H_PROCHOT# R155 1 2 68_0402_5% 55 56 XDP_TDI
H_CPURST# R156 1 @ TCK1 TDI
2 68_0402_5% XDP_TCLK 57 TCK0 TMS 58 XDP_TMS
59 GND16 GND17 60
A A
H_COMP0 R526 1 2 49.9_0402_1% CONN@ SAMTE_BSH-030-01-L-D-A
H_COMP1 R179 1 2 49.9_0402_1%
H_COMP2 R541 1 2 20_0402_1%
R203 H_COMP3 R544 1 2 20_0402_1%

S3@
Security Classification Compal Secret Data Compal Electronics, Inc.
SD034750080 Issued Date 2009/5/12 2010/04/15 Title
SM_RCOMP_0 R636 1 Deciphered Date
2 100_0402_1%
750_0402_1% SM_RCOMP_1 R632 1 2 24.9_0402_1% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (2/6) CLK,JTAG
SM_RCOMP_2 R629 1 2 130_0402_1% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 5 of 60
5 4 3 2 1
 5 4 3 2 1

JCPU1D
11 DDR_B_D[0..63]
11 DDR_B_DM[0..7]
JCPU1C
10 DDR_A_D[0..63] 11 DDR_B_DQS#[0..7]
10 DDR_A_DM[0..7] 11 DDR_B_DQS[0..7]
10 DDR_A_DQS#[0..7] 11 DDR_B_MA[0..15]
10 DDR_A_DQS[0..7]
10 DDR_A_MA[0..15] SB_CK[0] W8 DDR_B_CLK0 11
SB_CK#[0] W9 DDR_B_CLK0# 11
AA6 DDR_B_D0 B5 M3
SA_CK[0] DDR_A_CLK0 10 SB_DQ[0] SB_CKE[0] DDR_B_CKE0 11
AA7 DDR_B_D1 A5
SA_CK#[0] DDR_A_CLK0# 10 SB_DQ[1]
P7 DDR_B_D2 C3
SA_CKE[0] DDR_A_CKE0 10 SB_DQ[2]
DDR_A_D0 A10 DDR_B_D3 B3 V7
SA_DQ[0] SB_DQ[3] SB_CK[1] DDR_B_CLK1 11
DDR_A_D1 C10 DDR_B_D4 E4 V6
SA_DQ[1] SB_DQ[4] SB_CK#[1] DDR_B_CLK1# 11
D DDR_A_D2 C7 DDR_B_D5 A6 M2 D
SA_DQ[2] SB_DQ[5] SB_CKE[1] DDR_B_CKE1 11
DDR_A_D3 A7 Y6 DDR_B_D6 A4
SA_DQ[3] SA_CK[1] DDR_A_CLK1 10 SB_DQ[6]
DDR_A_D4 B10 Y5 DDR_B_D7 C4
SA_DQ[4] SA_CK#[1] DDR_A_CLK1# 10 SB_DQ[7]
DDR_A_D5 D10 P6 DDR_B_D8 D1
SA_DQ[5] SA_CKE[1] DDR_A_CKE1 10 SB_DQ[8]
DDR_A_D6 E10 DDR_B_D9 D2
DDR_A_D7 SA_DQ[6] DDR_B_D10 SB_DQ[9]
A8 SA_DQ[7] F2 SB_DQ[10] SB_CS#[0] AB8 DDR_B_CS0# 11
DDR_A_D8 D8 DDR_B_D11 F1 AD6
SA_DQ[8] SB_DQ[11] SB_CS#[1] DDR_B_CS1# 11
DDR_A_D9 F10 AE2 DDR_B_D12 C2
SA_DQ[9] SA_CS#[0] DDR_A_CS0# 10 SB_DQ[12]
DDR_A_D10 E6 AE8 DDR_B_D13 F5
SA_DQ[10] SA_CS#[1] DDR_A_CS1# 10 SB_DQ[13]
DDR_A_D11 F7 DDR_B_D14 F3
DDR_A_D12 SA_DQ[11] DDR_B_D15 SB_DQ[14]
E9 SA_DQ[12] G4 SB_DQ[15] SB_ODT[0] AC7 DDR_B_ODT0 11
DDR_A_D13 B7 DDR_B_D16 H6 AD1
SA_DQ[13] SB_DQ[16] SB_ODT[1] DDR_B_ODT1 11
DDR_A_D14 E7 AD8 DDR_B_D17 G2
SA_DQ[14] SA_ODT[0] DDR_A_ODT0 10 SB_DQ[17]
DDR_A_D15 C6 AF9 DDR_B_D18 J6
SA_DQ[15] SA_ODT[1] DDR_A_ODT1 10 SB_DQ[18]
DDR_A_D16 H10 DDR_B_D19 J3
DDR_A_D17 SA_DQ[16] DDR_B_D20 SB_DQ[19]
G8 SA_DQ[17] G1 SB_DQ[20]
DDR_A_D18 K7 DDR_B_D21 G5 D4 DDR_B_DM0
DDR_A_D19 SA_DQ[18] DDR_B_D22 SB_DQ[21] SB_DM[0] DDR_B_DM1
J8 SA_DQ[19] J2 SB_DQ[22] SB_DM[1] E1
DDR_A_D20 G7 DDR_B_D23 J1 H3 DDR_B_DM2
DDR_A_D21 SA_DQ[20] DDR_B_D24 SB_DQ[23] SB_DM[2] DDR_B_DM3
G10 SA_DQ[21] J5 SB_DQ[24] SB_DM[3] K1
DDR_A_D22 J7 B9 DDR_A_DM0 DDR_B_D25 K2 AH1 DDR_B_DM4
DDR_A_D23 SA_DQ[22] SA_DM[0] DDR_A_DM1 DDR_B_D26 SB_DQ[25] SB_DM[4] DDR_B_DM5
J10 SA_DQ[23] SA_DM[1] D7 L3 SB_DQ[26] SB_DM[5] AL2
DDR_A_D24 L7 H7 DDR_A_DM2 DDR_B_D27 M1 AR4 DDR_B_DM6
DDR_A_D25 SA_DQ[24] SA_DM[2] DDR_A_DM3 DDR_B_D28 SB_DQ[27] SB_DM[6] DDR_B_DM7
M6 SA_DQ[25] SA_DM[3] M7 K5 SB_DQ[28] SB_DM[7] AT8
DDR_A_D26 M8 AG6 DDR_A_DM4 DDR_B_D29 K4
DDR_A_D27 SA_DQ[26] SA_DM[4] DDR_A_DM5 DDR_B_D30 SB_DQ[29]
L9 SA_DQ[27] SA_DM[5] AM7 M4 SB_DQ[30]
DDR_A_D28 L6 AN10 DDR_A_DM6 DDR_B_D31 N5
DDR_A_D29 SA_DQ[28] SA_DM[6] DDR_A_DM7 DDR_B_D32 SB_DQ[31]
K8 SA_DQ[29] SA_DM[7] AN13 AF3 SB_DQ[32]
DDR_A_D30 N8 DDR_B_D33 AG1
C DDR_A_D31 SA_DQ[30] DDR_B_D34 SB_DQ[33] DDR_B_DQS#0 C
P9 SA_DQ[31] AJ3 SB_DQ[34] SB_DQS#[0] D5
DDR_A_D32 AH5 DDR_B_D35 AK1 F4 DDR_B_DQS#1
DDR_A_D33 SA_DQ[32] DDR_B_D36 SB_DQ[35] SB_DQS#[1] DDR_B_DQS#2
AF5 SA_DQ[33] AG4 SB_DQ[36] SB_DQS#[2] J4
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D37 AG3 L4 DDR_B_DQS#3
SA_DQ[34] SA_DQS#[0] SB_DQ[37] SB_DQS#[3]
DDR SYSTEM MEMORY A

DDR_A_D35 AK7 F8 DDR_A_DQS#1 DDR_B_D38 AJ4 AH2 DDR_B_DQS#4

SA_DQ[35] SA_DQS#[1] SB_DQ[38] SB_DQS#[4]

DDR SYSTEM MEMORY - B

DDR_A_D36 AF6 J9 DDR_A_DQS#2 DDR_B_D39 AH4 AL4 DDR_B_DQS#5
DDR_A_D37 SA_DQ[36] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D40 SB_DQ[39] SB_DQS#[5] DDR_B_DQS#6
AG5 SA_DQ[37] SA_DQS#[3] N9 AK3 SB_DQ[40] SB_DQS#[6] AR5
DDR_A_D38 AJ7 AH7 DDR_A_DQS#4 DDR_B_D41 AK4 AR8 DDR_B_DQS#7
DDR_A_D39 SA_DQ[38] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D42 SB_DQ[41] SB_DQS#[7]
AJ6 SA_DQ[39] SA_DQS#[5] AK9 AM6 SB_DQ[42]
DDR_A_D40 AJ10 AP11 DDR_A_DQS#6 DDR_B_D43 AN2
DDR_A_D41 SA_DQ[40] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D44 SB_DQ[43]
AJ9 SA_DQ[41] SA_DQS#[7] AT13 AK5 SB_DQ[44]
DDR_A_D42 AL10 DDR_B_D45 AK2
DDR_A_D43 SA_DQ[42] DDR_B_D46 SB_DQ[45]
AK12 SA_DQ[43] AM4 SB_DQ[46]
DDR_A_D44 AK8 DDR_B_D47 AM3
DDR_A_D45 SA_DQ[44] DDR_B_D48 SB_DQ[47] DDR_B_DQS0
AL7 SA_DQ[45] AP3 SB_DQ[48] SB_DQS[0] C5
DDR_A_D46 AK11 C8 DDR_A_DQS0 DDR_B_D49 AN5 E3 DDR_B_DQS1
DDR_A_D47 SA_DQ[46] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[1] DDR_B_DQS2
AL8 SA_DQ[47] SA_DQS[1] F9 AT4 SB_DQ[50] SB_DQS[2] H4
DDR_A_D48 AN8 H9 DDR_A_DQS2 DDR_B_D51 AN6 M5 DDR_B_DQS3
DDR_A_D49 SA_DQ[48] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[3] DDR_B_DQS4
AM10 SA_DQ[49] SA_DQS[3] M9 AN4 SB_DQ[52] SB_DQS[4] AG2
DDR_A_D50 AR11 AH8 DDR_A_DQS4 DDR_B_D53 AN3 AL5 DDR_B_DQS5
DDR_A_D51 SA_DQ[50] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[5] DDR_B_DQS6
AL11 SA_DQ[51] SA_DQS[5] AK10 AT5 SB_DQ[54] SB_DQS[6] AP5
DDR_A_D52 AM9 AN11 DDR_A_DQS6 DDR_B_D55 AT6 AR7 DDR_B_DQS7
DDR_A_D53 SA_DQ[52] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[7]
AN9 SA_DQ[53] SA_DQS[7] AR13 AN7 SB_DQ[56]
DDR_A_D54 AT11 DDR_B_D57 AP6
DDR_A_D55 SA_DQ[54] DDR_B_D58 SB_DQ[57]
AP12 SA_DQ[55] AP8 SB_DQ[58]
DDR_A_D56 AM12 DDR_B_D59 AT9
DDR_A_D57 SA_DQ[56] DDR_B_D60 SB_DQ[59]
AN12 SA_DQ[57] AT7 SB_DQ[60]
DDR_A_D58 AM13 Y3 DDR_A_MA0 DDR_B_D61 AP9
DDR_A_D59 SA_DQ[58] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61]
AT14 SA_DQ[59] SA_MA[1] W1 AR10 SB_DQ[62]
B DDR_A_D60 DDR_A_MA2 DDR_B_D63 DDR_B_MA0 B
AT12 SA_DQ[60] SA_MA[2] AA8 AT10 SB_DQ[63] SB_MA[0] U5
DDR_A_D61 AL13 AA3 DDR_A_MA3 V2 DDR_B_MA1
DDR_A_D62 SA_DQ[61] SA_MA[3] DDR_A_MA4 SB_MA[1] DDR_B_MA2
AR14 SA_DQ[62] SA_MA[4] V1 SB_MA[2] T5
DDR_A_D63 AP14 AA9 DDR_A_MA5 V3 DDR_B_MA3
SA_DQ[63] SA_MA[5] DDR_A_MA6 SB_MA[3] DDR_B_MA4
SA_MA[6] V8 SB_MA[4] R1
T1 DDR_A_MA7 DDR_B_BS0 AB1 T8 DDR_B_MA5
SA_MA[7] 11 DDR_B_BS0 SB_BS[0] SB_MA[5]
Y9 DDR_A_MA8 DDR_B_BS1 W5 R2 DDR_B_MA6
SA_MA[8] 11 DDR_B_BS1 SB_BS[1] SB_MA[6]
DDR_A_BS0 AC3 U6 DDR_A_MA9 DDR_B_BS2 R7 R6 DDR_B_MA7
10 DDR_A_BS0 SA_BS[0] SA_MA[9] 11 DDR_B_BS2 SB_BS[2] SB_MA[7]
DDR_A_BS1 AB2 AD4 DDR_A_MA10 R4 DDR_B_MA8
10 DDR_A_BS1 SA_BS[1] SA_MA[10] SB_MA[8]
DDR_A_BS2 U7 T2 DDR_A_MA11 R5 DDR_B_MA9
10 DDR_A_BS2 SA_BS[2] SA_MA[11] SB_MA[9]
U3 DDR_A_MA12 DDR_B_CAS# AC5 AB5 DDR_B_MA10
SA_MA[12] 11 DDR_B_CAS# SB_CAS# SB_MA[10]
AG8 DDR_A_MA13 DDR_B_RAS# Y7 P3 DDR_B_MA11
SA_MA[13] 11 DDR_B_RAS# SB_RAS# SB_MA[11]
T3 DDR_A_MA14 11 DDR_B_W E# DDR_B_W E# AC6 R3 DDR_B_MA12
DDR_A_CAS# SA_MA[14] DDR_A_MA15 SB_WE# SB_MA[12] DDR_B_MA13
10 DDR_A_CAS# AE1 SA_CAS# SA_MA[15] V9 SB_MA[13] AF7
DDR_A_RAS# AB3 P5 DDR_B_MA14
10 DDR_A_RAS# SA_RAS# SB_MA[14]
10 DDR_A_W E# DDR_A_W E# AE9 N1 DDR_B_MA15
SA_WE# SB_MA[15]

IC,AUB_CFD_rPGA,R1P0
CONN@
IC,AUB_CFD_rPGA,R1P0
A
CONN@ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (3/6) DDRIII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 6 of 60
5 4 3 2 1
 5 4 3 2 1

JCPU1F

WW15 MOW
+CPU_CORE
Peak 21A +1.1VS_VTT
48A Continuous 18A
10U_0805_6.3V6M
AG35 AH14 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC1 VTT0_1
AG34 VCC2 VTT0_2 AH12
AG33 AH11 +CPU_CORE
VCC3 VTT0_3
AG32 VCC4 VTT0_4 AH10 1 1 1 1 1 1 1
D C228 C209 C222 C226 C224 C212 C204 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M D
AG31 VCC5 VTT0_5 J14
AG30 VCC6 VTT0_6 J13
AG29 VCC7 VTT0_7 H14 1 1 1 1 1 1 1 1 1
AG28 H12 2 2 2 2 2 2 2 C185 C195 C203 C207 C217 C196 C187 C202 C218
VCC8 VTT0_8
AG27 G14
VCC9 VTT0_9 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AG26 VCC10 VTT0_10 G13
AF35 G12 10U_0805_6.3V6M 2 2 2 2 2 2 2 2 2
VCC11 VTT0_11
AF34 VCC12 VTT0_12 G11
AF33 F14 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC13 VTT0_13
AF32
VCC14 VTT0_14
F13 (Place these capacitors between inductor and socket on Bottom)
AF31 VCC15 VTT0_15 F12
AF30 F11 +1.1VS_VTT
VCC16 VTT0_16 +CPU_CORE
AF29 VCC17 VTT0_17 E14
AF28 E12 330U_X_2VM_R6M
VCC18 VTT0_18 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AF27 D14 1 1 1
VCC19 VTT0_19
AF26 D13
VCC20 VTT0_20 + + +

1.1V RAIL POWER

AD35 D12 C250 C248 C249 1 1 1 1 1 1 1
VCC21 VTT0_21 @ C220 C216 C192 C221 C208 C191 C219
AD34 D11
VCC22 VTT0_22
AD33 VCC23 VTT0_23 C14
AD32 C13 2 2 2
VCC24 VTT0_24 2 2 2 2 2 2 2
AD31 C12
VCC25 VTT0_25 330U_X_2VM_R6M 330U_X_2VM_R6M
AD30 C11
VCC26 VTT0_26 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AD29 VCC27 VTT0_27 B14
AD28 VCC28 VTT0_28 B12 (Place these capacitors under CPU socket, top layer)
AD27 A14
VCC29 VTT0_29
AD26 VCC30 VTT0_30 A13 CSC (Current Sense Configuration)
AC35
VCC31 VTT0_31
A12 8/25 +1.1VS_VTT
AC34 A11
VCC32 VTT0_32
AC33 VCC33
AC32 +1.1VS_VTT
VCC34 CPU_VID0 R412 1
AC31 2 1K_0402_1%
VCC35 22U_0805_6.3V6M R413 1 @
AC30 AF10 2 1K_0402_1%
C VCC36 VTT0_33 C
AC29 VCC37 VTT0_34 AE10
AC28 AC10 CPU_VID1 R415 1 2 1K_0402_1% +CPU_CORE
VCC38 VTT0_35 1 1
CPU CORE SUPPLY

AC27 AB10 C231 C232 R416 1 @ 2 1K_0402_1%

VCC39 VTT0_36 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AC26 VCC40 VTT0_37 Y10
AA35 W10 CPU_VID2 R419 1 2 1K_0402_1%
VCC41 VTT0_38 2 2 R420 1 @
AA34 U10 2 1K_0402_1% 1 1 1 1 1 1
VCC42 VTT0_39 22U_0805_6.3V6M C502 C500 C501 C499 C498 C497
AA33 VCC43 VTT0_40 T10
AA32 J12 CPU_VID3 R422 1 @ 2 1K_0402_1%
VCC44 VTT0_41 R423 1
AA31 VCC45 VTT0_42 J11 2 1K_0402_1%
AA30 J16 2 2 2 2 2 2
VCC46 VTT0_43 CPU_VID4 R425 1 @
AA29 VCC47 VTT0_44 J15 2 1K_0402_1%
AA28 R426 1 2 1K_0402_1% 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC48
AA27 VCC49 (Place these capacitors on CPU cavity, Bottom Layer)
AA26 CPU_VID5 R428 1 2 1K_0402_1%
VCC50 R429 1 @
Y35 2 1K_0402_1%
VCC51
Y34
VCC52 CPU_VID6 R432 1 @
Y33 2 1K_0402_1%
VCC53 R433 1 +CPU_CORE
Y32 2 1K_0402_1%
VCC54
Y31
VCC55 H_DPRSLPVR R435 1
Y30 VCC56 2 1K_0402_1% 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
Y29 R436 1 @ 2 1K_0402_1%
VCC57
Y28 1 1 1 1 1 1
VCC58 H_PSI# R437 1 @
Y27 2 1K_0402_1% C524 C529 C528 C527 C526 C525
VCC59 R438 1
Y26 2 1K_0402_1%
VCC60
V35 AN33 H_PSI# 55
VCC61 PSI# 2 2 2 2 2 2
V34
POWER

VCC62
V33 VCC63
V32 AK35 CPU_VID0 55 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC64 VID[0]
V31
VCC65 VID[1]
AK33 CPU_VID1 55 (Place these capacitors on CPU cavity, Bottom Layer)
V30 AK34 CPU_VID2 55
VCC66 VID[2]
V29 AL35 CPU_VID3 55
VCC67 VID[3]
CPU VIDS

V28 AL33 CPU_VID4 55

B VCC68 VID[4] B
V27 VCC69 VID[5] AM33 CPU_VID5 55
V26 VCC70 VID[6] AM35 CPU_VID6 55
U35 AM34 H_DPRSLPVR 55
VCC71 PROC_DPRSLPVR
U34 VCC72
U33
VCC73
U32
VCC74 H_VTTVID1
U31 G15 H_VTTVID1 53
VCC75 VTT_SELECT
U30
VCC76
U29
VCC77
U28 VCC78
H_VTTVID1 = low, 1.1V VTT Rail
U27 pop 330u 6mohm p/n: SGA00001Q80
VCC79 +CPU_CORE
U26
VCC80
H_VTTVID1 = high, 1.05V
R35 VCC81 Auburndale +1.1VS_VTT=1.05V 4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)
R34
R33
VCC82 Clarksfield +1.1VS_VTT=1.1V 1 1 1 1 1 1
VCC83
R32 AN35 IMVP_IMON 55
VCC84 ISENSE C165 + C171 + C172 + C173 + C170 + C174 +
R31
VCC85
R30 1 2 +CPU_CORE
VCC86 R464 100_0402_1% 330U_X_2VM_R6M @ @
R29
VCC87 VCCSENSE_R R466 1 VCCSENSE 2 2 3 2 3 2 3 2 3 2 3
2 0_0402_5%
SENSE LINES

R28 AJ34 VCCSENSE 55

VCC88 VCC_SENSE VSSSENSE_R R465 1 VSSSENSE
R27 AJ35 2 0_0402_5% VSSSENSE 55
VCC89 VSS_SENSE 470U_D2T_2VM~D 470U_D2T_2VM~D 470U_D2T_2VM~D 470U_D2T_2VM~D 470U_D2T_2VM~D
R26 VCC90
P35
VCC91
1 2 TOP side (under inductor)
P34 B15 R463 100_0402_1%
VCC92 VTT_SENSE VSS_SENSE_VTT VTT_SENSE 53
P33 A15
VCC93 VSS_SENSE_VTT R585 1
P32 2 0_0402_5%
VCC94
P31 VCC95
P30
VCC96
P29
VCC97 +CPU-CORE C,uF ESR, mohm Stuffing Option
P28
P27
VCC98 Decoupling
VCC99
A
P26 VCC100 SPCAP,Polymer 4X330uF 6m ohm/4 4X330uF A

16X22uF 3m ohm/12
MLCC 0805 X5R
16X10uF 3m ohm/16

IC,AUB_CFD_rPGA,R1P0 Security Classification Compal Secret Data Compal Electronics, Inc.

CONN@ Issued Date 2009/5/12 2010/04/15 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (4/6) PWR,Bypass
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 7 of 60
5 4 3 2 1
 5 4 3 2 1

PJ27 @
+1.5V_CPU 2 2 1 1 +1.5VS
JUMP_43X118
+VGFX_CORE PJ28 @
JCPU1G 2 2
22U_0805_6.3V6M 10U_0805_6.3V6M 1 1
22U_0805_6.3V6M 22U_0805_6.3V6M AT21 JUMP_43X118
VAXG1
AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_SENSE 54

SENSE
LINES
1 1 1 1 1 1 1 1 AT18 VAXG3 VSSAXG_SENSE AT22 VSS_AXG_SENSE 54
C200 C199 C215 C214 C213 C198 C507 C523 AT16
@ @ @ @ VAXG4 PJ29 @
D AR21 VAXG5 D
UMA@ UMA@ UMA@ UMA@ AR19 2 1 +1.5V
2 2 2 2 2 2 2 2 VAXG6 2 1
AR18 VAXG7
AR16 AM22 JUMP_43X118
VAXG8 GFX_VID[0] GFXVR_VID_0 54
AP21 VAXG9 GFX_VID[1] AP22 GFXVR_VID_1 54

GRAPHICS VIDs
22U_0805_6.3V6M 22U_0805_6.3V6M AP19 AN22 PJ30 @
VAXG10 GFX_VID[2] GFXVR_VID_2 54
22U_0805_6.3V6M 10U_0805_6.3V6M AP18 AP23 2 1
VAXG11 GFX_VID[3] GFXVR_VID_3 54 2 1
AP16 VAXG12 15A GFX_VID[4] AM23 GFXVR_VID_4 54
JUMP_43X118
1 1 AN21 VAXG13 GFX_VID[5] AP24 GFXVR_VID_5 54

GRAPHICS
AN19 VAXG14 GFX_VID[6] AN24 GFXVR_VID_6 54
+ + R549 AN18 1 @ 2
C205 C206 VAXG15 R739 4.7K_0402_5%
0_0402_5% AN16 VAXG16
330U_X_2VM_R6M @ DIS only@ AM21 AR25
2 2 VAXG17 GFX_VR_EN GFXVR_EN 54
UMA@ AM19 AT25 GFXVR_DPRSLPVR_R R536 1 2 0_0402_5% GFXVR_DPRSLPVR 54

2
330U_X_2VM_R6M VAXG18 GFX_DPRSLPVR +1.5V_CPU
AM18 VAXG19 GFX_IMON AM24 GFXVR_IMON 54
AM16 VAXG20
AL21 VAXG21 1 DIS only@2
AL19 R146 1K_0402_5%
VAXG22
AL18 VAXG23
AL16 VAXG24
AK21 AJ1 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M
VAXG25 VDDQ1
AK19 VAXG26 VDDQ2 AF1 1
AK18 AE7 1 1 1 1 1 1 1

- 1.5V RAILS
VAXG27 VDDQ3 C252 C259 C253 C251 C262 C271 C258 + C269
AK16 VAXG28 VDDQ4 AE4
AJ21 AC1 330U_X_2VM_R6M
VAXG29 VDDQ5
AJ19 VAXG30 VDDQ6 AB7
2 2 2 2 2 2 2 2
AJ18 VAXG31 VDDQ7 AB4
AJ16 VAXG32 3A VDDQ8 Y1
AH21 VAXG33 VDDQ9 W7

POWER
C AH19 W4 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z C
VAXG34 VDDQ10 22U_0805_6.3V6M
AH18 VAXG35 VDDQ11 U1
AH16 VAXG36 VDDQ12 T7
VDDQ13 T4
VDDQ14 P1
+1.1VS_VTT N7
VDDQ15
VDDQ16 N4

DDR3
VDDQ17 L1
J24 VTT1_45 VDDQ18 H1

FDI
J23 VTT1_46
1 1 H25 VTT1_47
C233 C234 +1.1VS_VTT

22U_0805_6.3V6M 22U_0805_6.3V6M P10

2 2 VTT0_59
VTT0_60 N10
VTT0_61 L10 1
K10 C235
VTT0_62
+1.1VS_VTT 10U_0805_6.3V6M
2
+1.1VS_VTT

1.1V
VTT1_63 J22
K26 VTT1_48 VTT1_64 J20
J27 VTT1_49 VTT1_65 J18 1

PEG & DMI

1 1 J26 H21 C236
C237 C238 VTT1_50 VTT1_66
J25 VTT1_51 VTT1_67 H20
H27 H19 22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M VTT1_52 VTT1_68 2
G28 VTT1_53
2 2
G27 VTT1_54
B B
G26 VTT1_55
F26 +1.8VS
VTT1_56
E26 VTT1_57 VCCPLL1 L26

1.8V
E25 VTT1_58 0.6A VCCPLL2 L27
+1.8VS_VCCSFR 2.2U_0603_6.3V6K
VCCPLL3 M26 1 2
R157 0_0805_5%
1 1 1 1 1
C189 C186 C197 C193 C194

1U_0402_6.3V4Z
2 2 2 2 2 22U_0805_6.3V6M

IC,AUB_CFD_rPGA,R1P0 1U_0402_6.3V4Z 4.7U_0805_10V4Z

CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (5/6) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 8 of 60
5 4 3 2 1
 5 4 3 2 1

JCPU1H JCPU1I

AT20 VSS1 VSS81 AE34

AT17 VSS2 VSS82 AE33
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162
AR26 VSS5 VSS85 AE30 K6 VSS163
AR24 VSS6 VSS86 AE29 K3 VSS164
D AR23 VSS7 VSS87 AE28 J32 VSS165 D
AR20 VSS8 VSS88 AE27 J30 VSS166
AR17 VSS9 VSS89 AE26 J21 VSS167
AR15 VSS10 VSS90 AE6 J19 VSS168
AR12 VSS11 VSS91 AD10 H35 VSS169
AR9 VSS12 VSS92 AC8 H32 VSS170
AR6 VSS13 VSS93 AC4 H28 VSS171
AR3 VSS14 VSS94 AC2 H26 VSS172
AP20 VSS15 VSS95 AB35 H24 VSS173
AP17 VSS16 VSS96 AB34 H22 VSS174
AP13 VSS17 VSS97 AB33 H18 VSS175
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177
AP4 VSS20 VSS100 AB30 H11 VSS178
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181
AN23 VSS24 VSS104 AB26 G34 VSS182
AN20 VSS25 VSS105 AB6 G31 VSS183
AN17 VSS26 VSS106 AA10 G20 VSS184
AM29 VSS27 VSS107 Y8 G9 VSS185
AM27 VSS28 VSS108 Y4 G6 VSS186
AM25 VSS29 VSS109 Y2 G3 VSS187
AM20 VSS30 VSS110 W35 F30 VSS188
AM17 VSS31 VSS111 W34 F27 VSS189
AM14 VSS32 VSS112 W33 F25 VSS190
AM11 VSS33 VSS113 W32 F22 VSS191
AM8 VSS34 VSS114 W31 F19 VSS192
AM5 VSS35 VSS115 W30 F16 VSS193
C AM2 W29 E35 C
VSS36 VSS116 VSS194
AL34 W28 E32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E29
E24
VSS195
VSS196
VSS197
VSS
AL20 VSS40 VSS120 W6 E21 VSS198
AL17 VSS41 VSS121 V10 E18 VSS199
AL12 VSS42 VSS122 U8 E13 VSS200
AL9 VSS43 VSS123 U4 E11 VSS201
AL6 VSS44 VSS124 U2 E8 VSS202
AL3 VSS45 VSS125 T35 E5 VSS203
AK29 T34 E2 AT35 H_NCTF1 @ PAD T14
VSS46 VSS126 VSS204 VSS_NCTF1 H_NCTF2 @
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1 PAD T19
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34
AK17 T30 D9 B2

NCTF
VSS50 VSS130 VSS208 VSS_NCTF5 H_NCTF6 @
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1 PAD T18
AJ23 T28 D3 A35 H_NCTF7 @ PAD T13
VSS52 VSS132 VSS210 VSS_NCTF7
AJ20 VSS53 VSS133 T27 C34 VSS211
AJ17 VSS54 VSS134 T26 C32 VSS212
AJ14 VSS55 VSS135 T6 C29 VSS213
AJ11 VSS56 VSS136 R10 C28 VSS214
AJ8 VSS57 VSS137 P8 C24 VSS215
AJ5 VSS58 VSS138 P4 C22 VSS216
AJ2 VSS59 VSS139 P2 C20 VSS217
AH35 VSS60 VSS140 N35 C19 VSS218
AH34 VSS61 VSS141 N34 C16 VSS219
AH33 VSS62 VSS142 N33 B31 VSS220
AH32 VSS63 VSS143 N32 B25 VSS221
AH31 VSS64 VSS144 N31 B21 VSS222
B B
AH30 VSS65 VSS145 N30 B18 VSS223
AH29 VSS66 VSS146 N29 B17 VSS224
AH28 VSS67 VSS147 N28 B13 VSS225
AH27 VSS68 VSS148 N27 B11 VSS226
AH26 VSS69 VSS149 N26 B8 VSS227
AH20 VSS70 VSS150 N6 B6 VSS228
AH17 VSS71 VSS151 M10 B4 VSS229
AH13 VSS72 VSS152 L35 A29 VSS230
AH9 VSS73 VSS153 L32 A27 VSS231
AH6 VSS74 VSS154 L29 A23 VSS232
AH3 VSS75 VSS155 L8 A9 VSS233
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2
AF4 VSS78 VSS158 K34
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30

IC,AUB_CFD_rPGA,R1P0 IC,AUB_CFD_rPGA,R1P0
CONN@ CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (6/6) VSS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V

JDIMM1
+1.5V 6 DDR_A_DQS#[0..7]
H_DIMMA_REF R324 1 @ 2 0_0402_5% VREF_DQA 1 2
4 H_DIMMA_REF VREF_DQ VSS
6 DDR_A_D[0..63] 3 4 DDR_A_D4
DDR_A_D0 VSS DQ4 DDR_A_D5
5 DQ0 DQ5 6

1
DDR_A_D1 7 8
6 DDR_A_DM[0..7] DQ1 VSS DDR_A_DQS#0
R312 +V_DDR3_DIMM_REF R325 1 2 0_0402_5% 9 10
DDR_A_DM0 VSS DQS0# DDR_A_DQS0
6 DDR_A_DQS[0..7] 11 DM0 DQS0 12
1K_0402_1% +V_DDR3_DIMM_REF 13 14
DDR_A_D2 VSS VSS DDR_A_D6
6 DDR_A_MA[0..15] 15 16
2

+V_DDR3_DIMM_REF DDR_A_D3 DQ2 DQ6 DDR_A_D7

17 18
DQ3 DQ7
19 VSS VSS 20
1

DDR_A_D8 21 22 DDR_A_D12
R319 DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 DQ9 DQ13 24
D D
1 1 25 VSS VSS 26
1K_0402_1% C322 C321 DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS1# DM1 DIMM_RST#
29 30 DIMM_RST# 11
2

0.1U_0402_16V4Z 2.2U_0805_16V4Z DQS1 RESET#

31 32
2 2 DDR_A_D10 VSS VSS DDR_A_D14
33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 38
DDR_A_D16 VSS VSS DDR_A_D20
39 DQ16 DQ20 40
DDR_A_D17 41 42 DDR_A_D21
DQ17 DQ21
43 44
DDR_A_DQS#2 VSS VSS DDR_A_DM2
45 DQS2# DM2 46
DDR_A_DQS2 47 48
DQS2 VSS DDR_A_D22
49 VSS DQ22 50
DDR_A_D18 51 52 DDR_A_D23
@ Q64 DDR_A_D19 DQ18 DQ23
53 54
BSS138_NL_SOT23-3 DQ19 VSS DDR_A_D28
55 56
DDR_A_D24 VSS DQ28 DDR_A_D29
57 DQ24 DQ29 58

D
H_DIMMA_REF 3 1 VREF_DQA DDR_A_D25 59 60
DQ25 VSS

1
61 62 DDR_A_DQS#3
R738 DDR_A_DM3 VSS DQS3# DDR_A_DQS3
63 64
@ DM3 DQS3

G
100K_0402_5% 65 66

2
DDR_A_D26 VSS VSS DDR_A_D30
67 68
+V_DDR3_DIMM_REF DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 70

2
DQ27 DQ31
71 VSS VSS 72
11,18 RST_GATE
DDR_A_CKE0 73 74 DDR_A_CKE1
6 DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 6
2
0_0402_5%

75 76
+1.5V R323 VDD VDD DDR_A_MA15
77 NC A15 78
@ DDR_A_BS2 79 80 DDR_A_MA14
6 DDR_A_BS2 BA2 A14
81 82
VDD VDD
1

DDR_A_MA12 83 84 DDR_A_MA11
1

C R725 DDR_A_MA9 A12/BC# A11 DDR_A_MA7 C

85 A9 A7 86
+DDR_VREF_CA 87 88
1K_0402_1% DDR_A_MA8 VDD VDD DDR_A_MA6
89 90
DDR_A_MA5 A8 A6 DDR_A_MA4
91 92
2

DDR_VREF_CA_DIMMA 2 A5 A4
1 93 VDD VDD 94
R726 DDR_A_MA3 95 96 DDR_A_MA2
A3 A2
1

0_0402_5% DDR_A_MA1 97 98 DDR_A_MA0

R496 A1 A0
99 100
DDR_A_CLK0 VDD VDD DDR_A_CLK1
6 DDR_A_CLK0 101 CK0 CK1 102 DDR_A_CLK1 6
1K_0402_1% DDR_A_CLK0# 103 104 DDR_A_CLK1#
6 DDR_A_CLK0# CK0# CK1# DDR_A_CLK1# 6
105 106
2

DDR_A_MA10 VDD VDD DDR_A_BS1

107 108 DDR_A_BS1 6
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
6 DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# 6
111 112
DDR_A_WE# VDD VDD DDR_A_CS0#
113 114 DDR_A_CS0# 6
6 DDR_A_WE# DDR_A_CAS# WE# S0# DDR_A_ODT0
6 DDR_A_CAS# 115 116 DDR_A_ODT0 6
CAS# ODT0
117 118
DDR_A_MA13 VDD VDD DDR_A_ODT1
119 120 DDR_A_ODT1 6
DDR_A_CS1# A13 ODT1 +DDR_VREF_CA
121 122
6 DDR_A_CS1# S1# NC
123 VDD VDD 124
125 126
TEST VREF_CA
127 128
DDR_A_D32 VSS VSS DDR_A_D36
129 130
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 132
DQ33 DQ37
Layout Note: DDR_A_DQS#4
133
VSS VSS
134
DDR_A_DM4

2.2U_0603_6.3V4Z
135 136
Place near JDIMM1 DDR_A_DQS4 DQS4# DM4
137 DQS4 VSS 138 1 1
139 140 DDR_A_D38 C318 C317
DDR_A_D34 VSS DQ38 DDR_A_D39
141 142
DDR_A_D35 DQ34 DQ39
Layout Note: Place these 4 Caps near Command 143
DQ35 VSS
144
2 2
0.1U_0402_16V4Z
145 146 DDR_A_D44
and Control signals of DIMMA DDR_A_D40 147
VSS DQ44
148 DDR_A_D45
B DDR_A_D41 DQ40 DQ45 B
149 DQ41 VSS 150
+1.5V 151 152 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
153 154
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DM5 DQS5
155 VSS VSS 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
1 159 160
DQ43 DQ47
1 1 1 1 1 1 1 1 1 1 161 162
C309 C310 C285 C290 C295 C311 C326 C325 C323 C324 + C300 DDR_A_D48 VSS VSS DDR_A_D52
163 164
330U_X_2VM_R6M DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 166
DQ49 DQ53
167 VSS VSS 168
2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS#6 DDR_A_DM6
169 DQS6# DM6 170
DDR_A_DQS6 171 172
DQS6 VSS DDR_A_D54
173 VSS DQ54 174
DDR_A_D50 175 176 DDR_A_D55
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_A_D51 DQ50 DQ55
177 DQ51 VSS 178
179 180 DDR_A_D60
DDR_A_D56 VSS DQ60 DDR_A_D61
181 182
DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS DDR_A_DQS#7
185 186
DDR_A_DM7 VSS DQS7# DDR_A_DQS7
187 188
DM7 DQS7
189 190
DDR_A_D58 VSS VSS DDR_A_D62
Layout Note: DDR_A_D59
191 DQ58 DQ62 192
DDR_A_D63
193 194
Place near JDIMM1.203 & JDIMM1.204 DQ59 DQ63
195 VSS VSS 196
R335 1 2 10K_0402_5% 197 198 PM_EXTTS#0_1
SA0 EVENT# PM_EXTTS#0_1 5,11
199 200 D_CK_SDATA
+3VS VDDSPD SDA D_CK_SDATA 11,12
201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK 11,12
1 1 203 204 +0.75VS
VTT VTT
1

+0.75VS C344 C345

2.2U_0603_6.3V4Z R332 205 206
1U_0603_10V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z GND1 BOSS1
207 208
2 2 10K_0402_5% GND2 BOSS2
A
DDR3 SO-DIMM A A
2

FOX_AS0A626-U2SN-7F_204P

C624
2 2
C629
2
C625
2
C680
1
C291 CONN@
Standard Type
10U_0805_6.3V6M
1 1 1 1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title
1U_0603_10V4Z 1U_0603_10V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NALG0 M/B LA-5681P Schematic 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 23, 2009 Sheet 10 of 60
5 4 3 2 1
 5 4 3 2 1

H_DIMMB_REF R327 1 @ 2 0_0402_5% +1.5V +1.5V

4 H_DIMMB_REF
2008/9/8 #400755 JDIMM2
6 DDR_B_DQS#[0..7] Calpella Clarksfield +V_DDR3_DIMM_REF R328 1 2 0_0402_5% VREF_DQB 1 2
VREF_DQ VSS DDR_B_D4
DDR3 SO-DIMM 3 VSS DQ4 4
DDR_B_D0 5 6 DDR_B_D5
6 DDR_B_D[0..63] VREFDQ Platform DQ0 DQ5
DDR_B_D1 7 8
Design Guide Change Details DQ1 VSS DDR_B_DQS#0
9 VSS DQS0# 10
DDR_B_DM0 11 12 DDR_B_DQS0
6 DDR_B_DM[0..7] DM0 DQS0
13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6
6 DDR_B_DQS[0..7] DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
6 DDR_B_MA[0..15] 2009/04/13 19
VSS VSS
20
DDR_B_D8 21 22 DDR_B_D12
D PCH_SMBCLK For Arrandale ,it should be use M1 Circuit (pop R328) DDR_B_D9 23
DQ8 DQ12
24 DDR_B_D13 D
12,14,32 PCH_SMBCLK For Clarksfield ,it should be use M3 Circuit (pop R327) DQ9 DQ13
25 VSS VSS 26
PCH_SMBDATA DG V1.52 DDR_B_DQS#1 27 28 DDR_B_DM1
12,14,32 PCH_SMBDATA DQS1# DM1
1 1 DDR_B_DQS1 29 30 DIMM_RST#
C335 C336 DQS1 RESET#
31 32
DDR_B_D10 VSS VSS DDR_B_D14
33 DQ10 DQ14 34
DDR_B_D11 35 36 DDR_B_D15
2.2U_0805_16V4Z 2 2 DQ11 DQ15
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 42
0.1U_0402_16V4Z DQ17 DQ21
43 VSS VSS 44
@ Q63 DDR_B_DQS#2 45 46 DDR_B_DM2
BSS138_NL_SOT23-3 DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
VSS DQ22

D
H_DIMMB_REF 3 1 VREF_DQB DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
53 54
DQ19 VSS
1

55 56 DDR_B_D28
R737 DDR_B_D24 VSS DQ28 DDR_B_D29
57 58

G
2
@ DDR_B_D25 DQ24 DQ29
100K_0402_5% 59 DQ25 VSS 60
1 61 62 DDR_B_DQS#3
C714 0.047U_0402_16V7K DDR_B_DM3 VSS DQS3# DDR_B_DQS3
63 64
2

DM3 DQS3
65 66
@ DDR_B_D26 VSS VSS DDR_B_D30
10,18 RST_GATE 67 DQ26 DQ30 68
2 +1.5V DDR_B_D27 DDR_B_D31
69 DQ27 DQ31 70
71 72
VSS VSS

1
DDR_B_CKE0 73 74 DDR_B_CKE1
6 DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 6
R734 1 @ 2 0_0402_5% R732 75 76
VDD VDD DDR_B_MA15
77 NC A15 78
1K_0402_1% DDR_B_BS2 79 80 DDR_B_MA14
6 DDR_B_BS2 BA2 A14
81 82

2
C DDR_B_MA12 VDD VDD DDR_B_MA11 C
83 A12/BC# A11 84
BSS138_NL_SOT23-3 DDR_B_MA9 85 86 DDR_B_MA7
A9 A7
87 88
VDD VDD
S

3 1 DIMM_RST# DDR_B_MA8 89 90 DDR_B_MA6

5 SM_DRAMRST# DIMM_RST# 10 DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
1

Q62 93 94
R294 DDR_B_MA3 VDD VDD DDR_B_MA2
95 96
G

1
2

S3@ @ C711 DDR_B_MA1 A3 A2 DDR_B_MA0

100K_0402_5% 97 98
A1 A0
99 VDD VDD 100
1 S3@ 0.1U_0402_16V4Z DDR_B_CLK0 101 102 DDR_B_CLK1
DDR_B_CLK1 6
2

C712 2 6 DDR_B_CLK0 DDR_B_CLK0# CK0 CK1 DDR_B_CLK1#

103 CK0# CK1# 104 DDR_B_CLK1# 6
0.047U_0402_16V7K 6 DDR_B_CLK0#
105 106
DDR_B_MA10 VDD VDD DDR_B_BS1
107 A10/AP BA1 108 DDR_B_BS1 6
2 DDR_B_BS0 109 110 DDR_B_RAS#
10,18 RST_GATE 6 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 6
111 112
DDR_B_WE# VDD VDD DDR_B_CS0#
113 114 DDR_B_CS0# 6
6 DDR_B_WE# DDR_B_CAS# WE# S0# DDR_B_ODT0
6 DDR_B_CAS# 115 116 DDR_B_ODT0 6
CAS# ODT0
117 118
DDR_B_MA13 VDD VDD DDR_B_ODT1
Layout Note: DDR_B_CS1#
119
A13 ODT1
120 DDR_B_ODT1 6
121 S1# NC 122
Place near JDIMM2 6 DDR_B_CS1#
123 124
VDD VDD
125 126 +DDR_VREF_CA
TEST VREF_CA
Layout Note: Place these 4 Caps near Command 127
VSS VSS
128
DDR_B_D32 129 130 DDR_B_D36
and Control signals of DIMMA DDR_B_D33 131
DQ32 DQ36
132 DDR_B_D37
DQ33 DQ37
133 134
+1.5V DDR_B_DQS#4 VSS VSS DDR_B_DM4
135 DQS4# DM4 136
DDR_B_DQS4 137 138 1 1
10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DQS4 VSS DDR_B_D38 C334 C332
139 140
DDR_B_D34 VSS DQ38 DDR_B_D39
141 142
DDR_B_D35 DQ34 DQ39 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z
1 143 144
DQ35 VSS DDR_B_D44 2 2
1 1 1 1 1 1 1 1 1 1 145 146
VSS DQ44
C659

B C660 C657 C655 C656 C658 C331 C330 C329 C333 + C307 DDR_B_D40 147 148 DDR_B_D45 B
330U_X_2VM_R6M DDR_B_D41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDR_B_DQS#5
10U_0805_6.3V6M 2 2 2 2 2 2 2 2 2 2 2 DDR_B_DM5 VSS DQS5# DDR_B_DQS5
153 DM5 DQS5 154
155 156
DDR_B_D42 VSS VSS DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DQ43 DQ47
161 162
DDR_B_D48 VSS VSS DDR_B_D52
163 164
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS VSS 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS6# DM6
171 DQS6 VSS 172
Layout Note: 173 174 DDR_B_D54
DDR_B_D50 VSS DQ54 DDR_B_D55
175 176
Place near JDIMM2.203 & JDIMM2.204 DDR_B_D51 177
DQ50 DQ55
178
DQ51 VSS DDR_B_D60
179 180
DDR_B_D56 VSS DQ60 DDR_B_D61
181 182
DDR_B_D57 DQ56 DQ61
183 184
DQ57 VSS DDR_B_DQS#7
185 186
+0.75VS DDR_B_DM7 VSS DQS7# DDR_B_DQS7
187 188
DM7 DQS7
189 VSS VSS 190
1U_0603_10V4Z DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
195 196
R685 1 VSS VSS PM_EXTTS#0_1
2 10K_0402_5% 197 198 PM_EXTTS#0_1 5,10
C667 2 C666 2 C671 2 C665 2 SA0 EVENT# D_CK_SDATA
1 C690 +3VS 199 VDDSPD SDA 200 D_CK_SDATA 10,12
1 2 201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK 10,12
R686 10K_0402_5% 203 204 +0.75VS
1U_0603_10V4Z 10U_0805_6.3V6M VTT VTT
1 1 1 1 2 1 1
C661 C663 205 206
GND1 BOSS1
207 GND2 BOSS2 208
A 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z A

1U_0603_10V4Z 1U_0603_10V4Z
2 2 DDR3 SO-DIMM B
TYCO_2-2013310-1_204P
CONN@
Standard Type

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NALG0 M/B LA-5681P Schematic 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 23, 2009 Sheet 11 of 60
5 4 3 2 1
 A B C D E F G H

power save CLK gen use +1.5VS at +CLK_VDD +CLK_VDD

@
+1.5VS L12 2 1
FBMA-L11-201209-221LMA30T_0805
+CLK_VDDSRC
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.05VS L13 2 1 +3VS L14 2 1
FBMA-L11-201209-221LMA30T_0805 FBMA-L11-201209-221LMA30T_0805
1 1 1 1 1 1 1 1
C297 C628 C632 C298 C634 C630 C631
C286
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2
1 1

0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z

+CLK_SE
+3VS L17 2 1 0.1U_0402_16V4Z
FBMA-L11-201209-221LMA30T_0805
1 1 1
C308 C636 C633

0.1U_0402_16V4Z
2 2 2

+CLK_VDDSRC 10U_0805_10V4Z

+CLK_VDD
Clock Generator +CLK_VDDSRC

U27 +CLK_VDD
Integrated 33ohm Resistor
1 32 D_CK_SCLK
VDD_USB_48 SCL D_CK_SCLK 10,11
0_0404_4P2R_5% 2 31 D_CK_SDATA
VSS_48M SDA D_CK_SDATA 10,11
CLK_BUF_DREF_96M 1 4 CLK_BUF_DREF_96M_R 3 30 REF_0/CPU_SEL R305 1 2 33_0402_5%
14 CLK_BUF_DREF_96M DOT_96 REF_0/CPU_SEL CLK_BUF_ICH_14M 14
CLK_BUF_DREF_96M# 2 3 CLK_BUF_DREF_96M#_R 4 29 +CLK_SE
14 CLK_BUF_DREF_96M# DOT_96# VDD_REF
RP12 +CLK_SE 5 28 CLK_XTAL_IN
R316 1 DIS@ VDD_27 XTAL_IN
22 27M_CLK 2 0_0402_5% 27M_CLK_R 6 27MHZ XTAL_OUT 27 CLK_XTAL_OUT
R317 1 DIS@ 2 0_0402_5% 27M_SSC_R 7 26
22 27M_SSC 27MHZ_SS VSS_REF
CLK_SD_48M 1 2 CLK_SD_48M_R 8 25 CK505_PW RGD
36 CLK_SD_48M USB_48 CKPWRGD/PD#
R318 33_0402_5%
2 9 24 2
CLK_BUF_PCIE_SATA CLK_BUF_PCIE_SATA_R VSS_27M VDD_CPU CLK_BUF_CPU_BCLK_R CLK_BUF_CPU_BCLK
14 CLK_BUF_PCIE_SATA 1 4 10 SATA CPU_0 23 1 4 CLK_BUF_CPU_BCLK 14
CLK_BUF_PCIE_SATA# 2 3 CLK_BUF_PCIE_SATA#_R 11 22 CLK_BUF_CPU_BCLK#_R 2 3 CLK_BUF_CPU_BCLK#
14 CLK_BUF_PCIE_SATA# SATA# CPU_0# CLK_BUF_CPU_BCLK# 14
RP11 0_0404_4P2R_5% 12 21 0_0404_4P2R_5%
CLK_BUF_CPU_DMI CLK_BUF_CPU_DMI_R VSS_SRC VSS_CPU RP9
14 CLK_BUF_CPU_DMI 1 4 13 SRC_1 CPU_1 20
CLK_BUF_CPU_DMI# 2 3 CLK_BUF_CPU_DMI#_R 14 19
14 CLK_BUF_CPU_DMI# SRC_1# CPU_1#
RP10 0_0404_4P2R_5% 15 VDD_SRC_IO VDD_CPU_IO 18 Integrated 33ohm Resistor
H_STP_CPU# 16 17
CPU_STOP# VDD_SRC
Integrated 33ohm Resistor 33 TGND
IDT SA000030P00
SLG8SP587VTR_QFN32_5X5
<BOM Structure>
IDT: 9LRS3199AKLFT, SA000030P00 +3VS
SILEGO: SLG8SP587V(WF), SA00002XY10

2
R301
10K_0402_5%
R297
+3VS 0_0402_5%

1
Silego Have Internal Pull-Up CK505_PW RGD 1 @ 2 VGATE 15,55
1 D

1
0.1U_0402_16V4Z C715
R302 1 2 10K_0402_5% H_STP_CPU# +3VS 2 CLK_ENABLE# 55
R320 @ G
4.7K_0402_5% 2 S Q29

3
2
G
1 2 +3VS 2N7002_SOT23
3 3

14,32 PCH_SMBDATA 1 3 D_CK_SDATA

S
IDT Have Internal Pull-Down Q33 1 XDP@ 2 XDP_SDATA 5
2N7002_SOT23 R310 0_0402_5% C303
CLK_XTAL_IN 2 1
R315 1 2 10K_0402_5% REF_0/CPU_SEL +3VS

2
R321 27P_0402_50V8J
2 4.7K_0402_5% Y4
G 1 2 +3VS C301
14.318MHZ_16PF_7A14300083
27P_0402_50V8J

1
PIN 30 CPU_0 CPU_1 14,32 PCH_SMBCLK 1 3 D_CK_SCLK CLK_XTAL_OUT 2 1
D

Q34
0 (Default) 133MHz 133MHz 2N7002_SOT23 1 XDP@ 2 XDP_SCLK 5
R311 0_0402_5%

1 100MHz 100MHz

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator (CK505)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 12 of 60
A B C D E F G H
 5 4 3 2 1

+RTCVCC 1 2 PCH_RTCRST#
R565 C210 +3VS
20K_0402_1% RC Delay 18~25mS 18P_0402_50V8J
2 1 PCH_RTCX1

1
close to RAM door
X1 R729

1
1 2 3 NC OSC 4
J4 @ R176 100K_0402_5%
10K_0603_5% 2 1

2
C505 NC OSC 10M_0402_5% U18A ME_EN#
1U_0603_10V6K 32.768KHZ_12.5PF_Q13MC14610002
REV1.0

2
D

1
1 2 C211 B13 D33 LPC_AD0
RTCX1 FWH0 / LAD0 LPC_AD0 37
D 2 1 PCH_RTCX2 D13 B33 LPC_AD1 37 ME_EN 2 Q61 D
RTCX2 FWH1 / LAD1 LPC_AD1 37
C32 LPC_AD2 G 2N7002_SOT23
FWH2 / LAD2 LPC_AD2 37

1
18P_0402_50V8J A32 LPC_AD3 S
LPC_AD3 37

3
PCH_SRTCRST# PCH_RTCRST# FWH3 / LAD3 R730
+RTCVCC 1 2 C14 RTCRST#
R566 C34 LPC_FRAME#
+RTCVCC FWH4 / LFRAME# LPC_FRAME# 37
20K_0402_1% RC Delay 18~25mS PCH_SRTCRST# D17 SRTCRST#
100K_0402_5%
A34

RTC

LPC

2
LDRQ0#
close to RAM door R567 1 2 1M_0402_5% SM_INTRUDER# A16 INTRUDER# LDRQ1# / GPIO23 F34
1 2
J5 @ R564 1 2 332K_0402_1% PCH_INTVRMEN A14 AB9 SERIRQ
INTVRMEN SERIRQ SERIRQ 37
10K_0603_5% INTVRMEN - Integrated SUS 1.1V VRM Enable
C518
1U_0603_10V6K
High - Enable Internal VRs
1 2 HDA_BITCLK_PCH A30 HDA_BCLK SATA_DTX_C_PRX_N0
SATA0RXN AK7 SATA_DTX_C_PRX_N0 31
HDA_SYNC_PCH D29 AK6 SATA_DTX_C_PRX_P0 SATA_DTX_C_PRX_P0 31 SATA for HDD1
HDA_SYNC SATA0RXP SATA_PTX_DRX_N0
HDA for AUDIO PCH_SPKR SATA0TXN AK11
SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 31
37,40 PCH_SPKR P1 SPKR SATA0TXP AK9 SATA_PTX_DRX_P0 31
40 HDA_BITCLK_AUDIO 1 2 HDA_BITCLK_PCH
R185 33_0402_5% HDA_RST#_PCH C30
HDA_SYNC_PCH HDA_RST# SATA_DTX_C_PRX_N1
40 HDA_SYNC_AUDIO 1 2 SATA1RXN AH6 SATA_DTX_C_PRX_N1 31
R183 33_0402_5% AH5 SATA_DTX_C_PRX_P1 SATA_DTX_C_PRX_P1 31 SATA for ODD
HDA_RST#_PCH SATA1RXP SATA_PTX_DRX_N1
40 HDA_RST_AUDIO# 1 2 40 HDA_SDIN0 G30 HDA_SDIN0 SATA1TXN AH9 SATA_PTX_DRX_N1 31
R186 33_0402_5% AH8 SATA_PTX_DRX_P1
HDA_SDOUT_PCH SATA1TXP SATA_PTX_DRX_P1 31
40 HDA_SDOUT_AUDIO 1 2 39 HDA_SDIN1 F30 HDA_SDIN1
R180 33_0402_5% AF11
SATA2RXN 2/10 SATA2, SATA3 not support on HM55
E32 AF9

IHDA
HDA_SDIN2 SATA2RXP
HDA for MDC SATA2TXN AF7
F32 HDA_SDIN3 SATA2TXP AF6
C
39 HDA_BITCLK_MDC 1 2 HDA_BITCLK_PCH C
R593 33_0402_5% AH3
HDA_SYNC_PCH HDA_SDOUT_PCH SATA3RXN
39 HDA_SYNC_MDC 1 2 B29 HDA_SDO SATA3RXP AH1
R590 33_0402_5% AF3
HDA_RST#_PCH SATA3TXN
39 HDA_RST_MDC# 1 2 SATA3TXP AF1
R596 33_0402_5% ME_EN# H32

SATA
HDA_SDOUT_PCH HDA_DOCK_EN# / GPIO33 SATA_DTX_C_PRX_N4
39 HDA_SDOUT_MDC 1 2 SATA4RXN AD9 SATA_DTX_C_PRX_N4 35
R583 33_0402_5% GPIO33 can not pull down J30 HDA_DOCK_RST# / GPIO13 SATA4RXP AD8 SATA_DTX_C_PRX_P4 SATA_DTX_C_PRX_P4 35 SATA for eSATA
(manufacturing environments) AD6 SATA_PTX_DRX_N4
SATA4TXN SATA_PTX_DRX_P4 SATA_PTX_DRX_N4 35
SATA4TXP AD5 SATA_PTX_DRX_P4 35
PCH_JTAG_TCK M3 AD3
JTAG_TCK SATA5RXN
SATA5RXP AD1
PCH_JTAG_TMS K3 AB3
JTAG_TMS SATA5TXN
SATA5TXP AB1
PCH_JTAG_TDI K1 JTAG_TDI +1.05VS

JTAG
PCH_JTAG_TDO J2 AF16
JTAG_TDO SATAICOMPO
PCH_JTAG_RST# J4 AF15 SATA_COMP R576 1 2 37.4_0402_1%
TRST# SATAICOMPI

If GPIO33 pull down, ME will not working.

For factory update ME, pull down resistor pull PCH_SPI_CLK_1 R122 1 2 0_0402_5% PCH_SPI_CLK BA2 +3VS
SPI_CLK
under door.
PCH_SPI_CS0# R124 1 2 15_0402_5% PCH_SPI_CS0#_R AV3 R136 1 2 10K_0402_5%
SPI_CS0#
AY3 SPI_CS1# SATALED# T3 SATA_LED# 44
+3VS R130 +3VS
B 1K_0402_5% B

1 @ 2 PCH_SPKR PCH_SPI_MOSI_1 R123 1 2 15_0402_5% PCH_SPI_MOSI AY1 Y9 R517 1 @ 2 10K_0402_5%

Have internal PD SPI_MOSI SATA0GP / GPIO21

SPI
PCH_SPI_MISO_1 R125 1 2 33_0402_5% PCH_SPI_MISO AV1 V1 R135 1 @ 2 10K_0402_5%
SERIRQ SPI_MISO SATA1GP / GPIO19
1 2
R512

1
10K_0402_5% IBEXPEAK-M_FCBGA107
R111 R518

+3VALW +1.05VS 10K_0402_5% 10K_0402_5%

2
R115 1 @ 2 51_0402_5% 2008 Intel MOW36/MOW50
R114 1 2 200_0402_5% TDO:
PCH_JTAG_TMS R138 1 2 100_0402_5% Reserved on ES1 Sample
Mount R516, R517 on ES2 Sample
R141 1 @ 2 51_0402_5%
R118 1 2 200_0402_5%
PCH_JTAG_TDO R140 1 2 100_0402_5%

R116 1 @ 2 51_0402_5% MP mount R689, R690,

R117 1 2 200_0402_5% R691, R692 and remove +3VS
PCH_JTAG_TDI R139 1 2 100_0402_5% others U14
PCH_SPI_CS0# 1 8
R142 1 @ CS# VCC
2 51_0402_5% +3VS R97 1 2 3.3K_0402_5% SPI_W P1# 3 WP# SCLK 6 PCH_SPI_CLK_1
R119 1 2 20K_0402_5% R96 1 2 3.3K_0402_5% SPI_HOLD1# 7 5 PCH_SPI_MOSI_1
PCH_JTAG_RST# R143 1 HOLD# SI
2 10K_0402_5% 4 GND SO 2 PCH_SPI_MISO_1

A
MX25L1605DM2I-12G SOP 8P A

SA000021A00

+3VS SPI ROM (4M)

PCH_SPI_MOSI R134 1 @ 2 1K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.
enable iTPM: SPI_MOSI High Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/9) SATA,HDA,SPI, LPC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PCH_JTAG_TCK R137 2 4.7K_0402_5% Custom 1.0
1
CRB 1.0 Change to 4.7K
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 13 of 60
5 4 3 2 1
 5 4 3 2 1

U18B

REV1.0 1. Connect Directly

PCIE_DTX_C_PRX_N1 BG30 B9 EC_LID_OUT#
33 PCIE_DTX_C_PRX_N1
PCIE_DTX_C_PRX_P1 BJ30
PERN1 SMBALERT# / GPIO11 EC_LID_OUT# 37 EXPRESS CARD, MINI1, MINI2
33 PCIE_DTX_C_PRX_P1 PERP1
For PCIE LAN 33 PCIE_PTX_C_DRX_N1 C240 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N1 BF29 PETN1 SMBCLK H14 PCH_SMBCLK PCH_SMBCLK 12,32 2. Level Shift1, Pull-Up to +3VS
33 PCIE_PTX_C_DRX_P1 C241 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P1 BH29 PETP1
C8 PCH_SMBDATA CLOCK GEN, DIMM1, DIMM2
SMBDATA PCH_SMBDATA 12,32
32 PCIE_DTX_C_PRX_N2
PCIE_DTX_C_PRX_N2 AW30
PERN2 3. Level Shift2, Pull-Up to +3VS
PCIE_DTX_C_PRX_P2 BA30
32 PCIE_DTX_C_PRX_P2
C242 2 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BC30 PERP2 PCH_GPIO60 LAN
For Wireless LAN 32 PCIE_PTX_C_DRX_N2 1 PETN2 SML0ALERT# / GPIO60 J14
32 PCIE_PTX_C_DRX_P2 C243 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P2 BD30
PETP2 4. Level Shift3, Pull-Up to +3VS
D C6 D
AU30
SML0CLK CPU & PCH XDP

SMBus
PERN3
AT30 PERP3 SML0DATA G8
AU32 PETN3
AV32 PETP3
M14 PCH_GPIO74 +3VS_DELAY
PCIE_DTX_C_PRX_N4 SML1ALERT# / GPIO74
32 PCIE_DTX_C_PRX_N4 BA32 PERN4
For Mini2 PCIE_DTX_C_PRX_P4 BB32 E10 PCH_SML1CLK
32 PCIE_DTX_C_PRX_P4 PERP4 SML1CLK / GPIO58

1
32 PCIE_PTX_C_DRX_N4 C246 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N4 BD32 R98
C244 2 0.1U_0402_16V7K PCIE_PTX_DRX_P4 PETN4 PCH_SML1DAT +3VALW 10K_0402_5% +3VS_DELAY
32 PCIE_PTX_C_DRX_P4 1 BE32 PETP4 SML1DATA / GPIO75 G12
mini2@

PCI-E*

2
mini2@ BF33 DIS@
PERN5

1
BH33 T13 R109 R121

2
PERP5 CL_CLK1

Controller
BG32 10K_0402_5% Q16
PETN5 2N7002_SOT23 10K_0402_5%
BJ32 PETP5 CL_DATA1 T11

2
G
Link

1
BA34 T9

2
PERN6 CL_RST1#
AW34 PERP6 1 3
BC34 DIS@

S
PETN6
BD34 PETP6
H1 PEG_CLKREQ#_R 1 @ 2
PEG_A_CLKRQ# / GPIO47 PEG_CLKREQ# 22
AT34 R120 0_0402_5%
PERN7
2/10 PCIE7, PCIE8 not support on HM55 AU34 PERP7 1 @ 2 VGA_PW ROK 39,52
AU36 AD43 CLK_PEG_VGA# 22 R144 0_0402_5%
PETN7 CLKOUT_PEG_A_N
AV36 PETP7 CLKOUT_PEG_A_P AD45 CLK_PEG_VGA 22 +3VS
BG34 PERN8 CLKOUT_DMI_N AN4 CLK_CPU_DMI# 5

PEG
BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_CPU_DMI 5

2
G
BG36 PETN8
C BJ36 C
PETP8 PCH_SML1CLK EC_SMB_CK2
CLKOUT_DP_N / CLKOUT_BCLK1_N AT1 CLK_CPU_DP# 5 1 3 EC_SMB_CK2 22,37
AT3

S
CLKOUT_DP_P / CLKOUT_BCLK1_P CLK_CPU_DP 5
33 CLK_PCIE_LAN# R244 1 2 0_0402_5% CLK_PCIE_LAN#_R AK48 Q17
R245 1 CLKOUT_PCIE0N
For PCIE LAN 33 CLK_PCIE_LAN 2 0_0402_5% CLK_PCIE_LAN_R AK47 CLKOUT_PCIE0P
2N7002_SOT23

From CLK BUFFER

CLKIN_DMI_N AW24 CLK_BUF_CPU_DMI# 12
R528 1 2 0_0402_5% PCH_GPIO73 P9 BA24 +3VS
33 LAN_CLKREQ# PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK_BUF_CPU_DMI 12

2
R242 1 2 0_0402_5% CLK_PCIE_MINI1#_R

G
32 CLK_PCIE_MINI1# AM43 CLKOUT_PCIE1N CLKIN_BCLK_N AP3 CLK_BUF_CPU_BCLK# 12
For Wireless LAN 32 CLK_PCIE_MINI1 R243 1 2 0_0402_5% CLK_PCIE_MINI1_R AM45 AP1
CLKOUT_PCIE1P CLKIN_BCLK_P CLK_BUF_CPU_BCLK 12
PCH_SML1DAT 1 3 EC_SMB_DA2 EC_SMB_DA2 22,37
R129 1 2 0_0402_5% PCH_GPIO18 U4

S
32 MINI1_CLKREQ# PCIECLKRQ1# / GPIO18
F18 Q21
CLKIN_DOT_96N CLK_BUF_DREF_96M# 12
E18 2N7002_SOT23
CLKIN_DOT_96P CLK_BUF_DREF_96M 12
AM47 CLKOUT_PCIE2N
AM48 CLKOUT_PCIE2P
CLKIN_SATA_N / CKSSCD_N AH13 CLK_BUF_PCIE_SATA# 12
PCH_GPIO20 N4 AH12
PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK_BUF_PCIE_SATA 12
Layout guide 1.52 update
AH42 P41 DIS only@
CLKOUT_PCIE3N REFCLK14IN CLK_BUF_ICH_14M 12
AH41 R228 1 2
CLKOUT_PCIE3P 0_0402_5%
+3VS R554 1 2 10K_0402_5% PCH_GPIO25 A8 J42
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCI_FB 17
C255
27P_0402_50V8J
For Mini2 32 CLK_PCIE_MINI2# R230 1 2 0_0402_5% CLK_PCIE_MINI2#_R AM51 AH51 XTAL25_IN 1 2
R229 1 CLKOUT_PCIE4N XTAL25_IN
32 CLK_PCIE_MINI2 2 0_0402_5% CLK_PCIE_MINI2_R AM53 CLKOUT_PCIE4P XTAL25_OUT AH53 XTAL25_OUT UMA@

2
B B
MINI2_CLKREQ#_1 M9 AF38 XCLK_RCOMP R604 1 2 90.9_0402_1% +1.05VS R209 Y6
PCIECLKRQ4# / GPIO26 XCLK_RCOMP 1M_0402_5% 25MHZ_20PF_7A25000012
UMA@ UMA@

1
+3VS AJ50 T45 +3VS

2
CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
For CardReader R545
AJ52 CLKOUT_PCIE5P Project Port ID 1 2
UMA@
1

PCH_GPIO44 H6 P43 PROJECT_ID1 R617 1 2 10K_0402_5% C254

Clock Flex

10K_0402_5% PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65 R622 1 @ 2 10K_0402_5% 27P_0402_50V8J

AK53 T42 PROJECT_ID0 R616 1 @ 2 10K_0402_5%

MINI2_CLKREQ#_1 CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66 R609 1
32 MINI2_CLKREQ# 1 2 AK51 2 10K_0402_5%
2

R551 0_0402_5% CLKOUT_PEG_B_P

PCH_GPIO56 P13 N50
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67

+3VS IBEXPEAK-M_FCBGA107

MINI1_CLKREQ# R112 1 @ 2 10K_0402_5%

PCH_GPIO20 R107 1 2 10K_0402_5%
+3VALW Project ID

EC_LID_OUT# R170 1 2 10K_0402_5%

ID1 ID0 Project
PCH_SMBCLK R178 1 2 2.2K_0402_5%
PCH_SMBDATA R547 1 2 2.2K_0402_5% * 1 0 JV 40
PCH_GPIO60 R572 1 2 10K_0402_5%
A 1 1 JM 40 A

PCH_SML1CLK R546 1 2 2.2K_0402_5%

PCH_SML1DAT R148 1 2 2.2K_0402_5%

PCH_GPIO74 R573 1 2 10K_0402_5%

PCH_GPIO18 R727 1 2 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title
PCH_GPIO44 R534 1 2 10K_0402_5%
PCH_GPIO56 R574 1 2 10K_0402_5% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/9) PCIE, SMBUS, CLK
PCH_GPIO73 R538 1 2 10K_0402_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 14 of 60
5 4 3 2 1
 5 4 3 2 1

DMI_HTX_PRX_N[0..3]
4 DMI_HTX_PRX_N[0..3]
DMI_HTX_PRX_P[0..3]
4 DMI_HTX_PRX_P[0..3]
DMI_PTX_HRX_N[0..3]
4 DMI_PTX_HRX_N[0..3]
DMI_PTX_HRX_P[0..3]
4 DMI_PTX_HRX_P[0..3]

H_FDI_TXN[0..7]
4 H_FDI_TXN[0..7]
D U18C D
H_FDI_TXP[0..7] H_FDI_TXN0
4 H_FDI_TXP[0..7]
DMI_HTX_PRX_N0 BC24
REV1.0 FDI_RXN0 BA18
BH17 H_FDI_TXN1
DMI_HTX_PRX_N1 BJ22 DMI0RXN FDI_RXN1 H_FDI_TXN2
DMI1RXN FDI_RXN2 BD16
DMI_HTX_PRX_N2 AW20 BJ16 H_FDI_TXN3
DMI_HTX_PRX_N3 BJ20 DMI2RXN FDI_RXN3 H_FDI_TXN4
DMI3RXN FDI_RXN4 BA16
+3VS BE14 H_FDI_TXN5
DMI_HTX_PRX_P0 FDI_RXN5 H_FDI_TXN6
BD24 DMI0RXP FDI_RXN6 BA14
DMI_HTX_PRX_P1 BG22 BC12 H_FDI_TXN7
DMI_HTX_PRX_P2 DMI1RXP FDI_RXN7
BA20 DMI2RXP
1 2 PM_CLKRUN# DMI_HTX_PRX_P3 BG20 BB18 H_FDI_TXP0
R127 8.2K_0402_5% DMI3RXP FDI_RXP0 H_FDI_TXP1
FDI_RXP1 BF17
1 @ 2 XDP_DBRESET# DMI_PTX_HRX_N0 BE22 DMI0TXN FDI_RXP2 BC16 H_FDI_TXP2
R509 10K_0402_5% DMI_PTX_HRX_N1 BF21 BG16 H_FDI_TXP3
DMI_PTX_HRX_N2 DMI1TXN FDI_RXP3 H_FDI_TXP4
BD20 DMI2TXN FDI_RXP4 AW16
DMI_PTX_HRX_N3 BE18 BD14 H_FDI_TXP5
DMI3TXN FDI_RXP5 H_FDI_TXP6
FDI_RXP6 BB14
DMI_PTX_HRX_P0 BD22 BD12 H_FDI_TXP7
DMI_PTX_HRX_P1 DMI0TXP FDI_RXP7
BH21 DMI1TXP
+3VALW DMI_PTX_HRX_P2 BC20
DMI_PTX_HRX_P3 DMI2TXP
BD18 DMI3TXP FDI_INT BJ14 H_FDI_INT 4
+1.05VS

DMI
FDI
1 2 SUS_PW R_ACK BF13 H_FDI_FSYNC0 4
R108 10K_0402_5% R184 FDI_FSYNC0
BH25 DMI_ZCOMP
1 2 PCH_GPIO72 49.9_0402_1% BH13 H_FDI_FSYNC1 4
R165 8.2K_0402_5% DMI_COMP FDI_FSYNC1
1 2 BF25 DMI_IRCOMP
1 2 EC_SW I# BJ12 H_FDI_LSYNC0 4
R580 10K_0402_5% FDI_LSYNC0
1 2 PCH_PCIE_W AKE# BG14 H_FDI_LSYNC1 4
C R552 1K_0402_5% FDI_LSYNC1 C
1 @ 2 PM_SLP_LAN#
R540 10K_0402_5%

XDP_DBRESET# T6 J12 PCH_PCIE_W AKE#

5 XDP_DBRESET# SYS_RESET# WAKE# PCH_PCIE_W AKE# 32,33

SYS_PW ROK R100 2 1 0_0402_5% SYS_PW ROK_R M6 Y1 PM_CLKRUN#

SYS_PWROK CLKRUN# / GPIO32 PM_CLKRUN# 37
VGATE R95 2 @ 1 0_0402_5%

System Power Management

SYS_PW ROK B17 PWROK

2 1 ME_PW ROK K5 MEPWROK SUS_STAT# / GPIO61 P8 PCH_GPIO61 @ PAD T17

R101 0_0402_5%

LAN_RST# A10 F3 PCH_GPIO62 @ PAD

LAN_RST# SUSCLK / GPIO62 T15

5 PM_DRAM_PW RGD D9 DRAMPWROK SLP_S5# / GPIO63 E4 PM_SLP_S5# 37

PCH_RSMRST# C16 H7 PM_SLP_S4# 37

RSMRST# SLP_S4#

SUS_PW R_ACK M1 P12 PM_SLP_S3# 37

B 37 SUS_PW R_ACK SUS_PWR_DN_ACK / GPIO30 SLP_S3# B
10/2 Intel suggestion change to 10K
PBTN_OUT# P5 K8 PM_SLP_M# @ PAD @
5,37 PBTN_OUT# PWRBTN# SLP_M# T16
+3VALW 1 2 R198 2 1 0_0402_5%
R530 100K_0402_5% Q25
1 2 PCH_ACIN P7 N2 PM_SLP_DSW # @ PAD MMBT3906_SOT23-3
37,43,44,45 ACIN ACPRESENT / GPIO31 TP23 T4
D10 PCH_RSMRST# 1 3

C
EC_RSMRST# 37
CH751H-40PT_SOD323-2

E
PCH_GPIO72 A6 BJ10
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5

B
2
R197 1 2 +3VALW
EC_SW I# F14 F6 PM_SLP_LAN# 10K_0402_5% R207 4.7K_0402_5%
37 EC_SW I# RI# SLP_LAN# / GPIO29
D14A

2
IBEXPEAK-M_FCBGA107 1
@ 6
2
+3VS BAV99DW -7_SOT363

D14B
5

U13 4
2 EC_PW ROK 3
P

B EC_PW ROK 37
SYS_PW ROK 4 5
Y

1
1 VGATE
A VGATE 12,55
G

BAV99DW -7_SOT363 R206

NC7SZ08P5X_NL_SC70-5 2.2K_0402_5%
3

2
A A

SYS_PW ROK 1 2
R103 10K_0402_5%

EC_PW ROK
R94
1 2
10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title
LAN_RST# 1
R174
2
10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/9) DMI, FDI, PM
No used Integrated LAN, Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
connecting LAN_RST# to GND DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 15 of 60
5 4 3 2 1
 5 4 3 2 1

U18D

IGPU_BKLT_EN T48 BJ46

L_BKLTEN SDVO_TVCLKINN
28 PCH_ENVDD T47 L_VDD_EN SDVO_TVCLKINP BG46

D 28 DPST_PW M Y48 L_BKLTCTL SDVO_STALLN BJ48 D

SDVO_STALLP BG48
28 PCH_LCD_CLK AB48 L_DDC_CLK
28 PCH_LCD_DATA Y45 L_DDC_DATA SDVO_INTN BF45
SDVO_INTP BH45
LCTLA_CLK AB46
LCTLB_DATA L_CTRL_CLK
V48 L_CTRL_DATA
R608 1 UMA@ 2 LVDS_IBG AP39 T51
LVD_IBG SDVO_CTRLCLK SDVO_SCLK 30
2.37K_0402_1% AP41 T53
LVD_VBG SDVO_CTRLDATA SDVO_SDATA 30
R618 1 UMA@ 2 LVD_VREF AT43
0_0402_5% LVD_VREFH R606 1
AT42 LVD_VREFL DDPB_AUXN BG44 2 100K_0402_5%
DDPB_AUXP BJ44
AU38 PCH_DPB_HPD
DDPB_HPD PCH_DPB_HPD 30

LVDS
PCH_TXCLK- AV53
28 PCH_TXCLK- LVDSA_CLK#
PCH_TXCLK+ AV51 BD42 PCH_DPB_N0 C613 2 1 UMA only@
0.1U_0402_16V7K PCH_TMDS_D2# 30
+3VS 28 PCH_TXCLK+ LVDSA_CLK DDPB_0N
BC42 PCH_DPB_P0 C611 2 1 UMA only@
0.1U_0402_16V7K PCH_TMDS_D2 30 HDMI D2
PCH_TXOUT0- DDPB_0P PCH_DPB_N1 C615 UMA only@
0.1U_0402_16V7K
28 PCH_TXOUT0- BB47 LVDSA_DATA#0 DDPB_1N BJ42 2 1 PCH_TMDS_D1# 30
11/21 intel JIM suggest Pull high at LVDS Conn PCH_TXOUT1- BA52 BG42 PCH_DPB_P1 C614 2 1 UMA only@
0.1U_0402_16V7K PCH_TMDS_D1 30 HDMI D1

Digital Display Interface

28 PCH_TXOUT1- LVDSA_DATA#1 DDPB_1P
for LVDS DDC PCH_TXOUT2- AY48 BB40 PCH_DPB_N2 C620 2 1 UMA only@
0.1U_0402_16V7K PCH_TMDS_D0# 30
28 PCH_TXOUT2- LVDSA_DATA#2 DDPB_2N
AV47 BA40 PCH_DPB_P2 C618 2 1 UMA only@
0.1U_0402_16V7K PCH_TMDS_D0 30 HDMI D0
LVDSA_DATA#3 DDPB_2P PCH_DPB_N3 C617 UMA only@
0.1U_0402_16V7K
DDPB_3N AW38 2 1 PCH_TMDS_CK# 30
PCH_TXOUT0+ BB48 BA38 PCH_DPB_P3 C616 2 1 UMA only@
0.1U_0402_16V7K PCH_TMDS_CK 30 HDMI CLK
28 PCH_TXOUT0+ LVDSA_DATA0 DDPB_3P
PCH_TXOUT1+ BA50
28 PCH_TXOUT1+ LVDSA_DATA1
R639 1 2 10K_0402_5% LCTLA_CLK PCH_TXOUT2+ AY49
28 PCH_TXOUT2+ LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
R641 1 2 10K_0402_5% LCTLB_DATA AB49
DDPC_CTRLDATA
C R219 1 2 2.2K_0402_5% PCH_CRT_CLK AP48 C
LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
R220 1 2 2.2K_0402_5% PCH_CRT_DATA BD44
DDPC_AUXP
AY53 LVDSB_DATA#0 DDPC_HPD AV40
AT49 LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40
AT53 LVDSB_DATA#3 DDPC_0P BD40
DDPC_1N BF41
AY51 LVDSB_DATA0 DDPC_1P BH41
AT48 LVDSB_DATA1 DDPC_2N BD38
AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36

1 2 PCH_CRT_B PCH_CRT_B AA52 U50

29 PCH_CRT_B CRT_BLUE DDPD_CTRLCLK
R227 150_0402_1% PCH_CRT_G AB53 U52
29 PCH_CRT_G CRT_GREEN DDPD_CTRLDATA
1 2 PCH_CRT_G PCH_CRT_R AD53
29 PCH_CRT_R CRT_RED
R226 150_0402_1%
1 2 PCH_CRT_R BC46
R225 150_0402_1% PCH_CRT_CLK DDPD_AUXN
29 PCH_CRT_CLK V51 CRT_DDC_CLK DDPD_AUXP BD46
PCH_CRT_DATA V53 AT38
29 PCH_CRT_DATA CRT_DDC_DATA DDPD_HPD

DDPD_0N BJ40
29 PCH_CRT_HSYNC Y53 CRT_HSYNC DDPD_0P BG40
29 PCH_CRT_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38

CRT
DDPD_2N BF37
CRT_IREF AD48 BH37
B DAC_IREF DDPD_2P B
AB51 CRT_IRTN DDPD_3N BE36
REV1.0 DDPD_3P BD36

IBEXPEAK-M_FCBGA107
@
1

2/3 Change to 1K_0402_0.5% from Intel

R623 Suggestion. (EDS 1.0 is incorrect)
1K_0402_0.5%
2

+5VS C178 SG@

0.1U_0402_16V4Z
U11 1 2

22 VGA_BKL_EN 2 1A VCC 8
IGPU_BKLT_EN 5 3 ENBKL
2A 1B ENBKL 37
28 PW MSEL_1# 1 1OE# 2B 6
28 IGPU_PW M_SELECT# 7 2OE# GND 4
1

SN74CBTD3306CPW R_TSSOP8 R83

SG@ 100K_0402_5%
2

A A

IGPU_BKLT_EN R76 1 UMA only@

2 0_0402_5% ENBKL

Reserved for UMA Only

Security Classification Compal Secret Data Compal Electronics, Inc.
VGA_BKL_EN R77 1 DIS only@2 0_0402_5% ENBKL 2009/5/12 2010/04/15 Title
Issued Date Deciphered Date
Reserved for DIS Only THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS, CRT, DPI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 16 of 60
5 4 3 2 1
 5 4 3 2 1

U18E
+3VS H40
N34
AD0 REV1.0 NV_CE#0 AY9
BD1
AD1 NV_CE#1
C44 AD2 NV_CE#2 AP15
R621 1 2 8.2K_0402_5% PCI_PIRQA# A38 BD8
R187 8.2K_0402_5% PCI_PIRQG# AD3 NV_CE#3
1 2 C36 AD4
R188 1 2 8.2K_0402_5% PCI_PIRQC# J34 AV9
R205 8.2K_0402_5% PCI_SERR# AD5 NV_DQS0
1 2 A40 AD6 NV_DQS1 BG8
D45 AD7
E36 AD8 NV_DQ0 / NV_IO0 AP7
H48 AP6 +3VS
AD9 NV_DQ1 / NV_IO1
E40 AD10 NV_DQ2 / NV_IO2 AT6
D C40 AD11 NV_DQ3 / NV_IO3 AT9 D

5
R218 1 2 8.2K_0402_5% PCI_PLOCK# M48 BB1 U17
R624 8.2K_0402_5% PCI_PERR# AD12 NV_DQ4 / NV_IO4 PLT_RST#
1 2 M45 AV6 2 B

P
R192 8.2K_0402_5% PCI_PIRQE# AD13 NV_DQ5 / NV_IO5
1 2 F53 AD14 NV_DQ6 / NV_IO6 BB3 Y 4 PLT_RST_BUF# 32
R193 1 2 8.2K_0402_5% PCI_STOP# M40 BA4 1
AD15 NV_DQ7 / NV_IO7 A

G
NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4

1
J36 BB6 NC7SZ08P5X_NL_SC70-5

3
AD17 NV_DQ9 / NV_IO9 R149
K48 AD18 NV_DQ10 / NV_IO10 BD6
F40 BB7 100K_0402_5%
AD19 NV_DQ11 / NV_IO11
C42 AD20 NV_DQ12 / NV_IO12 BC8
R224 1 2 8.2K_0402_5% PCI_REQ0# K46 BJ8

2
R223 8.2K_0402_5% PCI_PIRQB# AD21 NV_DQ13 / NV_IO13 +VCCQ_NAND
1 2 M51 AD22 NV_DQ14 / NV_IO14 BJ6
R222 1 2 8.2K_0402_5% PCI_PIRQF# J52 BG6
R235 8.2K_0402_5% PCI_REQ3# AD23 NV_DQ15 / NV_IO15 +3VS
1 2 K51 AD24
L34 BD3 NV_ALE R153 1 @ 2 1K_0402_5%
AD25 NV_ALE NV_CLE R555 1 @
F42 AD26 NV_CLE AY6 2 1K_0402_5%

5
J40 U19
AD27
G46 2 B

P
R194 8.2K_0402_5% PCI_IRDY# AD28 NV_RCOMP R133 1
1 2 F44 AD29 NV_RCOMP AU2 2 32.4_0402_1% Y 4 R162 1 DIS@ 2 PLTRST_VGA# 22
R195 1 2 8.2K_0402_5% PCI_PIRQD# M47 1 100_0402_5%
AD30 18 DGPU_HOLD_RST# A

G
PCI
R196 1 2 8.2K_0402_5% DGPU_SELECT# H36 AV7
AD31 NV_RB#

1
R625 1 2 8.2K_0402_5% PCI_DEVSEL# NC7SZ08P5X_NL_SC70-5

3
J50 AY8 DIS@ R161
C/BE0# NV_WR#0_RE# 100K_0402_5%
G42 C/BE1# NV_WR#1_RE# AY5
H47 C/BE2# DIS@
G34 AV11

2
R200 8.2K_0402_5% PCI_FRAME# C/BE3# NV_WE#_CK0
1 2 NV_WE#_CK1 BF5
R199 1 2 8.2K_0402_5% PCI_REQ1# PCI_PIRQA# G38
R202 8.2K_0402_5% PCI_PIRQH# PCI_PIRQB# PIRQA#
1 2 H51 PIRQB#
C R201 1 2 8.2K_0402_5% PCI_TRDY# PCI_PIRQC# B37 H18 C
PIRQC# USBP0N USB20_N0 35
PCI_PIRQD# A44 J18 eSATA USB Conn.(LEFT REAR)
PIRQD# USBP0P USB20_P0 35
USBP1N A18 USB20_N1 35
PCI_REQ0# F51 C18 USB/B(RIGHT)
REQ0# USBP1P USB20_P1 35
PCI_REQ1# A46 N20
DGPU_SELECT# REQ1# / GPIO50 USBP2N
28,29 DGPU_SELECT# B45 REQ2# / GPIO52 USBP2P P20
PCI_REQ3# M53 J20
REQ3# / GPIO54 USBP3N USB20_N3 28
USBP3P L20 USB20_P3 28 CMOS Camera (LVDS) EHCI 1
PCI_GNT0# F48 F20
GNT0# USBP4N USB20_N4 32
PCI_GNT1# K45 GNT1# / GPIO51 USBP4P G20 USB20_P4 32 Mini Card(WLAN) Danbury Technology Enabled
28 DGPU_PW MSEL# F36 GNT2# / GPIO53 USBP5N A20 USB20_N5 32
PCI_GNT3# H53 C20 Mini Card(Mini2)
GNT3# / GPIO55 USBP5P USB20_P5 32
USBP6N M22 High = Enabled
PCI_PIRQE# B41 PIRQE# / GPIO2 USBP6P N22 NV_ALE
PCI_PIRQF# K53 PIRQF# / GPIO3 USBP7N B21 Low = Disabled
PCI_PIRQG# A36 D21
PCI_PIRQH# PIRQG# / GPIO4 USBP7P
A48 PIRQH# / GPIO5 USBP8N H22 USB20_N8 35
USBP8P J22 USB20_P8 35 USB Conn. (HS)(LEFT FRONT)

USB
K6 PCIRST# USBP9N E22 USB20_N9 36
USBP9P F22 USB20_P9 36 Card Reader DMI Termination Voltage
PCI_SERR# E44 A22
SERR# USBP10N USB20_N10 35
PCI_PERR# E50 C22 Bluetooth
PERR# USBP10P USB20_P10 35
USBP11N G24 USB20_N11 35 Set to Vss when LOW
USBP11P H24 USB20_P11 35 Fingerprint EHCI 2 NV_CLE
PCI_IRDY# A42 IRDY# USBP12N L24 Set to Vcc when HIGH
H44 PAR USBP12P M24
PCI_DEVSEL# F46 A24
PCI_FRAME# DEVSEL# USBP13N
C46 FRAME# USBP13P C24
B PCI_PLOCK# B
D49 PLOCK#
B25 USB_BIAS 1 2
PCI_STOP# USBRBIAS# R584
D41 STOP#
PCI_TRDY# C48 D25 22.6_0402_1%
TRDY# USBRBIAS
M7 PME#
N16 USB_OC#0
USB_OC#0 35
(For USB Port0) USB_OC#0 1 2
PLT_RST# OC0# / GPIO59 USB_OC#1 R281 10K_0402_5%
5,33,37 PLT_RST# D5 PLTRST# OC1# / GPIO40 J16
F16 USB_OC#2
USB_OC#2 35
(For eSATA USB Port) USB_OC#1 1 2
OC2# / GPIO41 USB_OC#3_R R750 10K_0402_5%
N52 CLKOUT_PCI0 OC3# / GPIO42 L16
P53 CLKOUT_PCI1 OC4# / GPIO43 E14 USB_OC#4
USB_OC#4 35
(For USB Port8)
P46 G16 USB_OC#5_R
R221 CLKOUT_PCI2 OC5# / GPIO9
37 CLK_PCI_LPC 1 2 22_0402_5% CLK_PCI_LPC_R P51 CLKOUT_PCI3 OC6# / GPIO10 F12 USB_OC#6_R RP17
R627 1 2 22_0402_5% CLK_PCI_FB_R P48 T15 USB_OC#7_R USB_OC#3_R 1 8 +3VALW
14 CLK_PCI_FB CLKOUT_PCI4 OC7# / GPIO14 USB_OC#5_R 2 7
USB_OC#7_R 3 6
2008/1/6 2009MOW01 change to 22 ohm IBEXPEAK-M_FCBGA107 USB_OC#6_R 4 5
@ OC[0..3] use for EHCI 1
OC[4..7] use for EHCI 2 10K_1206_8P4R_5%
<BOM Structure>

Boot BIOS Strap

PCI_GNT0# R638 1 @ 2 1K_0402_5%
PCI_GNT#0 PCI_GNT#1 Boot BIOS Location Have internal PU
PCI_GNT1# R620 1 @ 2 1K_0402_5%
0 0 LPC Have internal PU
0 1 Reserved (NAND)
A
PCI_GNT3# R238 1 @ 2 1K_0402_5% A
1 0 PCI Have internal PU

* 1 1 SPI

A16 swap override Strap/Top-Block Security Classification Compal Secret Data Compal Electronics, Inc.
Swap Override jumper Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

PCI_GNT#3 Low = A16 swap THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB, VRAM
High = Default AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 17 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS
U18F

CRT_DET Y3 AH45
R191 10K_0402_5% DGPU_EDIDSEL# BMBUSY# / GPIO0 CLKOUT_PCIE6N
1 2 CLKOUT_PCIE6P AH46
R190 1 2 10K_0402_5% PCH_GPIO6 28 DGPU_EDIDSEL# DGPU_EDIDSEL# C38
R126 10K_0402_5% DGPU_HOLD_RST# TACH1 / GPIO1
1 2
R510 1 2 10K_0402_5% GPIO22 PCH_GPIO6 D37 TACH2 / GPIO6
D
CLKOUT_PCIE7N AF48 D

MISC
R128 1 2 10K_0402_5% GPIO38 EC_SCI# J32 AF47 +3VS
37 EC_SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
R113 1 2 10K_0402_5% GPIO39
R532 1 @ 2 10K_0402_5% DGPU_PW R_EN EC_SMI# F10
37 EC_SMI# GPIO8 EC_GA20 R105 1 2 10K_0402_5%
R531 1
(GPIO8 Should not be Pull-Low)
2 10K_0402_5% PCH_GPIO48 CP_PE# K9 LAN_PHY_PWR_CTRL / GPIO12 A20GATE U2 EC_GA20
EC_GA20 37
R110 1 2 10K_0402_5% PCH_TEMP_ALERT# EC_KBRST# R106 1 2 10K_0402_5%
30 HDMI_HPD# 1 SG@ 2PCH_GPIO15 T7 GPIO15
R529 1 2 10K_0402_5% PCH_GPIO34 R519 0_0402_5%
R602 1 2 10K_0402_5% EC_SCI# 17 DGPU_HOLD_RST# DGPU_HOLD_RST# AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# 5
+3VALW R619 1 2 DGPU_PW ROK_BUF_R F38 AM1
39 DGPU_PW ROK_BUF TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLK 5
0_0402_5%
GPIO22 Y7 BG10
SCLOCK / GPIO22 PECI H_PECI 5

GPIO
R550 1 2 10K_0402_5% PCH_GPIO57
H10 T1 EC_KBRST#
GPIO24 RCIN# EC_KBRST# 37
R553 1 2 10K_0402_5% EC_SMI#
PCH_GPIO27 AB12 BE10
GPIO27 PROCPWRGD H_CPUPW RGD 5

CPU
R508 1 2 1K_0402_5% PCH_GPIO15
10/7 Not Use PCH_GPIO15 PU 1K to +3V PCH_GPIO28 V13 GPIO28 THRMTRIP# BD10 THRMTRIP_PCH# 2 1 H_THERMTRIP#
H_THERMTRIP# 5
R558 56_0402_5%
R507 1 2 10K_0402_5% PCH_GPIO28 PCH_GPIO34 M11 2 1 +1.1VS_VTT
R560 1 (Rev:1.0 GPIO24 Only) STP_PCI# / GPIO34
2 10K_0402_5% CP_PE# R559 56_0402_5%
R131 1 2 10K_0402_5% PCH_GPIO45 PCH_GPIO35 V6 SATACLKREQ# / GPIO35
WW46 Platform/Design Updates
39 DGPU_PW R_EN DGPU_PW R_EN AB7 BA22
SATA2GP / GPIO36 TP1 2008/11/17 54.9 1% ->56 5%
+3VS R562 1 2 10K_0402_5% PCH_GPIO37 AB13 AW22
UMA only@ SATA3GP / GPIO37 TP2
C GPIO38 V3 BB22 C
R731 1 SLOAD / GPIO38 TP3
2 10K_0402_5%
DIS@ GPIO39 P3 AY45
SDATAOUT0 / GPIO39 TP4
PCH_GPIO45 H3 AY46
PCIECLKRQ6# / GPIO45 TP5 MAINPW ON 46,47,49
PCH_GPIO46 F1 AV43
PCIECLKRQ7# / GPIO46 TP6 R556

1
R615 1 @ 2 10K_0402_5% DGPU_PW ROK_BUF_R PCH_GPIO48 AB6 AV45 @ 330_0402_5% C
SDATAOUT1 / GPIO48 TP7 Q43
+1.1VS_VTT 1 2 2
R539 1 2 10K_0402_5% PCH_GPIO35 PCH_TEMP_ALERT# AA4 AF13 B
37 PCH_TEMP_ALERT# SATA5GP / GPIO49 TP8 E 2SC2411K_SOT23

3
PCH_GPIO57 F8 M18 @
R511 1 @ GPIO57 TP9
2 10K_0402_5% PCH_GPIO27
GPIO27 (Have internal Pull-High) N18 H_THERMTRIP#
TP10
High: VCCVRM VR Enable A4 AJ24
VSS_NCTF_1 TP11
Low: VCCVRM VR Disable A49

NCTF
VSS_NCTF_2

RSVD
A5 VSS_NCTF_3 TP12 AK41
A50 VSS_NCTF_4
A52 VSS_NCTF_5 TP13 AK42
A53 VSS_NCTF_6
+3VS
B2 VSS_NCTF_7 TP14 M32
B4 VSS_NCTF_8
B52 VSS_NCTF_9 TP15 N32
2

B53 VSS_NCTF_10
R104 BE1 M30
VSS_NCTF_11 TP16
10K_0402_5% BE53 VSS_NCTF_12
B High: CRT Plugged BF1 VSS_NCTF_13 TP17 N30
B
BF53
1

CRT_DET VSS_NCTF_14
BH1 VSS_NCTF_15 TP18 H12
D BH2 VSS_NCTF_16
1

BH52 VSS_NCTF_17 TP19 AA23

29 CRT_DET# 2 BH53 VSS_NCTF_18
Q15G BJ1 AB45
2N7002_SOT23 VSS_NCTF_19 NC_1
S BJ2
3

VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
BJ49 VSS_NCTF_22
BJ5 VSS_NCTF_23 NC_3 AB42
BJ50 VSS_NCTF_24
BJ52 VSS_NCTF_25 NC_4 AB41
BJ53 VSS_NCTF_26
D1 VSS_NCTF_27 NC_5 T39
D2 VSS_NCTF_28
D53 VSS_NCTF_29
(Have internal PD,
E1 VSS_NCTF_30 INIT3_3V# P6 Do not pull high)
E53 VSS_NCTF_31 TP24_SST @
REV1.0 TP24 C10 PAD T6
IBEXPEAK-M_FCBGA107
@
+3VALW
1

10K_0402_5%
A A
R132
2

S3@
10,11 RST_GATE 1 2 PCH_GPIO46
R733 0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 18 of 60
5 4 3 2 1
 5 4 3 2 1

+1.05VS +3VS
60mA
10U_0805_10V4Z 1U_0402_6.3V4Z
U18G POWER +VCCADAC 0.01U_0402_16V7K 22U_0805_6.3V6M 22U_0805_6.3V6M
L9
AB24 VCCCORE[1] VCCADAC[1] AE50 1 2
1 1 AB26 1 1 1 1 BLM18AG601SN1D_2P
VCCCORE[2]

1
D Intel suggest follow CRB 8/21 AB28 VCCCORE[3] 69mA VCCADAC[2] AE52 C597 C598 D
C550 C544 R635 C256 C257 600 ohm bead,350mA
AD26 VCCCORE[4]1524mA

CRT
AD28 AF53 0_0402_5% 0.1U_0402_16V4Z
2 2 VCCCORE[5] VSSA_DAC[1] @ 2 2 2 2
AF26 VCCCORE[6]
Near AE50

VCC CORE
AF28 AF51

2
VCCCORE[7] VSSA_DAC[2] +3VS CRB 0.9 is 180 ohm @ 100MHz
Near AB24 Near AB24 AF30 VCCCORE[8]
Top Side AF31 VCCCORE[9] DG0.8 is 600 ohm FB (Page 290)
AH26 VCCCORE[10]
AH28 +VCCA_LVDS 1 UMA@ 2
VCCCORE[11] R634 0_0805_5%
AH30 VCCCORE[12] 300mA

1
AH31 VCCCORE[13] VCCALVDS AH38
All Ibex Peak-M Power rails with netnames +1.1VS and AJ30 R605
VCCCORE[14] 0_0402_5%
AJ31 AH39
+1.1V rails are actually +1.05VS and +1.05V rails VCCCORE[15] VSSA_LVDS DIS only@
59mA

2
+1.05VS AP43 +1.8VS
VCCTX_LVDS[1]
VCCTX_LVDS[2] AP45
+1.05VS AT46 Near AP43 L41 UMA@

LVDS
VCCTX_LVDS[3] +VCCTX_LVDS C596
AK24 VCCIO[24] VCCTX_LVDS[4] AT45 2 1
C590 1 1 UMA@ 1 0.1UH_MLF1608DR10KT_10%_1608
42mA 0.01U_0402_16V7K 22U_0805_6.3V6M 0.1uH inductor, 200mA
L8 1 @ 2 +VCCAPLL_EXP BJ24 C591
1UH_CBC2012T1R0M_20% VCCAPLLEXP UMA@ 0.01U_0402_16V7K
1 VCC3_3[2] AB34 1 DIS only@2
1uH inductor, 405mA C225 2 UMA@ 2 2 R628
@ AN20 AB35 0_0402_5%
10U_0805_10V4Z VCCIO[25] VCC3_3[3]
AN22

HVCMOS
DG 0.8 is 1uH Inductor (Page 291) 2 VCCIO[26]
AN23 VCCIO[27] VCC3_3[4] AD35 +3VS
Have Internal VRM (DG0.8 Page 293) AN24 VCCIO[28]
AN26 VCCIO[29] 1
C AN28 C554 C
VCCIO[30]
BJ26 VCCIO[31]
BJ28 VCCIO[32]
0.1U_0402_16V4Z
2
Near AB34
AT26 VCCIO[33]
AT28 R587 1 @ 2 0_0805_5% +1.05VS
VCCIO[34]
AU26 VCCIO[35]
+1.05VS AU28 +VCCVRM R588 1 @ 2 0_0805_5%
VCCIO[36] +1.5VS
AV26 VCCIO[37] 35mA
Near AN20 AV28 VCCIO[38] VCCVRM[2] AT24 1 2 +1.8VS
10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z AW26 3208mA R582 0_0805_5%
VCCIO[39]
1 1 1 1 1 AW28 VCCIO[40] 61mA +1.1VS_VTT

DMI
BA26 VCCIO[41] VCCDMI[1] AT16
C549 C535 C547 C542 C537 BA28 VCCIO[42] +VCC_DMI
BB26 VCCIO[43] VCCDMI[2] AU16 1 2
2 2 2 2 2 R575 0_0805_5%
BB28 VCCIO[44] 1
Top Side BC26 +1.05VS
VCCIO[45]

PCI E*
1U_0402_6.3V4Z 1U_0402_6.3V4Z BC28 C516
VCCIO[46] 1U_0402_6.3V4Z @
BD26 VCCIO[47] 1 2
2 R570 0_0805_5%
BD28 VCCIO[48] 156mA
BE26 VCCIO[49] VCCPNAND[1] AM16 Near AT16
BE28 VCCIO[50] VCCPNAND[2] AK16
BG26 VCCIO[51] VCCPNAND[3] AK20
BG28 VCCIO[52] VCCPNAND[4] AK19
Near AN35 BH27 VCCIO[53] VCCPNAND[5] AK15
+VCCQ_NAND +1.8VS
VCCPNAND[6] AK13
+3VS AN30 AM12
Follow Intel suggestion 8/21 VCCIO[54] VCCPNAND[7]

NAND / SPI
AN31 VCCIO[55] VCCPNAND[8] AM13
VCCPNAND[9] AM15 1 2
0.1U_0402_16V4Z 1 R527 0_0805_5%
B C556 2 C514 B
1 AN35 VCC3_3[1]
+1.05VS 0.1U_0402_16V4Z
2
+VCCVRM AT22 VCCVRM[1]
85mA Near AK13
L7 1 @ 2 +VCCAPLL_FDI BJ18 6mA AM8
1UH_CBC2012T1R0M_20% VCCFDIPLL VCCME3_3[1] +3VS
1 VCCME3_3[2] AM9
FDI

1uH inductor, 405mA +1.05VS AM23 AP11

C223 VCCIO[1] VCCME3_3[3]
VCCME3_3[4] AP9
Change to 0 ohm 10U_0805_10V4Z 1
for discrete @ 2 C506
REV1.0
IBEXPEAK-M_FCBGA107 0.1U_0402_16V4Z
2
Near AM8

DG 0.8 is 1uH Inductor (Page 291)

Have Internal VRM (DG0.8 Page 293)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 19 of 60
5 4 3 2 1
 5 4 3 2 1

+1.05VS U18J POWER

DG 0.8 is 10uH Inductor (Page 290) L43 1 @ 2 +1.1VS_VCCACLK AP51
52mA REV1.0 V24
VCCACLK[1] VCCIO[5] +1.05VS
Have Internal VRM (DG0.8 Page 293) 10UH_LB2012T100MR_20% 1 1 VCCIO[6] V26 1
10uH inductor, 120mA AP53 Y24 +1.05VS +VCCADPLLA
C608 C599 VCCACLK[2] VCCIO[7] C540
VCCIO[8] Y26
10U_0805_10V4Z 1U_0402_6.3V4Z 344mA 1U_0402_6.3V4Z
+1.05VS 2 2 2
@ @ AF23 VCCLAN[1] VCCSUS3_3[1] V28
+3VALW
Near BB51
Near AP51 VCCSUS3_3[2] U28 Near V24 L11 1 2
R592 1 @ 2 AF24 U26 10UH_LB2012T100MR_20%
VCCLAN[2] VCCSUS3_3[3]
0_0603_5% 1 VCCSUS3_3[4] U24 10uH inductor, 120mA
1 1

1
P28 1 1 R208
VCCSUS3_3[5]

1
D R579 C532 +PCH_VCCD6W Y20 P26 C227 C534 C594+ 0_0402_5% D
0_0402_5% 1U_0402_6.3V4Z DCPSUSBYP VCCSUS3_3[6] C261 1U_0402_6.3V4Z @
1 VCCSUS3_3[7] N28
@ 2 C520 0.1U_0402_16V4Z 0.1U_0402_16V4Z 220U_B2_2.5VM_R35 2
1998mA VCCSUS3_3[8] N26
2 2 2
AD38 M28

2
VCCME[1] VCCSUS3_3[9]
0.1U_0402_16V4Z M26 Near A26 Near U23

2
2 VCCSUS3_3[10] +VCCADPLLB
Near AF23 AD39 L28

USB
VCCME[2] VCCSUS3_3[11]
VCCSUS3_3[12] L26
Near Y20 AD41 VCCME[3] VCCSUS3_3[13] J28
J26 L10 1 2
+1.05VS VCCSUS3_3[14]
Follow Intel suggestion AF43 VCCME[4] VCCSUS3_3[15] H28 10UH_LB2012T100MR_20%
VCCSUS3_3[16] H26 10uH inductor, 120mA 1 1
22U_0805_6.3V6M AF41 163mA G28
VCCME[5] VCCSUS3_3[17] C595+
1 1 1 1 1 VCCSUS3_3[18] G26
AF42 F28 C260 1U_0402_6.3V4Z
C230 C559 C587 C229 C588 VCCME[6] VCCSUS3_3[19] 220U_B2_2.5VM_R35 2
VCCSUS3_3[20] F26
+3VALW 2
2 2 2
22U_0805_6.3V6M
2 2
V39 VCCME[7] VCCSUS3_3[21] E28 Near BD51
1U_0402_6.3V4Z E26

Clock and Miscellaneous

VCCSUS3_3[22] D11
V41 VCCME[8] VCCSUS3_3[23] C28

2
22U_0805_6.3V6M Near AD38 1U_0402_6.3V4Z Near V39 VCCSUS3_3[24] C26 CH751H-40PT_SOD323-2
V42 VCCME[9] VCCSUS3_3[25] B27
VCCSUS3_3[26] A28
Y39 VCCME[10] VCCSUS3_3[27] A26
All Ibex Peak-M Power rails with netnames +1.1VS and +1.05VS 2/12 Follow

1
Y41 U23 EDS1.11 Change +3VS
+1.1V rails are actually +1.05VS and +1.05V rails VCCME[11] VCCSUS3_3[28] +5VALW
to 100 ohm
Y42 VCCME[12] VCCIO[56] V23

2
R589 D15
Near V9 C503 >1mA V5REF_SUS F24 +VCC5REFSUS 1 2 100_0402_5% CH751H-40PT_SOD323-2
0.1U_0402_16V4Z
C 1 2 +VCCRTCEXT V9 DCPRTC 2 1 C536 2/12 Follow EDS1.11 C
1U_0402_6.3V6K R630 Change to 100 ohm

1
>1mA Near F24 100_0402_5%
K49 +VCC5REF 1 2 +5VS
V5REF
+VCCVRM AU24 VCCVRM[3]
Change to 1U for power

PCI/GPIO/LPC
357mA sequence issue on ICH9 2 1 C593
72mA J38 1U_0402_6.3V6K
VCC3_3[8]
+VCCADPLLA BB51 VCCADPLLA[1] Near K49
BB53 VCCADPLLA[2] VCC3_3[9] L38
+3VS
73mA VCC3_3[10] M36
+VCCADPLLB BD51 VCCADPLLB[1]
+1.05VS BD53 N36
VCCADPLLB[2] VCC3_3[11]
Near AF32 Near AH23 1
AH23 P36 C558
VCCIO[21] VCC3_3[12]
AJ35 VCCIO[22]
1 1 1 AH35 U35 0.1U_0402_16V4Z
C546 C533 VCCIO[23] VCC3_3[13] 2 +3VS
C555 AF34 VCCIO[2] Near J38
1U_0402_6.3V4Z
2 2 2
1U_0402_6.3V4Z
VCC3_3[14] AD13 Near AD13 +1.05VS
AH34 VCCIO[3]
Near AH35 1 2 C508
1U_0402_6.3V4Z AF32 32mA 0.1U_0402_16V4Z
VCCIO[4] +VCCSATAPLL L6 1 @
VCCSATAPLL[1] AK3 2
1 2 +VCCSST V12 DCPSST VCCSATAPLL[2] AK1 1 1 10UH_LB2012T100MR_20% DG 0.8 is 10uH Inductor (Page 291)
C509 Near V12 10uH inductor, 120mA Have Internal VRM (DG0.8 Page 293)
0.1U_0402_16V4Z C181 C183
+1.05VS 10U_0805_10V4Z 1U_0402_6.3V4Z
+VCCSUS @ 2 @ 2
1 2 Y22 DCPSUS
B B
+3VALW
C531 Near Y22 VCCIO[9] AH22 Near AK1
0.1U_0402_16V4Z

P18 VCCSUS3_3[29] VCCVRM[4] AT20 +VCCVRM

1
C515 U19
SATA

VCCSUS3_3[30] +1.05VS
PCI/GPIO/LPC

VCCIO[10] AH19
0.1U_0402_16V4Z U20
2 VCCSUS3_3[31]
VCCIO[11] AD20
Near P18 U22 VCCSUS3_3[32]
VCCIO[12] AF22 1
+3VS
AD19 C517
VCCIO[13] 1U_0402_6.3V4Z
V15 VCC3_3[5] VCCIO[14] AF20
2
1 VCCIO[15] AF19
C513 V16 VCC3_3[6] VCCIO[16] AH20 Near AB19
0.1U_0402_16V4Z Y16 AB19
2 VCC3_3[7] VCCIO[17]
VCCIO[18] AB20
+1.1VS_VTT Near V15 AB22 +1.05VS
VCCIO[19]
> 1mA VCCIO[20] AD22
AT18 V_CPU_IO[1]
1 1 1 AA34 PCH_VCCME13 R599 1 2 0_0603_5%
CPU

C530 C522 C521 VCCME[13] PCH_VCCME14 R232 0_0603_5%

VCCME[14] Y34 1 2
AU18 Y35 PCH_VCCME15 R234 1 2 0_0603_5%
4.7U_0805_10V4Z 0.1U_0402_16V4Z V_CPU_IO[2] VCCME[15] PCH_VCCME16 R233 0_0603_5%
VCCME[16] AA35 1 2
2 2 2
0.1U_0402_16V4Z Near AT18 2mA 6mA
RTC

A A12 VCCRTC VCCSUSHDA L30 +3VALW A

HDA

C541 1 2 1U_0402_6.3V4Z
IBEXPEAK-M_FCBGA107
+RTCVCC Near L30
1 1 1
C512 C510
C504 Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z 2009/5/12 2010/04/15 Title
1U_0402_6.3V4Z 2 2 2 Issued Date Deciphered Date
Near A12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (8/9) PWR
0.1U_0402_16V4Z Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 20 of 60
5 4 3 2 1
 5 4 3 2 1

U18I U18H
AY7 VSS[159] VSS[259] H49 AB16 VSS[0]
B11 VSS[160] VSS[260] H5
B15 VSS[161] VSS[261] J24 AA19 VSS[1] VSS[80] AK30
B19 VSS[162] VSS[262] K11 AA20 VSS[2] VSS[81] AK31
B23 VSS[163] VSS[263] K43 AA22 VSS[3] VSS[82] AK32
B31 VSS[164] VSS[264] K47 AM19 VSS[4] VSS[83] AK34
B35 VSS[165] VSS[265] K7 AA24 VSS[5] VSS[84] AK35
B39 VSS[166] VSS[266] L14 AA26 VSS[6] VSS[85] AK38
B43 VSS[167] VSS[267] L18 AA28 VSS[7] VSS[86] AK43
B47 VSS[168] VSS[268] L2 AA30 VSS[8] VSS[87] AK46
B7 VSS[169] VSS[269] L22 AA31 VSS[9] VSS[88] AK49
D BG12 VSS[170] VSS[270] L32 AA32 VSS[10] VSS[89] AK5 D
BB12 VSS[171] VSS[271] L36 AB11 VSS[11] VSS[90] AK8
BB16 VSS[172] VSS[272] L40 AB15 VSS[12] VSS[91] AL2
BB20 VSS[173] VSS[273] L52 AB23 VSS[13] VSS[92] AL52
BB24 VSS[174] VSS[274] M12 AB30 VSS[14] VSS[93] AM11
BB30 VSS[175] VSS[275] M16 AB31 VSS[15] VSS[94] BB44
BB34 VSS[176] VSS[276] M20 AB32 VSS[16] VSS[95] AD24
BB38 VSS[177] VSS[277] N38 AB39 VSS[17] VSS[96] AM20
BB42 VSS[178] VSS[278] M34 AB43 VSS[18] VSS[97] AM22
BB49 VSS[179] VSS[279] M38 AB47 VSS[19] VSS[98] AM24
BB5 VSS[180] VSS[280] M42 AB5 VSS[20] VSS[99] AM26
BC10 VSS[181] VSS[281] M46 AB8 VSS[21] VSS[100] AM28
BC14 VSS[182] VSS[282] M49 AC2 VSS[22] VSS[101] BA42
BC18 VSS[183] VSS[283] M5 AC52 VSS[23] VSS[102] AM30
BC2 VSS[184] VSS[284] M8 AD11 VSS[24] VSS[103] AM31
BC22 VSS[185] VSS[285] N24 AD12 VSS[25] VSS[104] AM32
BC32 VSS[186] VSS[286] P11 AD16 VSS[26] VSS[105] AM34
BC36 VSS[187] VSS[287] AD15 AD23 VSS[27] VSS[106] AM35
BC40 VSS[188] VSS[288] P22 AD30 VSS[28] VSS[107] AM38
BC44 VSS[189] VSS[289] P30 AD31 VSS[29] VSS[108] AM39
BC52 VSS[190] VSS[290] P32 AD32 VSS[30] VSS[109] AM42
BH9 VSS[191] VSS[291] P34 AD34 VSS[31] VSS[110] AU20
BD48 VSS[192] VSS[292] P42 AU22 VSS[32] VSS[111] AM46
BD49 VSS[193] VSS[293] P45 AD42 VSS[33] VSS[112] AV22
BD5 VSS[194] VSS[294] P47 AD46 VSS[34] VSS[113] AM49
BE12 VSS[195] VSS[295] R2 AD49 VSS[35] VSS[114] AM7
BE16 VSS[196] VSS[296] R52 AD7 VSS[36] VSS[115] AA50
BE20 VSS[197] VSS[297] T12 AE2 VSS[37] VSS[116] BB10
BE24 VSS[198] VSS[298] T41 AE4 VSS[38] VSS[117] AN32
C BE30 T46 AF12 AN50 C
VSS[199] VSS[299] VSS[39] VSS[118]
BE34 VSS[200] VSS[300] T49 Y13 VSS[40] VSS[119] AN52
BE38 VSS[201] VSS[301] T5 AH49 VSS[41] VSS[120] AP12
BE42 VSS[202] VSS[302] T8 AU4 VSS[42] VSS[121] AP42
BE46 VSS[203] VSS[303] U30 AF35 VSS[43] VSS[122] AP46
BE48 VSS[204] VSS[304] U31 AP13 VSS[44] VSS[123] AP49
BE50 VSS[205] VSS[305] U32 AN34 VSS[45] VSS[124] AP5
BE6 VSS[206] VSS[306] U34 AF45 VSS[46] VSS[125] AP8
BE8 VSS[207] VSS[307] P38 AF46 VSS[47] VSS[126] AR2
BF3 VSS[208] VSS[308] V11 AF49 VSS[48] VSS[127] AR52
BF49 VSS[209] VSS[309] P16 AF5 VSS[49] VSS[128] AT11
BF51 VSS[210] VSS[310] V19 AF8 VSS[50] VSS[129] BA12
BG18 VSS[211] VSS[311] V20 AG2 VSS[51] VSS[130] AH48
BG24 VSS[212] VSS[312] V22 AG52 VSS[52] VSS[131] AT32
BG4 VSS[213] VSS[313] V30 AH11 VSS[53] VSS[132] AT36
BG50 VSS[214] VSS[314] V31 AH15 VSS[54] VSS[133] AT41
BH11 VSS[215] VSS[315] V32 AH16 VSS[55] VSS[134] AT47
BH15 VSS[216] VSS[316] V34 AH24 VSS[56] VSS[135] AT7
BH19 VSS[217] VSS[317] V35 AH32 VSS[57] VSS[136] AV12
BH23 VSS[218] VSS[318] V38 AV18 VSS[58] VSS[137] AV16
BH31 VSS[219] VSS[319] V43 AH43 VSS[59] VSS[138] AV20
BH35 VSS[220] VSS[320] V45 AH47 VSS[60] VSS[139] AV24
BH39 VSS[221] VSS[321] V46 AH7 VSS[61] VSS[140] AV30
BH43 VSS[222] VSS[322] V47 AJ19 VSS[62] VSS[141] AV34
BH47 VSS[223] VSS[323] V49 AJ2 VSS[63] VSS[142] AV38
BH7 VSS[224] VSS[324] V5 AJ20 VSS[64] VSS[143] AV42
C12 VSS[225] VSS[325] V7 AJ22 VSS[65] VSS[144] AV46
C50 VSS[226] VSS[326] V8 AJ23 VSS[66] VSS[145] AV49
D51 VSS[227] VSS[327] W2 AJ26 VSS[67] VSS[146] AV5
B B
E12 VSS[228] VSS[328] W52 AJ28 VSS[68] VSS[147] AV8
E16 VSS[229] VSS[329] Y11 AJ32 VSS[69] VSS[148] AW14
E20 VSS[230] VSS[330] Y12 AJ34 VSS[70] VSS[149] AW18
E24 VSS[231] VSS[331] Y15 AT5 VSS[71] VSS[150] AW2
E30 VSS[232] VSS[332] Y19 AJ4 VSS[72] VSS[151] BF9
E34 VSS[233] VSS[333] Y23 AK12 VSS[73] VSS[152] AW32
E38 VSS[234] VSS[334] Y28 AM41 VSS[74] VSS[153] AW36
E42 VSS[235] VSS[335] Y30 AN19 VSS[75] VSS[154] AW40
E46 VSS[236] VSS[336] Y31 AK26 VSS[76] VSS[155] AW52
E48 VSS[237] VSS[337] Y32 AK22 VSS[77] VSS[156] AY11
E6 VSS[238] VSS[338] Y38 AK23 VSS[78] VSS[157] AY43
E8
F49
VSS[239] VSS[339] Y43
Y46
AK28 VSS[79] REV1.0 VSS[158] AY47
VSS[240] VSS[340] IBEXPEAK-M_FCBGA107
@
F5 VSS[241] VSS[341] P49
G10 VSS[242] VSS[342] Y5
G14 VSS[243] VSS[343] Y6
G18 VSS[244] VSS[344] Y8
G2 VSS[245] VSS[345] P24
G22 VSS[246] VSS[346] T43
G32 VSS[247] VSS[347] AD51
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
H30 VSS[255] VSS[355] AK45
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

REV1.0
IBEXPEAK-M_FCBGA107 Security Classification Compal Secret Data Compal Electronics, Inc.
@ Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS & PCH XDP Port
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 21 of 60
5 4 3 2 1
 A B C D E

U35A

4 PEG_HTX_C_GRX_P0 AP17 Part 1 of 7 K1 GPIO I/O ACTIVE USAGE

PEX_RX0 GPIO0 @
4 PEG_HTX_C_GRX_N0 AN17 K2 VGA_HDMI_DET 30 2 1 +3VS_DELAY
PEX_RX0_N GPIO1 R716 2.2K_0402_5%
4 PEG_HTX_C_GRX_P1 AN19 K3 VGA_PNL_PWM 28
PEX_RX1 GPIO2
4 PEG_HTX_C_GRX_N1 AP19 PEX_RX1_N GPIO3 H3 ENVDD 28 GPIO0 IN N/A N/A
4 PEG_HTX_C_GRX_P2 AR19 H2 VGA_BKL_EN 16
PEX_RX2 GPIO4
4 PEG_HTX_C_GRX_N2 AR20 H1 GPU_VID0 52
PEX_RX2_N GPIO5 @
4 PEG_HTX_C_GRX_P3 AP20 PEX_RX3 GPIO6 H4 GPU_VID1 52
R93
2 1
2.2K_0402_5%
+3VS_DELAY GPIO1 IN H HDMI Hot-plug
4 PEG_HTX_C_GRX_N3 AN20 H5
PEX_RX3_N GPIO7
4 PEG_HTX_C_GRX_P4 AN22 PEX_RX4 GPIO8 H6 1 DIS@ 2 +3VS_DELAY
4 PEG_HTX_C_GRX_N4 AP22 J7 R7141 DIS@ 10K_0402_5%
2 GPIO2 OUT H VGA_PNL_PWM
PEX_RX4_N GPIO9 R715 10K_0402_5%
4 PEG_HTX_C_GRX_P5 AR22 K4
PEX_RX5 GPIO10
4 PEG_HTX_C_GRX_N5 AR23 PEX_RX5_N GPIO11 K5 1 DIS@ 2
AP23 H7 R67 10K_0402_5% GPIO3 OUT H ENVDD

GPIO
4 PEG_HTX_C_GRX_P6 PEX_RX6 GPIO12
1 4 PEG_HTX_C_GRX_N6 AN23 J4 1
PEX_RX6_N GPIO13
4 PEG_HTX_C_GRX_P7 AN25 PEX_RX7 GPIO14 J6 1 DIS@ 2
4 PEG_HTX_C_GRX_N7 AP25 L1 R63 10K_0402_5% GPIO4 OUT H VGA_BKL_EN
PEX_RX7_N GPIO15
4 PEG_HTX_C_GRX_P8 AR25 L2
PEX_RX8 GPIO16 Q65 2N7002_SOT23
4 PEG_HTX_C_GRX_N8 AR26 PEX_RX8_N GPIO17 L4

D
4 PEG_HTX_C_GRX_P9 AP26
PEX_RX9 GPIO18
M4 3 1 VGA_idle 37 GPIO5 OUT N/A NVVDD VID0
4 PEG_HTX_C_GRX_N9 AN26 PEX_RX9_N GPIO19 L7
4 PEG_HTX_C_GRX_P10 AN28 PEX_RX10 GPIO20 L5
GPIO6 OUT N/A NVVDD VID1

G
4 PEG_HTX_C_GRX_N10 AP28 K6

2
PEX_RX10_N GPIO21
4 PEG_HTX_C_GRX_P11 AR28 L6 +3VS_DELAY
PEX_RX11 GPIO22 DIS@
4 PEG_HTX_C_GRX_N11 AR29 M6
PEX_RX11_N GPIO23
4 PEG_HTX_C_GRX_P12 AP29
PEX_RX12 GPIO7 OUT N/A N/A
4 PEG_HTX_C_GRX_N12 AN29 PEX_RX12_N 1 2 +3VS_DELAY
4 PEG_HTX_C_GRX_P13 AN31 N1 R740 DIS@ 10K_0402_5%
PEX_RX13 NC
4 PEG_HTX_C_GRX_N13 AP31
PEX_RX13_N NC
P4 GPIO8 IN L N/A
4 PEG_HTX_C_GRX_P14 AR31 P1
PEX_RX14 NC
4 PEG_HTX_C_GRX_N14 AR32 P2
PEX_RX14_N NC +3VS_DELAY
4 PEG_HTX_C_GRX_P15 AR34
PEX_RX15 NC
P3 GPIO9 OUT L N/A
4 PEG_HTX_C_GRX_N15 AP34 T3
PEX_RX15_N NC
NC T2

DIS@ C151 0.1U_0402_16V7K PEX_TXP0 NC

T1
DIS@ DIS@
1
HDCP@
GPIO10 OUT N/A N/A
4 PEG_GTX_C_HRX_P0 1 2 AL17 PEX_TX0 NC U4

1
DIS@ C146 1 2 0.1U_0402_16V7K PEX_TXN0 AM17 U1 C81
4 PEG_GTX_C_HRX_N0 PEX_TX0_N NC
DIS@ C129 1 2 0.1U_0402_16V7K PEX_TXP1 AM18 U2 R36 R37 @ 0.1U_0402_16V4Z GPIO11 OUT N/A N/A
4 PEG_GTX_C_HRX_P1 PEX_TX1 NC 2

PCI EXPRESS
DIS@ C124 1 2 0.1U_0402_16V7K PEX_TXN1 AM19 U3 2.2K_0402_5% 2.2K_0402_5% R44
4 PEG_GTX_C_HRX_N1 PEX_TX1_N NC
DIS@ C139 1 2 0.1U_0402_16V7K PEX_TXP2 AL19 R6 10K_0402_5% U9 HDCP@
4 PEG_GTX_C_HRX_P2 PEX_TX2 NC
DIS@ C135 1 2 0.1U_0402_16V7K PEX_TXN2 AK19 T6 8 1 GPIO12 IN N/A N/A

DVO
4 PEG_GTX_C_HRX_N2

2
DIS@ C121 0.1U_0402_16V7K PEX_TXP3 PEX_TX2_N NC VCC A0
4 PEG_GTX_C_HRX_P3 1 2 AL20 PEX_TX3 NC N6 7 WP A1 2
DIS@ C118 1 2 0.1U_0402_16V7K PEX_TXN3 AM20 N2 HDCP_SCL 6 3
4 PEG_GTX_C_HRX_N3 PEX_TX3_N NC SCL A2
DIS@ C130 1 2 0.1U_0402_16V7K PEX_TXP4 AM21 N3 HDCP_SDA 5 4 GPIO13 OUT N/A N/A
4 PEG_GTX_C_HRX_P4 PEX_TX4 NC SDA GND
DIS@ C126 1 2 0.1U_0402_16V7K PEX_TXN4 AM22 L3
4 PEG_GTX_C_HRX_N4 PEX_TX4_N NC

1
DIS@ C116 1 2 0.1U_0402_16V7K PEX_TXP5 AL22 P5 AT24C16AN-10SU-2.7_SO8
4 PEG_GTX_C_HRX_P5 PEX_TX5 NC
DIS@ C112 1 2 0.1U_0402_16V7K PEX_TXN5 AK22 N5 @ GPIO14 OUT N/A N/A
2 4 PEG_GTX_C_HRX_N5 PEX_TX5_N NC 2
DIS@ C104 1 2 0.1U_0402_16V7K PEX_TXP6 AL23 N4 R39 HDCP@ R48
4 PEG_GTX_C_HRX_P6 PEX_TX6 NC
DIS@ C101 1 2 0.1U_0402_16V7K PEX_TXN6 AM23 R4 2.2K_0402_5% 100K_0402_1%
4 PEG_GTX_C_HRX_N6 PEX_TX6_N NC
DIS@ C110 1 2 0.1U_0402_16V7K PEX_TXP7 AM24 U5
4 PEG_GTX_C_HRX_P7

2
DIS@ C106 0.1U_0402_16V7K PEX_TXN7 PEX_TX7 NC
4 PEG_GTX_C_HRX_N7 1 2 AM25 T5
DIS@ C96 0.1U_0402_16V7K PEX_TXP8 PEX_TX7_N NC
4 PEG_GTX_C_HRX_P8 1 2 AL25 T4
DIS@ C92 0.1U_0402_16V7K PEX_TXN8 PEX_TX8 NC
4 PEG_GTX_C_HRX_N8 1 2 AK25
DIS@ C102 0.1U_0402_16V7K PEX_TX8_N
4 PEG_GTX_C_HRX_P9 1 2 PEX_TXP9 AL26 1 @ 2 XTALIN
DIS@ C97 0.1U_0402_16V7K PEX_TXN9
PEX_TX9 12 27M_CLK R70 0_0402_5%
4 PEG_GTX_C_HRX_N9 1 2 AM26 Y1
DIS@ C94 0.1U_0402_16V7K PEX_TXP10 PEX_TX9_N MIOB_D0
4 PEG_GTX_C_HRX_P10 1 2 AM27 Y2
DIS@ C91 0.1U_0402_16V7K PEX_TXN10
PEX_TX10 MIOB_D1 Y2
4 PEG_GTX_C_HRX_N10 1 2 AM28 Y3
DIS@ C67 0.1U_0402_16V7K PEX_TXP11
PEX_TX10_N MIOB_D2 XTALOUT
4 PEG_GTX_C_HRX_P11 1 2 AL28 AB3 3 4
DIS@ C63 0.1U_0402_16V7K PEX_TXN11
PEX_TX11 MIOB_D3 OUT GND
4 PEG_GTX_C_HRX_N11 1 2 AK28 AB2
DIS@ C62 0.1U_0402_16V7K PEX_TXP12 PEX_TX11_N MIOB_D4 VGA_CRT_R
4 PEG_GTX_C_HRX_P12 1 2 AK29 PEX_TX12 MIOB_D5 AB1 1 2 GND IN 1
DIS@ C60 1 2 0.1U_0402_16V7K PEX_TXN12 AL29 AC4
4 PEG_GTX_C_HRX_N12 PEX_TX12_N MIOB_D6
DIS@ C57 1 2 0.1U_0402_16V7K PEX_TXP13 AM29 AC1 VGA_CRT_G C160 1
4 PEG_GTX_C_HRX_P13 PEX_TX13 MIOB_D7
DIS@ C56 1 2 0.1U_0402_16V7K PEX_TXN13 AM30 AC2 18P_0402_50V8J 27MHZ_16PF_X7T027000BG1H-V
4 PEG_GTX_C_HRX_N13 PEX_TX13_N MIOB_D8 2
DIS@ C54 1 2 0.1U_0402_16V7K PEX_TXP14 AM31 AC3 DIS@ DIS@ C161
4 PEG_GTX_C_HRX_P14 PEX_TX14 MIOB_D9
DIS@ C53 1 2 0.1U_0402_16V7K PEX_TXN14 AM32 AE3 VGA_CRT_B 18P_0402_50V8J
4 PEG_GTX_C_HRX_N14 PEX_TX14_N MIOBD_10 2
DIS@ C51 1 2 0.1U_0402_16V7K PEX_TXP15 AN32 AE2 DIS@
4 PEG_GTX_C_HRX_P15 PEX_TX15 MIOB_D11
DIS@ C50 1 2 0.1U_0402_16V7K PEX_TXN15 AP32 U6
4 PEG_GTX_C_HRX_N15 PEX_TX15_N MIOB_D12
+3VS_DELAY MIOB_D13 W6
2

1
Y6
MIOB_D14

150_0402_1%

150_0402_1%

150_0402_1%
R497
10K_0402_5% AR16
DIS@
14 CLK_PEG_VGA
AR17
PEX_REFCLK
W1
External Spread Spectrum OSC_OUT R51 1 2 @ 22_0402_5% XTAL_OUTBUFF
14 CLK_PEG_VGA# PEX_REFCLK_N MIOB_HSYNC
14 PEG_CLKREQ# AR13 W2
1

2
PEX_CLKREQ_N MIOB_VSYNC

1
R57 @ AJ17 U8 R54
PEX_TSTCLK_OUT R62 R61 R58 10K_0402_5%
2 1 AJ18 PEX_TSTCLK_OUT_N MIOB_DE Y5 1 REFOUT VSS 6
200_0402_1% W3 DIS@ DIS@ DIS@ DIS@
MIOB_CTL3 OSC_SPREAD
AF1 2 5

2
MIOB_VREF XOUT MODOUT
17 PLTRST_VGA# AM16
@ PEX_RST_N OSC_OUT
3 2 1 AG21 3 4 +3VS_DELAY 3
R53 2.49K_0402_1% PEX_TERMP XIN/CLKIN VDD OSC_SPREAD R52
1 1 2 @ 22_0402_5% XTAL_SSIN
AE1 1 DIS@ 2 @
MIOB_CLKIN

1
BLM18PG181SN1D_0603 36 mA V4 R487 10K_0402_5% @ ASM3P2872AF-06OR_TSOT-23-6 C86
GPU_PLLVDD
MIOB_CLKOUT 0.1U_0402_16V4Z XTAL_SSIN
+1.05VSDGPU 2 1 AE9
DIS@ L5 PLLVDD 2 12 27M_SSC R55
4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
22U_0805_6.3V6M

1U_0402_6.3V6K

SP_PLLVDD 10K_0402_5%
0.1U_0402_16V4Z

1 1 1 1 1 1 AF9 W4
C492 C169 SP_PLLVDD MIOB_CLKOUT_N DIS@

2
DIS@ C164 C159 C154 C149 AD9
DIS@ DIS@ DIS@ DIS@ DIS@ VID_PLLVDD
AA7
CLK

2 2 2 2 2 2 XTALIN MIOBCAL_PD_VDDQ
B1 AA6
XTALOUT B2
XTAL_IN MIOBCAL_PU_GND If External Spread Spectrum not stuff then stuff resistor
XTAL_OUT
AM15 VGA_CRT_R 29
XTAL_OUTBUFF DACA_RED
D1 XTAL_OUTBUFF DACA_GREEN AM14 VGA_CRT_G 29
+3VS_DELAY XTAL_SSIN D2 AL14
XTAL_SSIN DACA_BLUE VGA_CRT_B 29

DACA_HSYNC AM13 VGA_CRT_HSYNC 29

R471 2 DIS@ 1 2K_0402_5% VGA_DDC_CLK AL13
DACA_VSYNC VGA_CRT_VSYNC 29
R472 2 DIS@ 1 2K_0402_5% VGA_DDC_DATA I2CS_SCL E2 150 mA BLM18PG181SN1D_0603
I2CS_SDA I2CS_SCL DACA_VDD
E1 AJ12 1 2 +3VS_DELAY
R470 2 DIS@ 1 2K_0402_5% VGA_LCD_CLK I2CS_SDA DACA_VDD
2 0.1U_0402_16V4Z DIS@L38
LVDS DACA_VREF AK12 1

470P_0402_50V7K

4700P_0402_25V7K

1U_0402_6.3V6K
R469 2 DIS@ 1 2K_0402_5% VGA_LCD_DAT VGA_LCD_CLK C133 DIS@

4.7U_0603_6.3V6M
E3 I2CC_SCL DACA_RSET AK13 1 2
28 VGA_LCD_CLK VGA_LCD_DAT E4 124_0402_1% R59 DIS@
I2CC_SDA 1 1 1 1
R478 1 DIS@ 22.2K_0402_5% I2CS_SCL 28 VGA_LCD_DAT AK4 C704
DACB_RED
DACs

R477 1 DIS@ 22.2K_0402_5% I2CS_SDA I2CB_SCL G3 AL4 C478 C487 C490

I2CB_SDA I2CB_SCL DACB_GREEN DIS@ DIS@ DIS@ DIS@
G2 AJ4
I2C

R748 1 DIS@ 22.2K_0402_5% I2CB_SCL I2CB_SDA DACB_BLUE 2 2 2 2

R749 1 DIS@ 22.2K_0402_5% I2CB_SDA VGA_DDC_CLK G1 AM1
29 VGA_DDC_CLK VGA_DDC_DATA G4 I2CA_SCL DACB_HSYNC
CRT 29 VGA_DDC_DATA I2CA_SDA DACB_VSYNC
AM2

HDCP_SCL F6 AG7 2 R494 1 0.1U_0402_16V4Z

HDCP_SDA I2CH_SCL DACB_VDD
G6 I2CH_SDA DACB_VREF AK6 10K_0402_5% DIS@ 1 2
AH7 1 R474 2 DIS@ C152
4 Q60A DACB_RSET 124_0402_1% DIS@ 4
2N7002DW-T/R7_SOT363-6 DIS@
I2CS_SCL 1 6 DIS@ N11M-GE1-B-A2_BGA969
EC_SMB_CK2 14,37
BLM18PG181SN1D_0603
+1.05VSDGPU 2 1 SP_PLLVDD
+3VS_DELAY DIS@ L54
2

4.7U_0603_6.3V6M

1U_0402_6.3V6K

Q60B
2N7002DW-T/R7_SOT363-6 DIS@
1
C702
C703
1 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2009/12/31 Title
I2CS_SDA 4 3 DIS@ DIS@
EC_SMB_DA2 14,37 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11M PEG 1/6
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
+3VS_DELAY DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NALG0 M/B LA-5681P Schematic 1.0
5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 23, 2009 Sheet 22 of 60
A B C D E
 5 4 3 2 1

U35D

Part 4 of 7
28 VGA_TXCLK+ AM11 IFPA_TXC NC A2
28 VGA_TXCLK- AM12 IFPA_TXC_N NC C5
28 VGA_TXOUT0+ AM8 IFPA_TXD0 NC D5
28 VGA_TXOUT0- AL8 IFPA_TXD0_N NC E5
28 VGA_TXOUT1+ AM10 IFPA_TXD1 NC E7
28 VGA_TXOUT1- AM9 IFPA_TXD1_N NC F4
28 VGA_TXOUT2+ AK10 IFPA_TXD2 NC G5
28 VGA_TXOUT2- AL10 IFPA_TXD2_N NC G11
AK11 IFPA_TXD3 NC G12
D AL11 IFPA_TXD3_N NC G14 D
NC G15
NC G27
AP13 IFPB_TXC NC G28
AN13 IFPB_TXC_N NC G24
AN8 IFPB_TXD4 NC G25
AP8 IFPB_TXD4_N NC H32
AP10 IFPB_TXD5 NC J18 Straps MULTI LEVEL STRAPS
AN10 J19 STRAP0
IFPB_TXD5_N NC STRAP1
AR11 IFPB_TXD6 NC J25
AR10 J26 STRAP2
IFPB_TXD6_N NC ROM_SI
AN11 IFPB_TXD7 NC L29
AP11 M7 ROM_SO
IFPB_TXD7_N NC ROM_SCLK
NC M29
+3VS_DELAY

NC
NC P6
30 VGA_HDMI_TXD2+ AM7 IFPC_L0 NC P29
30 VGA_HDMI_TXD2- AM6 IFPC_L0_N NC R29
30 VGA_HDMI_TXD1+ AL5 U7 1 @ 2 1 DIS@ 2 strap0
IFPC_L1 NC R493 5.1K_0402_5% R481 45.3K_0402_1%
30 VGA_HDMI_TXD1- AM5 IFPC_L1_N NC V6
30 VGA_HDMI_TXD0+ AM3 IFPC_L2 NC Y4
30 VGA_HDMI_TXD0- AM4 AA4 1 @ 2 DIS@ strap1
IFPC_L2_N NC R492 10K_0402_1% R480 34.8K_0402_1%
30 VGA_HDMI_TXC+ AP1 IFPC_L3 NC AB4

LVDS/TMDS
30 VGA_HDMI_TXC- AR2 IFPC_L3_N NC AB7
AC5 1 2 1 @ 2 strap2
NC R491 30K_0402_5% R479 30K_0402_5%
NC AD6
AR8 IFPD_L0 NC AD29
AR7 IFPD_L0_N NC AE29 1 X76@ 2 1 @ 2 ROM_SI
AP7 AF6 R79 20K_0402_5% R88 5.1K_0402_5%
IFPD_L1 NC
AN7 IFPD_L1_N NC AG6
C AN5 IFPD_L2 NC AG20 1 DIS@ 2 1 @ 2 ROM_SO C
AP5 AG29 R80 10K_0402_1% R89 5.1K_0402_5%
IFPD_L2_N NC
AR5 IFPD_L3 NC AH29
AR4 AJ5 1 @ 2 DIS@ ROM_SCLK
IFPD_L3_N NC R81 5.1K_0402_5% R90 15K_0402_5%
NC AK15
NC AL7
AH6 IFPE_L0
AH5 IFPE_L0_N
AH4 IFPE_L1 ES: pop R479 30K ohm
AG4
AF4
IFPE_L1_N GS: pop R491 30K ohm
IFPE_L2
AF5 IFPE_L2_N
MP ID check R491 and R479
AE6 IFPE_L3
+3VS_DELAY AE5 IFPE_L3_N
D35 R461 1 DIS@ 2 0_0402_5%
VDD_SENSE_0 R68 1 DIS@
AL2 NC VDD_SENSE_1 P7 2 0_0402_5%
1

AL3 AD20 R462 1 DIS@ 2 0_0402_5%

NC VDD_SENSE_2 +NVVDD_SENSE 52
R475 R476 AJ3
4.7K_0402_5% 4.7K_0402_5% AJ2 NC
DIS@ DIS@ NC
AJ1 NC
AH1 AD19 R56 1 DIS@ 2 0_0402_5% strap0 strap1 strap2 ROM_SI ROM_SO ROM_SCLK
2

NC GND_SENSE_0 R443 1 DIS@

AH2 NC GND_SENSE_1 E35 2 0_0402_5%
AH3 R7 R69 1 DIS@ 2 0_0402_5% 64MX16 H H L L L H
NC GND_SENSE_2 Samsung 45K 35K 30K 20K 10K 15K
30 VGA_HDMI_SCLK AP2 SA000035700
IFPC_AUX_I2CW_SCL
30 VGA_HDMI_SDATA AN3 IFPC_AUX_I2CW_SDA_N 64MX16 H H L L L H
Hynix 45K 35K 30K 15K 10K 15K
B
AP4
AN4
IFPD_AUX_I2CX_SCL TEST SA000032400 B
IFPD_AUX_I2CX_SDA_N
AE4 AP35 DIS@ 1 R431 2
IFPE_AUX_I2CY_SCL TESTMODE 10K_0402_5% JTAG_TCK @
AD4 IFPE_AUX_I2CY_SDA_N JTAG_TCK AP14 PAD T11
AN14 JTAG_TDI PAD @
JTAG_TDI T12
AN16 JTAG_TDO PAD @
JTAG_TDO T9
AF3 AR14 JTAG_TMS PAD @
NC JTAG_TMS T10
AF2 AP16 JTAG_TRST PAD @
NC JTAG_TRST_N T8
2 R460 1
A7 10K_0402_5%
DBG_DATA0
B7
C7
DBG_DATA1 DBG SERIAL R468
DIS@
DBG_DATA2 ROM_CS# 10K_0402_5%1
D6 DBG_DATA3 ROM_CS_N C3 2 @ +3VS_DELAY
D7 D3 ROM_SI
DBG_DATA4 ROM_SI ROM_SO
ROM_SO C4
D4 ROM_SCLK
ROM_SCLK

GENERAL A5
NC DIS@ R65
A4 BUFRST_N
MULTI_STRAP_REF0_GND N9 2 1
AB5 40.2K_0402_1%
NC
MULTI_STRAP_REF1_GND M9 2 1
STRAP0 W5 40.2K_0402_1%
STRAP1 STRAP0 DIS@ R66
W7 STRAP1 THERMDP B5
STRAP2 V7 B4
STRAP2 THERMDN
A A

N11M-GE1-B-A2_BGA969

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11M LVDS 2/6
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 23 of 60
5 4 3 2 1
 5 4 3 2 1

U35E

Part 5 of 7 +1.05VSDGPU
FBVDDQ J23 AG11 PEX_IOVDDQ PEX_IOVDDQ
+1.5VSDGPU FBVDDQ_0 PEX_IOVDDQ_0
J24 AG12

1U_0603_10V4Z

4.7U_0603_6.3V6M
FBVDDQ_1 PEX_IOVDDQ_1
J29 AG13 2 1 1 1 1 2 1.920 Amps

10U_0805_6.3V6M

1U_0603_10V4Z
0.1U_0402_16V4Z

0.47U_0402_6.3V6K
FBVDDQ FBVDDQ_2 PEX_IOVDDQ_2 C115 C459 C158
AA27 FBVDDQ_3 PEX_IOVDDQ_3 AG15
AA29 AG16 DIS@ DIS@ DIS@ C89 C70 C142
FBVDDQ_4 PEX_IOVDDQ_4

C58

C55

C68

C75

C69
C114
1 1 1 1 1 1 AA31 AG17 DIS@ DIS@ DIS@

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.022U_0402_16V7K

0.022U_0402_16V7K

0.022U_0402_16V7K
FBVDDQ_5 PEX_IOVDDQ_5 1 2 2 2 2 1
AB27 FBVDDQ_6 PEX_IOVDDQ_6 AG18
AB29 FBVDDQ_7 PEX_IOVDDQ_7 AG22

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
AC27 FBVDDQ_8 PEX_IOVDDQ_8 AG23
2 2 2 2 2 2 AD27 AG24
FBVDDQ_9 PEX_IOVDDQ_9 +1.05VSDGPU
AE27 FBVDDQ_10 PEX_IOVDDQ_10 AG25
D AJ28 FBVDDQ_11 PEX_IOVDDQ_11 AG26 600 mA D
B18 AJ14 PEX_IOVDD
FBVDDQ FBVDDQ_12 PEX_IOVDDQ_12
E21 AJ15

1U_0603_10V4Z

4.7U_0603_6.3V6M
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K
FBVDDQ_13 PEX_IOVDDQ_13
G17 FBVDDQ_14 PEX_IOVDDQ_14 AJ19 1 1 2 1 1 1
C88

C71

C87

C77

C66
C100
1 1 1 1 1 1 G18 AJ21 C93 C132 C493 C148 C99 C111

4700P_0402_25V7K

4700P_0402_25V7K

4700P_0402_25V7K
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.022U_0402_16V7K
FBVDDQ_15 PEX_IOVDDQ_15 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
G22 FBVDDQ_16 PEX_IOVDDQ_16 AJ22
G8 FBVDDQ_17 PEX_IOVDDQ_17 AJ24
2 2 1 2 2 2
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
G9 FBVDDQ_18 PEX_IOVDDQ_18 AJ25
2 2 2 2 2 2 H29 AJ27
FBVDDQ_19 PEX_IOVDDQ_19

POWER
J14 FBVDDQ_20 PEX_IOVDDQ_20 AK18
J15 FBVDDQ_21 PEX_IOVDDQ_21 AK20
J16 FBVDDQ_22 PEX_IOVDDQ_22 AK23
FBVDDQ J17 AK26 PEX_PLLDVDD 2 1 +1.05VSDGPU
FBVDDQ_23 PEX_IOVDDQ_23 L37 DIS@
1 J20 FBVDDQ_24 PEX_IOVDDQ_24 AL16
C76

C64
C103

C436

C144

C108
1 1 1 1 1 J21 1 1 1 1 BLM18PG181SN1D_0603

4700P_0402_25V7K

4700P_0402_25V7K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
4.7U_0603_6.3V6M
0.1U_0402_16V4Z

0.1U_0402_16V4Z
0.022U_0402_16V7K

FBVDDQ_25
J22 120mA

0.01U_0402_25V7K
FBVDDQ_26 C484 C485 C119 C489
N27 FBVDDQ_27
2 PEX_IOVDD DIS@ DIS@ DIS@
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
P27 FBVDDQ_28 PEX_IOVDD_0 AK16
2 2 2 2 2 2 2 2 2

DIS@
R27 FBVDDQ_29 PEX_IOVDD_1 AK17
T27 FBVDDQ_30 PEX_IOVDD_2 AK21
U27 FBVDDQ_31 PEX_IOVDD_3 AK24
U29 FBVDDQ_32 PEX_IOVDD_4 AK27
V27 FBVDDQ_33
+1.05VSDGPU 100mA V29 R91

0.1U_0402_16V4Z
BLM18PG181SN1D_0603 FBVDDQ_34 PEX_SVDD_3V3
follow the DS04644 IFPAB_PLLVDD
V34 FBVDDQ_35 PEX_PLLDVDD
1 1 2 1 +3VS_DELAY
2 1 W27 AG14

0.01U_0402_25V7K
L35
DIS@ FBVDDQ_36 PEX_PLLVDD C176 C175 0_0603_5%
Y27 FBVDDQ_37 DIS@ DIS@
2 2
1 C444 1 C445

DIS@
1 1
1U_0402_6.3V6K
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

IFPAB_PLLVDD AK9 AG19 PEX_SVDD_3V3

C453 C446 1K_0402_1% 2 IFPAB_RSET AJ11 IFPAB_PLLVDD PEX_SVDD_3V3_0
1 IFPAB_RSET PEX_SVDD_3V3_1 F7
DIS@ DIS@ R488 @
DIS@

DIS@

2 2 2 2
IFPA_IOVDD AG9 +3VS_DELAY
IFPB_IOVDD IFPA_IOVDD VDD33
AG10 IFPB_IOVDD VDD33_0 J10
C J11 VDD33 C
VDD33_1
J12

1U_0603_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
IFPC_PLLVDD VDD33_2
AJ9 IFPC_PLLVDD VDD33_3 J13 1 1 1
2 1 IFPC_RSET AK7 IFPC_RSET VDD33_4 J9
DIS@ R467 1K_0402_1% C140 C120 C125
IFPC_IOVDD AJ8 DIS@ DIS@ DIS@
+1.8VSDGPU IFPC_IOVDD 2 2 2
100 mA #SI Change to +VDDMEM18 NC P9
2 1 IFPA_IOVDD IFPC_PLLVDD AC6 R9
IFPD_PLLVDD NC
L4 DIS@ 1K_0402_1% 2 DIS@ 1 R473 IFPD_RSET AB6 IFPD_RSET NC T9
BLM18PG181SN1D_0603 1 1 C162 2 IFPB_IOVDD U9
1U_0402_6.3V6K
4.7U_0603_6.3V6M

0.1U_0402_16V4Z

C150 IFPC_IOVDD NC +VGA_CORE

AK8 IFPD_IOVDD
C168 +VGA_CORE
DIS@ DIS@ U35G
DIS@

MIOB_VDDQ_0 AA9 +3VS_DELAY

2 2 1 1K_0402_5% 1 DIS@ 2 R495 AJ6 AB9
1K_0402_1% 2 DIS@ IFPEF_PLLVDD MIOB_VDDQ_1
1 R78 IFPE_RSET AL1 IFPEF_RSET MIOB_VDDQ_2 W9 AB11 VDD_0 VDD_56 P21
Y9 AB13 Part 7 of 7 P23

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
MIOB_VDDQ_3 VDD_1 VDD_57
1 R482 2 DIS@ AE7 IFPE_IOVDD 1 1 1 1 1 1 1 AB15 VDD_2 VDD_58 P25
1K_0402_5% AB17 R11
C167 C95 C90 C107 C122 C98 C109 VDD_3 VDD_59
AD7 NC AB19 VDD_4 VDD_60 R12
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ AB21 R13
2 2 2 2 2 2 2 VDD_5 VDD_61
AB23 VDD_6 VDD_62 R14
1 C155 2 AB25 R15
470P_0402_50V7K
0.1U_0402_16V4Z

N11M-GE1-B-A2_BGA969 VDD_7 VDD_63

AC11 VDD_8 VDD_64 R16
C156 AC12 R17
DIS@ VDD_9 VDD_65
DIS@

AC13 VDD_10 VDD_66 R18

2 1
AC14 VDD_11 VDD_67 R19
AC15 R20

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K
VDD_12 VDD_68
1 1 1 1 1 1 AC16 VDD_13 VDD_69 R21
AC17 VDD_14 VDD_70 R22
C127 C80 C113 C82 C84 C136 AC18 R23
PWR Sequence DIS@
2
DIS@
2
DIS@
2
DIS@
2
DIS@
2
DIS@
2
AC19
VDD_15
VDD_16
VDD_71
VDD_72 R24
AC20 VDD_17 VDD_73 R25
AC21 VDD_18 VDD_74 T12
+3VS_DELAY AC22 VDD_19 VDD_75 T14
B AC23 VDD_20 VDD_76 T16 B

POWER
follow the DS04644 +VGA_CORE AC24 VDD_21 VDD_77 T18
AC25 VDD_22 VDD_78 T20
+1.8VS AD12 VDD_23 VDD_79 T22
+3VS_DELAY BLM18PG181SN1D_0603
160 mA AD14
AD16
VDD_24 VDD_80 T24
V11
IFPC_PLLVDD VDD_25 VDD_81
2 1 AD18 VDD_26 VDD_82 V13
L3 DIS@ AD22 V15
+VGA_CORE VDD_27 VDD_83
AD24 V17
4700P_0402_25V7K
1U_0402_6.3V6K

4.7U_0603_6.3V6M

VDD_28 VDD_84
1 1 1 1 L11 VDD_29 VDD_85 V19
DIS@ +3VS
C491

L12 V21
470P_0402_50V7K

C157 VDD_30 VDD_86

C166

C163

L13 VDD_31 VDD_87 V23

L14 V25

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_16V4Z
0.47U_0402_6.3V6K
2 2 2 2 +3VS_DELAY VDD_32 VDD_88
DIS@

1 1 1 1 1 1 L15 VDD_33 VDD_89 W11

C78
DIS@

DIS@

L16 VDD_34 VDD_90 W12

1 C710 + DIS@ C65 C85 C128 C117 L17 W13
C718 R744 1 @ VDD_35 VDD_91
2 0_0805_5% @ DIS@ DIS@ DIS@ DIS@ L18 VDD_36 VDD_92 W14
DIS@ 330U_X_2VM_R6M 2 2 2 2 2 L19 W15
10U_0805_10V4Z 2 VDD_37 VDD_93
L20 VDD_38 VDD_94 W16
2 L21 W17
AO3413_SOT23-3 VDD_39 VDD_95
L22 VDD_40 VDD_96 W18
+3VALW Q10 100mil(1.5A) L23 VDD_41 VDD_97 W19
S

3 1 DIS@ L24 VDD_42 VDD_98 W20

1

385 mA L25 VDD_43 VDD_99 W21

2

+1.05VSDGPU BLM18PG181SN1D_0603 1 M12 W22

IFPC_IOVDD R673 C717 R743 VDD_44 VDD_100
2 1
G

M14 W23
2

L36 DIS@ 100K_0402_5% DIS@ 470_0603_5% VDD_45 VDD_101

3VSdelay_gate

M16 W24
4700P_0402_25V7K
1U_0402_6.3V6K

4.7U_0603_6.3V6M

10U_0805_10V4Z DIS@ VDD_46 VDD_102

1 1 1 1 M18 W25
2

2 VDD_47 VDD_103
C83

C486

C488

M20 Y12
470P_0402_50V7K

3 1

DIS@ VDD_48 VDD_104

1 2 M22 VDD_49 VDD_105 Y14
C483 R745 DIS@ 1K_0402_5% M24 Y16
2 2 2 2 2N7002DW-T/R7_SOT363-6 VDD_50 VDD_106
DIS@

DIS@

DIS@

P11 VDD_51 VDD_107 Y18

6

Q66B P13 Y20

VDD_52 VDD_108
R678 DIS@ 1 53VSdelay_gate P15 VDD_53 VDD_109 Y22
1K_0402_5% Q66A C719 DIS@ P17 Y24
0.1U_0603_25V7K VDD_54 VDD_110
A 39,43,52 VGA_ON 2 1 2 P19 A
4

DIS@ DIS@ VDD_55

1 2
C720 2N7002DW-T/R7_SOT363-6
1

0.1U_0603_25V7K DIS@
2
N11M-GE1-B-A2_BGA969

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11M POWER & GND 3/6
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom NALG0 M/B LA-5681P Schematic 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 23, 2009 Sheet 24 of 60
5 4 3 2 1
 A

VRAM Interface MDA[15..0]

U35C

Part 3 of 7 B3
U35F

Part 6 of 7
26 MDA[15..0] GND_0
B13 NC NC C17 B6 GND_1 GND_97 V18
MDA[31..16] D13 B19 B9 V20
26 MDA[31..16] NC NC GND_2 GND_98
A13 NC NC D18 B12 GND_3 GND_99 V22
MDA[47..32] A14 F21 B15 V24
27 MDA[47..32] NC NC GND_4 GND_100
C16 NC NC A23 B21 GND_5 GND_101 V31
MDA[63..48] B16 D21 B24 Y11
27 MDA[63..48] NC NC GND_6 GND_102
A17 NC NC B23 B27 GND_7 GND_103 Y13
D16 NC NC E20 B30 GND_8 GND_104 Y15
U35B C13 G21 B33 Y17
CMDA[30..0] 26,27 NC NC GND_9 GND_105
B11 NC NC F20 C2 GND_10 GND_106 Y19
Part 2 of 7 V32 CMDA0 C11 F19 C34 Y21
MDA0 FBA_CMD0 CMDA1 NC NC GND_11 GND_107
L32 FBA_D0 FBA_CMD1 W31 A11 NC NC F23 E6 GND_12 GND_108 Y23
MDA1 N33 U31 CMDA2 C10 A22 E9 Y25
MDA2 FBA_D1 FBA_CMD2 CMDA3 NC NC GND_13 GND_109
L33 FBA_D2 FBA_CMD3 Y32 C8 NC NC C22 E12 GND_14 GND_110 AA2
MDA3 N34 AB35 CMDA4 B8 B17 E15 AA5
MDA4 FBA_D3 FBA_CMD4 CMDA5 NC NC GND_15 GND_111
N35 FBA_D4 FBA_CMD5 AB34 A8 NC NC F24 E18 GND_16 GND_112 AA11
MDA5 P35 W35 CMDA6 E8 C25 E24 AA12
MDA6 FBA_D5 FBA_CMD6 CMDA7 NC NC GND_17 GND_113
P33 FBA_D6 FBA_CMD7 W33 F8 NC NC E22 E27 GND_18 GND_114 AA13
MDA7 P34 W30 CMDA8 F10 C20 E30 AA14
MDA8 FBA_D7 FBA_CMD8 CMDA9 NC NC GND_19 GND_115
K35 FBA_D8 FBA_CMD9 T34 F9 NC NC B22 F2 GND_20 GND_116 AA15
MDA9 K33 T35 CMDA10 F12 A19 F31 AA16
MDA10 FBA_D9 FBA_CMD10 CMDA11 NC NC GND_21 GND_117
K34 FBA_D10 FBA_CMD11 AB31 D8 NC NC D22 F34 GND_22 GND_118 AA17
MDA11 H33 Y30 CMDA12 D11 D20 F5 AA18
MDA12 FBA_D11 FBA_CMD12 CMDA13 NC NC GND_23 GND_119
G34 FBA_D12 FBA_CMD13 Y34 E11 NC NC E19 J2 GND_24 GND_120 AA19
MDA13 G33 W32 CMDA14 D12 D19 J5 AA20
MDA14 FBA_D13 FBA_CMD14 CMDA15 NC NC GND_25 GND_121
E34 FBA_D14 FBA_CMD15 AA30 E13 NC NC F18 J31 GND_26 GND_122 AA21

MEMORY INTERFACE C
MDA15 E33 AA32 CMDA16 F13 C19 J34 AA22
MDA16 FBA_D15 FBA_CMD16 CMDA17 NC NC GND_27 GND_123
G31 FBA_D16 FBA_CMD17 Y33 F14 NC NC F22 K9 GND_28 GND_124 AA23
MDA17 F30 U32 CMDA18 F15 C23 L9 AA24
MDA18 FBA_D17 FBA_CMD18 CMDA19 NC NC GND_29 GND_125
G30 FBA_D18 FBA_CMD19 Y31 E16 NC NC B20 M2 GND_30 GND_126 AA25
MDA19 G32 U34 CMDA20 F16 A20 M5 AA34
MDA20 FBA_D19 FBA_CMD20 CMDA21 NC NC GND_31 GND_127
K30 FBA_D20 FBA_CMD21 Y35 F17 NC M11 GND_32 GND_128 AB12
MDA21 K32 W34 CMDA22 D29 M13 AB14
MDA22 FBA_D21 FBA_CMD22 CMDA23 NC GND_33 GND_129
H30 FBA_D22 FBA_CMD23 V30 F27 NC M15 GND_34 GND_130 AB16
MDA23 K31 U35 CMDA24 F28 A16 M17 AB18
MDA24 FBA_D23 FBA_CMD24 CMDA25 NC NC GND_35 GND_131
L31 FBA_D24 FBA_CMD25 U30 E28 NC NC D10 M19 GND_36 GND_132 AB20
MDA25 L30 U33 CMDA26 D26 F11 M21 AB22
FBA_D25 FBA_CMD26 NC NC GND_37 GND_133
MEMORY INTERFACE

MDA26 M32 AB30 CMDA27 F25 D15 M23 AB24

MDA27 FBA_D26 FBA_CMD27 CMDA28 NC NC GND_38 GND_134
N30 FBA_D27 FBA_CMD28 AB33 D24 NC NC D27 M25 GND_39 GND_135 AC9
MDA28 M30 T33 CMDA29 E25 D34 M31 AD2
MDA29 FBA_D28 FBA_CMD29 CMDA30 NC NC GND_40 GND_136
P31 FBA_D29 FBA_CMD30 W29 E32 NC NC A34 M34 GND_41 GND_137 AD5
MDA30

GND
R32 FBA_D30 F32 NC NC D28 N11 GND_42 GND_138 AD11
MDA31 R30 D33 N12 AD13
MDA32 FBA_D31 NC GND_43 GND_139
AG30 FBA_D32 DQMA[3..0] 26 E31 NC N13 GND_44 GND_140 AD15
MDA33 AG32 P32 DQMA0 C33 B14 N14 AD17
MDA34 FBA_D33 FBA_DQM0 DQMA1 NC NC GND_45 GND_141
AH31 FBA_D34 FBA_DQM1 H34 F29 NC NC B10 N15 GND_46 GND_142 AD21
MDA35 AF31 J30 DQMA2 D30 D9 N16 AD23
MDA36 FBA_D35 FBA_DQM2 DQMA3 NC NC GND_47 GND_143
AF30 FBA_D36 FBA_DQM3 P30 DQMA[7..4] 27 E29 NC NC E14 N17 GND_48 GND_144 AD25
MDA37 AE30 AF32 DQMA4 B29 F26 N18 AD31
MDA38 FBA_D37 FBA_DQM4 DQMA5 NC NC GND_49 GND_145
AC32 FBA_D38 FBA_DQM5 AL32 C31 NC NC D31 N19 GND_50 GND_146 AD34
MDA39 AD30 AL34 DQMA6 C29 A31 N20 AE11
MDA40 FBA_D39 FBA_DQM6 DQMA7 NC NC GND_51 GND_147
AN33 FBA_D40 FBA_DQM7 AF35 B31 NC NC A26 N21 GND_52 GND_148 AE12
MDA41 AL31 C32 N22 AE13
FBA_D41 NC GND_53 GND_149
A

1 1
MDA42 AM33 B32 N23 AE14
MDA43 FBA_D42 NC GND_54 GND_150
AL33 FBA_D43 DQSA#[3..0] 26 B35 NC N24 GND_55 GND_151 AE15
MDA44 AK30 L35 DQSA#0 B34 C14 N25 AE16
MDA45 FBA_D44 FBA_DQS_RN0 DQSA#1 NC NC GND_56 GND_152
AK32 FBA_D45 FBA_DQS_RN1 G35 A29 NC NC A10 P12 GND_57 GND_153 AE17
MDA46 AJ30 H31 DQSA#2 B28 E10 P14 AE18
MDA47 FBA_D46 FBA_DQS_RN2 DQSA#3 NC NC GND_58 GND_154
AH30 FBA_D47 FBA_DQS_RN3 N32 DQSA#[7..4] 27 A28 NC NC D14 P16 GND_59 GND_155 AE19
MDA48 AH33 AD32 DQSA#4 C28 E26 P18 AE20
MDA49 FBA_D48 FBA_DQS_RN4 DQSA#5 NC NC GND_60 GND_156
AH35 FBA_D49 FBA_DQS_RN5 AJ31 C26 NC NC D32 P20 GND_61 GND_157 AE21
MDA50 AH34 AJ35 DQSA#6 D25 A32 P22 AE22
MDA51 FBA_D50 FBA_DQS_RN6 DQSA#7 NC NC GND_62 GND_158
AH32 FBA_D51 FBA_DQS_RN7 AC34 B25 NC NC B26 P24 GND_63 GND_159 AE23
MDA52 AJ33 A25 R2 AE24
MDA53 FBA_D52 NC GND_64 GND_160
AL35 FBA_D53 R5 GND_65 GND_161 AE25
MDA54 AM34 40.2_0402_1% R31 AG2
FBA_D54 DQSA[3..0] 26 GND_66 GND_162
MDA55 AM35 L34 DQSA0 +1.5VSDGPU 2 DIS@ 1 R42 K27 E17 R34 AG5
MDA56 FBA_D55 FBA_DQS_WP0 DQSA1 FBCAL_PD_VDDQ NC GND_67 GND_163
AF33 FBA_D56 FBA_DQS_WP1 H35 NC D17 T11 GND_68 GND_164 AG31
MDA57 AE32 J32 DQSA2 40.2_0402_1%2 DIS@ 1 R41 L27 T13 AG34
MDA58 FBA_D57 FBA_DQS_WP2 DQSA3 FBCAL_PU_GND GND_69 GND_165
AF34 FBA_D58 FBA_DQS_WP3 N31 DQSA[7..4] 27 NC D23 T15 GND_70 GND_166 AK2
MDA59 AE35 AE31 DQSA4 2 DIS@ 1 R40 M27 E23 T17 AK5
MDA60 FBA_D59 FBA_DQS_WP4 DQSA5 FBCAL_TERM_GND NC GND_71 GND_167
AE34 FBA_D60 FBA_DQS_WP5 AJ32 T19 GND_72 GND_168 AK14
MDA61 AE33 AJ34 DQSA6 60.4_0402_1% G19 T21 AK31
MDA62 FBA_D61 FBA_DQS_WP6 DQSA7 NC GND_73 GND_169
AB32 FBA_D62 FBA_DQS_WP7 AC33 T23 GND_74 GND_170 AK34
MDA63 AC35 T25 AL6
FBA_D63 GND_75 GND_171
U11 GND_76 GND_172 AL9
N11M-GE1-B-A2_BGA969 U12 AL12
FB_PLLAVDD GND_77 GND_173
AG27 FB_DLLAVDD U13 GND_78 GND_174 AL15
AF27 FB_PLLAVDD FBA_CLK0 T32 CLKA0 26 U14 GND_79 GND_175 AL18
FBA_CLK0_N T31 CLKA0# 26 U15 GND_80 GND_176 AL21
U16 GND_81 GND_177 AL24
FB_VREF J27 U17 AL27
FB_VREF GND_82 GND_178
+1.5VSDGPU FBA_CLK1 AC31 CLKA1 27 U18 GND_83 GND_179 AL30
2 1 T30 FBA_DEBUG FBA_CLK1_N AC30 CLKA1# 27 U19 GND_84 GND_180 AN2
R35 10K_0402_5% @ U20 AN34
GND_85 GND_181
U21 GND_86 GND_182 AP3
U22 GND_87 GND_183 AP6
U23 GND_88 GND_184 AP9
N11M-GE1-B-A2_BGA969 U24 AP12
FB_PLLAVDD GND_89 GND_185
2 1 +1.05VSDGPU U25 GND_90 GND_186 AP15
L2 DIS@ V2 AP18
BLM18PG181SN1D_0603 +1.5VSDGPU GND_91 GND_187
1 1 1 1 V5 AP21
0.1U_0402_16V4Z

GND_92 GND_188
C73

C72

C147

V9 AP24
1U_0402_6.3V6K

4.7U_0603_6.3V6M

C138 GND_93 GND_189

V12 AP27
0.01U_0402_25V7K

GND_94 GND_190
1

DIS@ V14 AP30

2 2 2 2 GND_95 GND_191
DIS@

DIS@

DIS@

V16 GND_96 GND_192 AP33

R47 @ Rt
1K_0402_1%
2

FB_VREF
N11M-GE1-B-A2_BGA969
1

1
Compal Electronics, Inc.
0.1U_0402_16V4Z

R45 @ Rb C74 Security Classification Compal Secret Data

1K_0402_1% @ 2009/5/12 2009/12/31 Title
2 Issued Date Deciphered Date N11M VRAM 4/6
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NALG0 M/B LA-5681P Schematic 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 23, 2009 Sheet 25 of 60
A
 5 4 3 2 1

VRAM gDDR3 chips (256MB & 512MB)

32Mx16 gDDR2 *4==>256MB Address 0..31 32..63
CMD0 A4
64Mx16 gDDR3 *4==>512MB
CMD1 RAS# RAS#
D +1.5VSDGPU +1.5VSDGPU CMD2 A5 D
DQSA[7..0]
25,27 DQSA[7..0]
CMD3 BA1 BA1

1
DQSA#[7..0] U2 X76@
25,27 DQSA#[7..0]
R16 CMD4 A2
DQMA[7..0] R401 DIS@ 1K_0402_1% DIS@ MEM_VREF1 M8 E3 MDA3
25,27 DQMA[7..0] VREFCA DQL0
1K_0402_1% H1 F7 MDA7 CMD5 A4
MDA[63..0] VREFDQ DQL1 MDA0
25,27 MDA[63..0] F2

2
CMDA19 DQL2 MDA5
N3 A0 DQL3 F8 CMD6 A3
CMDA[30..0] MEM_VREF0 MEM_VREF1 CMDA25 P7 H3 MDA2
25,27 CMDA[30..0] A1 DQL4
1 1 CMDA22 P3 H8 MDA6 CMD7 CKE
A2 DQL5

1
0.1U_0402_10V6K~D

0.1U_0402_10V6K~D
DIS@ DIS@ CMDA24 N2 G2 MDA1
R397 C407 R9 C24 CMDA0 A3 DQL6 MDA4
P8 A4 DQL7 H7 CMD8 CS#
U32 X76@ 1K_0402_1% DIS@ 1K_0402_1% DIS@ CMDA2 P2
2 2 CMDA21 A5
R8 A6 CMD9 A11 A11
MEM_VREF0 M8 E3 MDA27 CMDA16 R2 D7 MDA20

2
VREFCA DQL0 MDA26 CMDA23 A7 DQU0 MDA17
H1 VREFDQ DQL1 F7 T8 A8 DQU1 C3 CMD10 CAS# CAS#
F2 MDA29 CMDA20 R3 C8 MDA23
CMDA19 DQL2 MDA25 CMDA17 A9 DQU2 MDA19
N3 A0 DQL3 F8 L7 A10/AP DQU3 C2 CMD11 WE# WE#
CMDA25 P7 H3 MDA30 CMDA9 R7 A7 MDA22
CMDA22 A1 DQL4 MDA28 CMDA14 A11 DQU4 MDA18
P3 A2 DQL5 H8 N7 A12 DQU5 A2 CMD12 BA0 BA0
CMDA24 N2 G2 MDA31 CMDA26 T3 B8 MDA21
CMDA0 A3 DQL6 MDA24 A13 DQU6 MDA16
P8 A4 DQL7 H7 T7 A14 DQU7 A3 CMD13 A5
CMDA2 P2 M7
CMDA21 A5 A15/BA3 +1.5VSDGPU
R8 A6 CMD14 A12 A12
CMDA16 R2 D7 MDA15
CMDA23 A7 DQU0 MDA9 CMDA12
T8 A8 DQU1 C3 M2 BA0 VDD B2 CMD15 RST RST
CMDA20 R3 C8 MDA13 CMDA3 N8 D9
CMDA17 A9 DQU2 MDA11 CMDA27 BA1 VDD
L7 A10/AP DQU3 C2 M3 BA2 VDD G7 CMD16 A7 A7
C CMDA9 R7 A7 MDA12 K2 C
CMDA14 A11 DQU4 MDA10 VDD
N7 A12 DQU5 A2 VDD K8 CMD17 A10 A10
CMDA26 T3 B8 MDA14 N1
A13 DQU6 MDA8 CLKA0 VDD
T7 A14 DQU7 A3 J7 CK VDD N9 CMD18 CKE
M7 CLKA0# K7 R1
A15/BA3 +1.5VSDGPU CMDA18 CK VDD
K9 CKE/CKE0 VDD R9
+1.5VSDGPU
CMD19 A0 A0
CMDA12 M2 B2 CMD20 A9 A9
CMDA3 BA0 VDD CMDA30
N8 BA1 VDD D9 K1 ODT/ODT0 VDDQ A1
CMDA27 M3 G7 CMDA29 L2 A8 CMD21 A6 A6
BA2 VDD CMDA1 CS/CS0 VDDQ
VDD K2 J3 RAS VDDQ C1
K8 CMDA10 K3 C9 CMD22 A2
VDD CLKA0 CMDA11 CAS VDDQ
VDD N1 25 CLKA0 L3 WE VDDQ D2
CLKA0 J7 N9 E9 CMD23 A8 A8
CLKA0# CK VDD VDDQ
CMDA18
K7 CK VDD R1
DQSA0
310mAVDDQ F1
K9 CKE/CKE0 VDD R9
+1.5VSDGPU
F3 DQSL VDDQ H2 CMD24 A3
DQSA2 C7 H9
R399 DQSU VDDQ
CMD25 A1 A1
CMDA30 K1 A1 DIS@ 240_0402_1%
CMDA29 ODT/ODT0 VDDQ DQMA0
L2 CS/CS0 VDDQ A8 E7 DML VSS A9 CMD26 A13 A13
CMDA1 J3 C1 DQMA2 D3 B3
CMDA10 RAS VDDQ DMU VSS
K3 CAS VDDQ C9 VSS E1 CMD27 BA2 BA2
CMDA11 L3 D2 G8
WE VDDQ CLKA0# DQSA#0 VSS
310mAVDDQ E9 25 CLKA0# G3 DQSL VSS J2 CMD28 ODT
F1 DQSA#2 B7 J8
DQSA3 VDDQ DQSU VSS
F3 DQSL VDDQ H2 VSS M1 CMD29 CS#
DQSA1 C7 H9 M9
DQSU VDDQ VSS
VSS P1 CMD30 ODT
CMDA15 T2 P9
B DQMA3 RESET VSS B
DQMA1
E7 DML VSS A9
ZQ1 VSS T1 LOW HIGH
D3 DMU VSS B3 L8 ZQ/ZQ0 VSS T9
VSS E1
G8 CMDA7 R18 1 2 10K_0402_5%
VSS

1 243_0402_1%
DQSA#3 G3 J2 CMDA18 R27 1 2 10K_0402_5% J1 B1
DQSL VSS NC/ODT1 VSSQ

R12
DQSA#1 B7 J8 CMDA28 R25 1 DIS@ 2 10K_0402_5% L1 B9
DQSU VSS CMDA30 R19 10K_0402_5% NC/CS1 VSSQ
VSS M1 1 DIS@ 2 J9 NC/CE1 VSSQ D1
M9 CMDA15 R21 1 DIS@ 2 10K_0402_5% DIS@ L9 D8
VSS NCZQ1 VSSQ
P1 DIS@ E2

2
CMDA15 VSS VSSQ
T2 RESET VSS P9 DIS@ VSSQ E8
VSS T1 VSSQ F9
ZQ0 L8 T9 G1
ZQ/ZQ0 VSS VSSQ
VSSQ G9
1243_0402_1%

J1 B1 96-BALL
NC/ODT1 VSSQ
R13

L1 B9 SDRAM DDR3
NC/CS1 VSSQ K4B1G1646E-HC12_FBGA96
J9 NC/CE1 VSSQ D1
DIS@ L9 D8
NCZQ1 VSSQ
E2
2

VSSQ
VSSQ E8
F9 +1.5VSDGPU
VSSQ
VSSQ G1
VSSQ G9
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
96-BALL 1 1 1 1 1 1 1 1 1
+1.5VSDGPU SDRAM DDR3
K4B1G1646E-HC12_FBGA96 C18 C19 C35 C20 C17 C15 C399 C398 C400
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2 2 2 2 2 2 2 2 2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

A A
1000P_0402_50V7K

1 1 1 1 1 1 1 1 1 1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C26 C21 C22 C23 C25 C408 C409 C404 C405 C406
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2 2 2 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11M gDDR3 5/6
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 26 of 60
5 4 3 2 1
 5 4 3 2 1

VRAM DDR3 chips (256MB & 512MB)

Address 0..31 32..63
32Mx16 DDR3 *4==>256MB +1.5VSDGPU +1.5VSDGPU CMD0 A4
64Mx16 DDR3 *4==>512MB CMD1 RAS# RAS#

1
U31 X76@
R15 R402 CMD2 A5
D DQMA[7..0] 1K_0402_1% DIS@ 1K_0402_1% DIS@ MEM_VREF3 M8 E3 MDA40 D
25,26 DQMA[7..0] VREFCA DQL0
H1 F7 MDA41 CMD3 BA1 BA1
CMDA[30..0] VREFDQ DQL1 MDA43
25,26 CMDA[30..0] F2

2
CMDA19 DQL2 MDA44
DQSA#[7..0]
N3 A0 DQL3 F8 CMD4 A2
MEM_VREF2 MEM_VREF3 CMDA25 P7 H3 MDA45
25,26 DQSA#[7..0] A1 DQL4
1 1 CMDA4 P3 H8 MDA47 CMD5 A4
A2 DQL5

1
0.1U_0402_10V6K~D

0.1U_0402_10V6K~D
DQSA[7..0] DIS@ DIS@ CMDA6 N2 G2 MDA42
25,26 DQSA[7..0] A3 DQL6
R10 C30 R398 C412 CMDA5 P8 H7 MDA46 CMD6 A3
MDA[63..0] 1K_0402_1% DIS@ 1K_0402_1% DIS@ CMDA13 A4 DQL7
25,26 MDA[63..0] P2 A5
2 2 CMDA21 R8 A6 CMD7 CKE
U5 X76@ CMDA16 R2 D7 MDA51

2
CMDA23 A7 DQU0 MDA53
T8 A8 DQU1 C3 CMD8 CS#
MEM_VREF2 M8 E3 MDA57 CMDA20 R3 C8 MDA48
VREFCA DQL0 MDA63 CMDA17 A9 DQU2 MDA54
H1 VREFDQ DQL1 F7 L7 A10/AP DQU3 C2 CMD9 A11 A11
F2 MDA61 CMDA9 R7 A7 MDA49
CMDA19 DQL2 MDA58 CMDA14 A11 DQU4 MDA55
N3 A0 DQL3 F8 N7 A12 DQU5 A2 CMD10 CAS# CAS#
CMDA25 P7 H3 MDA56 CMDA26 T3 B8 MDA50
CMDA4 A1 DQL4 MDA60 A13 DQU6 MDA52
P3 A2 DQL5 H8 T7 A14 DQU7 A3 CMD11 WE# WE#
CMDA6 N2 G2 MDA62 M7
CMDA5 A3 DQL6 MDA59 A15/BA3 +1.5VSDGPU
P8 A4 DQL7 H7 CMD12 BA0 BA0
CMDA13 P2
CMDA21 A5 CMDA12
R8 A6 M2 BA0 VDD B2 CMD13 A5
CMDA16 R2 D7 MDA35 CMDA3 N8 D9
CMDA23 A7 DQU0 MDA39 CMDA27 BA1 VDD
T8 A8 DQU1 C3 M3 BA2 VDD G7 CMD14 A12 A12
CMDA20 R3 C8 MDA32 K2
CMDA17 A9 DQU2 MDA36 VDD
L7 A10/AP DQU3 C2 VDD K8 CMD15 RST RST
CMDA9 R7 A7 MDA33 N1
CMDA14 A11 DQU4 MDA38 CLKA1 VDD
N7 A12 DQU5 A2 J7 CK VDD N9 CMD16 A7 A7
CMDA26 T3 B8 MDA34 CLKA1# K7 R1
A13 DQU6 MDA37 CMDA7 CK VDD
C T7 A14 DQU7 A3 K9 CKE/CKE0 VDD R9
+1.5VSDGPU
CMD17 A10 A10 C
M7 A15/BA3 +1.5VSDGPU CMD18 CKE
CMDA28 K1 A1
CMDA12 CMDA8 ODT/ODT0 VDDQ
M2 BA0 VDD B2 L2 CS/CS0 VDDQ A8 CMD19 A0 A0
CMDA3 N8 D9 CMDA1 J3 C1
CMDA27 BA1 VDD CMDA10 RAS VDDQ
M3 BA2 VDD G7 K3 CAS VDDQ C9 CMD20 A9 A9
K2 CMDA11 L3 D2
VDD WE VDDQ
VDD K8 310mAVDDQ E9 CMD21 A6 A6
VDD N1 VDDQ F1
CLKA1 J7 N9 DQSA5 F3 H2 CMD22 A2
CLKA1# CK VDD CLKA1 DQSA6 DQSL VDDQ
K7 CK VDD R1 25 CLKA1 C7 DQSU VDDQ H9
CMDA7 K9 R9 CMD23 A8 A8
CKE/CKE0 VDD +1.5VSDGPU
DQMA5 E7 A9 CMD24 A3
CMDA28 DQMA6 DML VSS
K1 ODT/ODT0 VDDQ A1 D3 DMU VSS B3
CMDA8 L2 A8 E1 CMD25 A1 A1
CMDA1 CS/CS0 VDDQ VSS
J3 RAS VDDQ C1 VSS G8
CMDA10 K3 C9 R14 DQSA#5 G3 J2 CMD26 A13 A13
CMDA11 CAS VDDQ DIS@ 240_0402_1% DQSA#6 DQSL VSS
L3 WE VDDQ D2 B7 DQSU VSS J8
310mAVDDQ E9 VSS M1 CMD27 BA2 BA2
VDDQ F1 VSS M9
DQSA7 F3 H2 P1 CMD28 ODT
DQSA4 DQSL VDDQ CMDA15 VSS
C7 DQSU VDDQ H9 T2 RESET VSS P9
VSS T1 CMD29 CS#
ZQ3 L8 T9
DQMA7 CLKA1# ZQ/ZQ0 VSS
E7 DML VSS A9 25 CLKA1# CMD30 ODT
DQMA4 D3 B3
DMU VSS
VSS E1 J1 NC/ODT1 VSSQ B1 LOW HIGH

1
B B

243_0402_1%
VSS G8 L1 NC/CS1 VSSQ B9

R400
DQSA#7 G3 J2 J9 D1
DQSA#4 DQSL VSS NC/CE1 VSSQ
B7 DQSU VSS J8 L9 NCZQ1 VSSQ D8
VSS M1 VSSQ E2
M9 DIS@ E8

2
VSS VSSQ
VSS P1 VSSQ F9
CMDA15 T2 P9 G1
RESET VSS VSSQ
VSS T1 VSSQ G9
ZQ2 L8 T9
ZQ/ZQ0 VSS 96-BALL
SDRAM DDR3
J1 B1 K4B1G1646E-HC12_FBGA96
NC/ODT1 VSSQ
1 243_0402_1%

L1 NC/CS1 VSSQ B9
R17

J9 NC/CE1 VSSQ D1
L9 NCZQ1 VSSQ D8
DIS@ E2
VSSQ +1.5VSDGPU
E8
2

VSSQ
VSSQ F9
VSSQ G1
G9
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
VSSQ
1 1 1 1 1 1 1 1 1
96-BALL
SDRAM DDR3 C417 C403 C402 C39 C401 C36 C397 C416 C16
+1.5VSDGPU K4B1G1646E-HC12_FBGA96 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2 2 2 2 2 2 2 2 2
C32

1U_0402_6.3V6K

C31

1U_0402_6.3V6K

C411

1U_0402_6.3V6K

C29

1U_0402_6.3V6K

C28

0.1U_0402_16V7K

C27

0.1U_0402_16V7K

C414

0.1U_0402_16V7K

C413

0.1U_0402_16V7K

C410

0.1U_0402_16V7K

C415

0.1U_0402_16V7K

A 1 1 1 1 1 1 1 1 1 1 A

2 2 2 2 2 2 2 2 2 2

DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11M gDDR3 6/6
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 27 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS C496 SG@

0.1U_0402_16V4Z
+LCDVDD LCD POWER CIRCUIT 1 2
+3VALW +3VS +3VS C494 SG@ R504

1
W=60mils 0.1U_0402_16V4Z 0_0402_5% U37

1
1 2 DGPU_SELECT# 1 @ 2 PWMSEL_1# NC7SZ14P5X_NL_SC70-5

NC
R387 1 SG@ 2 2 4 IGPU_PWM_SELECT#
17 DGPU_PWMSEL# A Y

1
1 DGPU_SELECT# 1 @ 2 R503 0_0402_5%
17,29 DGPU_SELECT#

G
5

1
300_0603_5% <BOM Structure> R393 C7 R490 0_0402_5% U36 SG@
100K_0402_5%

NC
2

3
4.7U_0805_10V4Z 1 SG@ 2 DGPU_EDIDSEL_R#2 4 IGPU_EDIDSEL#
2 18 DGPU_EDIDSEL# A Y
R498 0_0402_5%

G
1 R390

3
D 1K_0402_5%
S
NC7SZ14P5X_NL_SC70-5

3
D
G D
Q1 2 2 1 2 Q2 SG@
2N7002_SOT23 G AO3413_SOT23-3
29 DGPU_EDIDSEL_R#
S 1
D
3

1
C381 +LCDVDD
W=60mils

1
D 0.047U_0402_16V7K +3VS
2 Q4 2
16 PCH_ENVDD PWMSEL_1#
G 2N7002_SOT23 1 1 +5VS

1
S UMA@ C1 C4
3
1

R513 R505 +5VS C495 SG@

1
4.7U_0805_10V4Z 0.1U_0402_16V4Z U44 0_0402_5% 2.2K_0402_5% 0.1U_0402_16V4Z
R391 2 2 1 @ 2 1 2
@

OE#
P
PWM_R INVTPWM 22 VGA_PNL_PWM U15
100K_0402_5% 2 4 R521

2
A Y SG@ PWM_R 2
37 INVT_PWM 1 2 8
2

1A VCC

G
74AHCT1G125GW_SOT353-5 @ 0_0402_5% DPST_PWM_1 5 3 INVTPWM
PWMSEL_1# 2A 1B
16 PWMSEL_1# 1 6

3
1OE# 2B
1
D IGPU_PWM_SELECT#
16 IGPU_PWM_SELECT# 7 2OE# GND 4

1
2 Q3
22 ENVDD
G 2N7002_SOT23 SN74CBTD3306CPWR_TSSOP8 R516
1

S DIS@ +5VS IGPU_PWM_SELECT# SG@

3

10K_0402_5%<BOM Structure>
R1

2
5

1
100K_0402_5% DIS@ U45

OE#
P
2

DPST_PWM_1 2 4 INVTPWM
A Y

G
@ VGA_PNL_PWM 0_0402_5% 2 @ 1 R533 INVTPWM
74AHCT1G125GW_SOT353-5

3
INVT_PWM 0_0402_5% 2 DIS only@
1 R523

LED PANEL Conn. Reserved for DIS Only

C +3VS C
JLVDS1
42 GND GND 41 R500 1 2 4.7K_0402_5% PCH_LCD_CLK +3VS
40 40 DAC_BRIG R489 1 2 4.7K_0402_5% PCH_LCD_DATA
+INVPWR_B+ 39 39 INVTPWM DAC_BRIG 37
U38
38 38 37 37

1
36 36 DISPOFF# 2009/04/14 UPDATE NC7SZ14P5X_NL_SC70-5 Reserved for UMA Only
+3VS
I2CC_SCL 35 35 UMA@
34 34 33 33

NC
+LCDVDD
I2CC_SDA 32 32 DPST_PWM_1 1 UMA only@ INVTPWM
31 31 16 DPST_PWM 2 4 2
A Y R542 0_0402_5%
30 30 29 29 W=60mils

G
1 @ 2 28 28
R370 0_0402_5% 27 27 TXOUT0- +3VS
26 26 25 25

3
24 24 TXOUT0+
23 23
LED PANEL PIN1&34 SHORT 22 22 21 21

2
20 20 TXOUT1- IGPU_EDIDSEL# @
19 19
1 2
18 18 TXOUT1+ R99 R543 0_0402_5%
17 17
16 16
15 15 TXOUT2+
4.7K_0402_5%
14 14
13 13

2
G
12 12 TXOUT2-
11 11

1
10 10
9 9 TXCLK- VGA_LCD_DAT I2CC_SDA +3VS
8 8 7 7 22 VGA_LCD_DAT 3 1
R369 0_0402_5% TXCLK+

D
6 5
6 5
1 2 USB20_CMOS_N3 4 4
17 USB20_N3 3 3

1
1 2 USB20_CMOS_P3 2 Q11
1 1
17 USB20_P3
R368 0_0402_5% 2
ACES_88242-4001
+3VS
2N7002_SOT23
SG@
+3VS
SG For LVDS SEL=LOW, B1
SEL=High, B2
R82
0_0603_5%
SG@

2
CONN@

2
+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
IGPU_EDIDSEL# R102 SG@ U12
+INVPWR_B+ 4.7K_0402_5% 4 +3VS_SWITCH
VCC
10 1 1 1
VCC

2
G
L20 2 1 VGA_TXOUT0-48 18
B+ 23 VGA_TXOUT0-

1
0B1 VCC
1

W=40mils FBMA-L11-201209-221LMA30T_0805 VGA_TXOUT0+47 27

B 23 VGA_TXOUT0+ 1B1 VCC B
R374 22 VGA_LCD_CLK VGA_LCD_CLK 3 1 I2CC_SCL VGA_TXOUT1-43 38 SG@SG@SG@
23 VGA_TXOUT1- 2B1 VCC 2 2 2
L19 2 D1 @ VGA_TXOUT1+42

D
1 23 VGA_TXOUT1+ 3B1 VCC 50
FBMA-L11-201209-221LMA30T_0805 CH751H-40PT_SOD323-2 4.7K_0402_5% VGA_TXOUT2-37 56
23 VGA_TXOUT2- VGA_TXOUT2+36 4B1 VCC
1 1 @ Q19 C182 C188 C177
23 VGA_TXOUT2+
2

C370 C369 BKOFF# DISPOFF# 2N7002_SOT23 VGA_TXCLK- 32 5B1 TXOUT0-

37 BKOFF# 1 2 23 VGA_TXCLK- 2
680P_0402_50V7K 68P_0402_50V8J SG@ VGA_TXCLK+ 31 6B1 A0 TXOUT0+
23 VGA_TXCLK+ 3
R2 VGA_LCD_CLK 7B1 A1 TXOUT1-
1 2 0_0402_5% R486 1 @ 2 0_0402_5% 22 7
2 2 R5 VGA_LCD_DAT 8B1 A2 TXOUT1+
1 2 10K_0402_5% R485 1 @ 2 0_0402_5% 23 8
9B1 A3 TXOUT2-
11
A4 TXOUT2+
A5 12
+LCDVDD 14 TXCLK-
+3VS A6 TXCLK+
15
PCH_TXOUT0-46 A7 I2CC_SCL
16 PCH_TXOUT0- 0B2 A8 19
PCH_TXOUT0+45 20 I2CC_SDA
16 PCH_TXOUT0+ 1B2 A9
INVTPWM 1 2 1 1 1 PCH_TXOUT1-41
16 PCH_TXOUT1- PCH_TXOUT1+40 2B2 DGPU_SELECT#
C374 220P_0402_50V7K C2 C3 C377 17
16 PCH_TXOUT1+ 3B2 SEL
DISPOFF# 1 2 DGPU_EDIDSEL_R# PCH_TXOUT2-35
16 PCH_TXOUT2- PCH_TXOUT2+34 4B2
C373 220P_0402_50V7K 10U_0805_10V4Z 0.1U_0402_16V4Z 1
16 PCH_TXOUT2+ 5B2 GND
2

2 2 2
G

0.1U_0402_16V4Z PCH_TXCLK- 30 6
16 PCH_TXCLK- PCH_TXCLK+ 29 6B2 GND
16 PCH_TXCLK+ 9
PCH_LCD_DATA I2CC_SDA PCH_LCD_CLK R159 1 @ 7B2 GND
16 PCH_LCD_DATA 3 1 2 0_0402_5% 25 13
PCH_LCD_DATA R160 1 @ 8B2 GND
2 0_0402_5% 26
S

9B2 GND 16
21
Q12 GND
GND 24
2N7002_SOT23 28
UMA ONLY DIS ONLY DGPU_EDIDSEL_R#
SG@ 52
5
NC
NC
GND
GND
GND
33
39
54 44
NC GND
2
G

PCH_TXOUT0+ 4 10_0404_4P2R_5% TXOUT0+ VGA_TXOUT0+ 2 3 DIS only@ TXOUT0+ 51 49

PCH_TXOUT0- RP13 3 TXOUT0- VGA_TXOUT0- TXOUT0- NC GND
2 1 4 53
UMA only@ RP1 0_0404_4P2R_5% PCH_LCD_CLK I2CC_SCL GND
16 PCH_LCD_CLK 3 1 57 55
Thermal_GND GND
PCH_TXOUT1+ 1 0_0404_4P2R_5%
TXOUT1+ VGA_TXOUT1+ DIS only@ TXOUT1+
S

4 2 3
A PCH_TXOUT1- RP14 3 TXOUT1- VGA_TXOUT1- TXOUT1- TS3DV520ERHUR_WQFN56_11X5 A
2 1 4
UMA only@ RP2 0_0404_4P2R_5% Q20
PCH_TXOUT2+ 4 1 0_0404_4P2R_5%
TXOUT2+ VGA_TXOUT2+ 2 3 DIS only@ TXOUT2+ 2N7002_SOT23
PCH_TXOUT2- RP15 3 2 TXOUT2- VGA_TXOUT2- 1 4 TXOUT2- SG@
UMA only@ RP3 0_0404_4P2R_5%
PCH_TXCLK+ 4 1 0_0404_4P2R_5%TXCLK+ VGA_TXCLK+ 2 3 DIS only@ TXCLK+
PCH_TXCLK- RP16 3 2 TXCLK- VGA_TXCLK- 1 4 TXCLK-
UMA only@ RP4 0_0404_4P2R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

PCH_LCD_CLK R501 1 UMA only@

2 0_0402_5% I2CC_SCL VGA_LCD_CLK R502 1 DIS only@
2 0_0402_5% I2CC_SCL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
PCH_LCD_DATA R483 1 UMA only@
2 0_0402_5% I2CC_SDA VGA_LCD_DAT R484 1 DIS only@
2 0_0402_5% I2CC_SDA Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 28 of 60
5 4 3 2 1
 A B C D E

CRT Connector D8 D7 D6
W=40mils
+5VS +R_CRT_VCC +CRT_VCC
DAN217_SC59 DAN217_SC59 DAN217_SC59
D20 F1 W=40mils

1
2 1 1 2

RB491D_SC59-3 1.1A_6VDC_FUSE
Change to 0 ohm for Discrete 1
C49

3
0.1U_0402_16V4Z
2
1 +3VS 1

CRT_R 1 2 CRT_R_1 1 2 CRT_R_2 JCRT1

L34 FCM2012CF-800T06_2P L33 FCM2012CF-800T06_2P 6 RGND
11
CRT_G CRT_G_1 CRT_G_2 ID0
1 2 1 2 1 Red
L32 FCM2012CF-800T06_2P L31 FCM2012CF-800T06_2P 7 GGND
12
CRT_B CRT_B_1 CRT_B_2 SDA
1 2 1 2 2 Green
L30 FCM2012CF-800T06_2P L29 FCM2012CF-800T06_2P 8
BGND
13 Hsync

1
1 1 1 1 1 1 1 1 1 3
R450 R445 R442 C431 C429 C424 C432 C430 C425 Blue
9
C79 C61 C52 +5V
14
150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J Vsync
4 res
2 2 2 2 2 2 2 2 2 10

2
10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J SGND
15 SCL
22P_0402_50V8J 1 5
GND
150_0402_1% 10P_0402_50V8J 22P_0402_50V8J Change to 12pf for Discrete C47
16
100P_0402_50V8J GND
17 GND
Change to 15pf for Discrete 2

1 2 CRT_HSYNC_2 SUYIN_070546FR015S263ZR
+CRT_VCC L28 MBC1608121YZF_0603 DSUB_12
CONN@
C44 1 2 0.1U_0402_16V4Z R26 2 1 10K_0402_5% 1 2 CRT_VSYNC_2 1
L27 MBC1608121YZF_0603 1 1 CRT_DET# 18

1
U7 C423 C422 DSUB_15
2 10P_0402_50V8J 10P_0402_50V8J C59 2 2

OE#
P

2
CRT_HSYNC 2 4 CRT_HSYNC_1 2 2 68P_0402_50V8J 1
A Y R24

G
C45 100K_0402_5%
74AHCT1G125GW_SOT353-5 68P_0402_50V8J

3
2

1
+CRT_VCC

C48 <BOM
1 Structure>
2 0.1U_0402_16V4Z
+CRT_VCC

1
U6

OE#
P
CRT_VSYNC 2 4 CRT_VSYNC_1
A Y

G
D22 D21
74AHCT1G125GW_SOT353-5 DIS@ DIS@

3
+3VS DAN217_SC59 DAN217_SC59

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1
C42 C40 C43 C46

SG@ SG@ SG@ SG@

3
2 2 2 2

+CRT_VCC

U4 SG@

4 1 CRT_R
3 +3VS VDD A0 +CRT_VCC 3
16 2 CRT_G
VDD A1 CRT_B
23 VDD A2 5
29 6 CRT_HSYNC
VDD A3 CRT_VSYNC
32 VDD A4 7

27 8 +3VS
22 VGA_CRT_R 0B1 SEL1 DGPU_SELECT# 17,28

1
22 VGA_CRT_G 25
1B1 R34 R33
22 VGA_CRT_B 22
2B1 DSUB_12_R R22 DSUB_12
22 VGA_CRT_HSYNC 20 9 2 @ 1 0_0402_5% 2.2K_0402_5% 2.2K_0402_5%
3B1 A5 DSUB_15_R R23 DSUB_15
22 VGA_CRT_VSYNC 18 4B1 A6 10 2 @ 1 0_0402_5%
12 Q6
22 VGA_DDC_DATA

2
5B1

2
G
14 30 VGA_DDC_DATA R28 2 DIS only@
1 0_0402_5% 2N7002_SOT23
22 VGA_DDC_CLK 6B1 SEL2 DGPU_EDIDSEL_R# 28
PCH_CRT_DATA R29 2 UMA only@
1 0_0402_5% DSUB_12_R 3 1 DSUB_12

D
pull-up 2.2k on PCH side 16 PCH_CRT_R 26 0B2
16 PCH_CRT_G 24
1B2

2
G
pull-up 2k on GPU SIDE 16 PCH_CRT_B 21
2B2 GND
3
19 11 Q7
16 PCH_CRT_HSYNC 3B2 GND VGA_DDC_CLK R30 DSUB_15_R DSUB_15
16 PCH_CRT_VSYNC 17 28 2 DIS only@
1 0_0402_5% 3 1 2N7002_SOT23
4B2 GND

D
16 PCH_CRT_DATA 13 31
5B2 GND PCH_CRT_CLK R31
16 PCH_CRT_CLK 15 33 2 UMA only@
1 0_0402_5%
6B2 GPAD

PI3V712-AZLEX_TQFN32_6X3~D

Reserved for UMA only Reserved for DIS only

PCH_CRT_R R411 2 UMA only@

1 0_0402_5% CRT_R VGA_CRT_R R410 2 DIS only@
1 0_0402_5% CRT_R
PCH_CRT_G R417 2 UMA only@
1 0_0402_5% CRT_G VGA_CRT_G R414 2 DIS only@
1 0_0402_5% CRT_G
L B1 DIS PCH_CRT_B R421 2 UMA only@
1 0_0402_5% CRT_B VGA_CRT_B R418 2 DIS only@
1 0_0402_5% CRT_B
4 PCH_CRT_HSYNC R427 UMA only@ CRT_HSYNC VGA_CRT_HSYNC CRT_HSYNC 4
2 1 0_0402_5% R424 2 DIS only@
1 0_0402_5%
PCH_CRT_VSYNC R434 2 UMA only@
1 0_0402_5% CRT_VSYNC VGA_CRT_VSYNC R430 2 DIS only@
1 0_0402_5% CRT_VSYNC
H B2 UMA

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 29 of 60
A B C D E
 5 4 3 2 1

+3VS
+3VS
+HDMI_5V_OUT JHDMI1

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z HDMI_HPD 19
R189 1 @ HP_DET
2 0_0603_5% R263 +HDMI_5V_OUT 18 +5V
1 1 1 1 1 1 1 10K_0402_5% 17 DDC/CEC_GND
C621 C622 C623 C619 C609 C612 C610 W=40mils UMA only@ HDMI_SDATA 16
UMA only@ UMA only@ UMA only@ UMA only@ UMA only@ UMA only@ UMA only@ D13 F2 HDMI_SCLK SDA
15

2
+HDMI_5V HDMI_HPD# SCL
+5VS 2 1 1 2 18 HDMI_HPD# 14 Reserved
2
0.1U_0402_16V4Z 2 2 2 2 2 2
1 D 13 CEC

1
RB491D_SC59-3 1.1A_6VDC_FUSE HDMI_R_CK- 12 20
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C592 Q26 HDMI_HPD CK- GND
2 11 CK_shield GND 21
0.1U_0402_16V4Z 2N7002_SOT23 G HDMI_R_CK+ 10 22
CK+ GND

1
2 S HDMI_R_D0-
D 1 9 23 D

3
C268 R254 D0- GND
8 D0_shield
HDMI_R_D0+ 7
U22 0.1U_0402_16V4Z 100K_0402_5% HDMI_R_D1- D0+
6 D1-
2
5

2
HDMI_R_D1+ D1_shield
4 D1+
+3VS +3VS 25 HDMI_HPD# +HDMI_5V_OUT HDMI_R_D2- 3
OE# D2-
2 D2_shield
2 HDMI_R_D2+ 1
VCC3V HDMI_SCLK R657 1 D2+
11 VCC3V SCL_SINK 28 2 2.2K_0402_5%
R271 15 TYCO_1939864-1
VCC3V HDMI_SDATA R655 1
21 29 2 2.2K_0402_5% CONN@

2.2K_0402_5%
VCC3V SDA_SINK

2
R265 26

2.2K_0402_5%
VCC3V
33

UMA only@

UMA only@
VCC3V HDMI_HPD
40 VCC3V HPD_SINK 30
46 VCC3V
32 R282 1 UMA only@
2 0_0402_5% +3VS HDMI_CLK- R637 1 2 0_0402_5% HDMI_R_CK-

1
DDC_EN
R276 1 @ 2 2.2K_0402_5% +3VS 1 2
R262 1 @ 1 2
2 2.2K_0402_5% HDMI_CG0 3
CG_0 EQ_0 34 R283 1 @ 2 2.2K_0402_5% L40
R274 1 @ 2 2.2K_0402_5% HDMI_CG1 4 35 EQ_S1 R277 1 @ 2 2.2K_0402_5% W CM-2012-900T_0805
CG_1 EQ_1 R284 @ 2.2K_0402_5% @
1 2 4 4 3 3

UMA only@ OC_S2 6 HDMI_CLK+ R640 1 2 0_0402_5% HDMI_R_CK+

R656 3.6K_0402_5% REXT
LS_HDMI_DET 7
R260 1 UMA only@ HPD#
+3VS 2 2.2K_0402_5%
16 SDVO_SDATA SDVO_SDATA 8 HDMI_TX0- R631 1 2 0_0402_5% HDMI_R_D0-
R258 1 UMA only@ SDA
2 2.2K_0402_5%
C
16 SDVO_SCLK SDVO_SCLK 9 1 2 C
SCL L39 1 2
W CM-2012-900T_0805
+3VS R253 1 @ 2 HDMI_CG3 10 @ 4 3
2.2K_0402_5% CG_2 4 3
2

HDMI_TX0+ R633 1 2 0_0402_5% HDMI_R_D0+

R248 HDMI_TX2+ 13 48
OUT_D4+ IN_D4+ PCH_TMDS_D2 16
0_0402_5%HDMI_TX2- 14 OUT_D4- IN_D4- 47 PCH_TMDS_D2# 16
HDMI_TX1- R650 1 2 0_0402_5% HDMI_R_D1-
UMA only@ HDMI_TX1+ 16 45 PCH_TMDS_D1 16
1

HDMI_TX1- OUT_D3+ IN_D3+

17 OUT_D3- IN_D3- 44 PCH_TMDS_D1# 16 1 1 2 2
L42
HDMI_CLK+ 19 42 W CM-2012-900T_0805
OUT_D2+ IN_D2+ PCH_TMDS_CK 16
HDMI_CLK- 20 41 @ 4 3
OUT_D2- IN_D2- PCH_TMDS_CK# 16 4 3
+3VS HDMI_TX0+ 22 39 HDMI_TX1+ R651 1 2 0_0402_5% HDMI_R_D1+
OUT_D1+ IN_D1+ PCH_TMDS_D0 16
HDMI_TX0- 23 38
OUT_D1- IN_D1- PCH_TMDS_D0# 16
1

R280 HDMI_TX2- R652 1 2 0_0402_5% HDMI_R_D2-

20K_0402_5%
@ 1 1 2
GND L44 1 2
5
2

GND
1 UMA only@
2 12 GND GND 49 W CM-2012-900T_0805
R279 PCH_DPB_HPD 16 18 @ 4 3
0_0402_5% GND 4 3
D 24 GND
1

27 HDMI_TX2+ R653 1 2 0_0402_5% HDMI_R_D2+

LS_HDMI_DET Q27 GND
2 31 GND
1

G 36
@ GND
S
2N7002_SOT23

37
3

B R278 GND B
43 GND
20K_0402_5%
@ CH7318C-BF PN: SA00001U920
2

ASM1442T_QFN48_7X7
UMA only@ default is ASM1442 p/n: SA00003GT00

Discrete use +3VS_delay C601 DIS@ 2

23 VGA_HDMI_TXD2- 1 0.1U_0402_16V7K HDMI_C_TX2-R643 1 DIS@ 2 499_0402_1%
C600 DIS@ 2 1 0.1U_0402_16V7K HDMI_C_TX2+R642 1 DIS@ 2 499_0402_1%
23 VGA_HDMI_TXD2+
C603 DIS@ 2 1 0.1U_0402_16V7K HDMI_C_TX1-R645 1 DIS@ 2 499_0402_1% HDMI_CLK- DIS@ 3 2 HDMI_C_CLK-
23 VGA_HDMI_TXD1-
2
G

C602 DIS@ 2 1 0.1U_0402_16V7K HDMI_C_TX1+R644 1 DIS@ 2 499_0402_1% HDMI_CLK+ 4 1 HDMI_C_CLK+

23 VGA_HDMI_TXD1+
DIS@ RP6 0_0404_4P2R_5%
23 VGA_HDMI_SDATA 3 1 HDMI_SDATA C607 DIS@ 2 1 0.1U_0402_16V7K HDMI_C_TX0-R649 1 DIS@ 2 499_0402_1% HDMI_TX0- DIS@ 3 2 HDMI_C_TX0-
23 VGA_HDMI_TXD0-
2N7002_SOT23 C606 DIS@ 2 1 0.1U_0402_16V7K HDMI_C_TX0+R648 1 DIS@ 2 499_0402_1% HDMI_TX0+ HDMI_C_TX0+
S

23 VGA_HDMI_TXD0+ 4 1
Q45 RP5 0_0404_4P2R_5%
2
G

C605 DIS@ 2 1 0.1U_0402_16V7K HDMI_C_CLK-R647 1 DIS@ 2 499_0402_1% HDMI_TX1- DIS@ 3 2 HDMI_C_TX1-

23 VGA_HDMI_TXC-
DIS@ C604 DIS@ 2 1 0.1U_0402_16V7K HDMI_C_CLK+R646 1 DIS@ 2 499_0402_1% HDMI_TX1+ 4 1 HDMI_C_TX1+
23 VGA_HDMI_TXC+
23 VGA_HDMI_SCLK 3 1 HDMI_SCLK RP7 0_0404_4P2R_5%
D

1
+HDMI_5V_OUT Q44 HDMI_TX2- DIS@ 3 HDMI_C_TX2-
S

2
2N7002_SOT23 Q47 HDMI_HPD +3VS_DELAY DIS@ 2 HDMI_TX2+ 4 1 HDMI_C_TX2+

1
2N7002_SOT23
G RP8 0_0404_4P2R_5%
2

1 R626 S

3
C247 DIS@ R231 2 DIS@ 1 +3VS_delay @
+3VS 0_0402_5% R237 100K_0402_5%
A A
5

0.1U_0402_16V4Z U21 @ 2.2K_0402_5%

2
2
OE#
P

2 A Y 4 VGA_HDMI_DET 22
2
G

SG@ DIS@
SDVO_SDATA HDMI_SDATA
3 1 Security Classification Compal Secret Data Compal Electronics, Inc.
3

2N7002_SOT23
S

Q67 74AHCT1G125GW _SOT353-5 2009/4/15 2010/04/15 Title

Issued Date Deciphered Date
2
G

SG@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Level Shife & Conn
SDVO_SCLK 3 1 HDMI_SCLK Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
S

2N7002_SOT23 Q68
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 30 of 60
5 4 3 2 1
 A B C D E F G H

+3VS +5VS_HDD1 0.1U_0402_16V4Z 10U_0805_10V4Z

1 1 1 1 1
C143 C145 C137 C153 C141

0.1U_0402_16V4Z
SATA HDD1 Conn.
2 2 2 2 2
CL 4.0 mm
1000P_0402_50V7K 1U_0402_6.3V4Z JSATA1

1 GND
C439 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2
13 SATA_PTX_DRX_P0 HTX+
C438 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3
13 SATA_PTX_DRX_N0 HTX-
4
C441 1 SATA_DTX_PRX_N0 GND
2 0.01U_0402_16V7K 5 HRX-
1 13 SATA_DTX_C_PRX_N0 C440 1 SATA_DTX_PRX_P0 1
13 SATA_DTX_C_PRX_P0 2 0.01U_0402_16V7K 6 HRX+
7 GND

+3VS 8 VCC3.3
9
VCC3.3
10 VCC3.3
11 GND
12
GND
13 GND
1 2 +5VS_HDD1 14
+5VS VCC5
R64 0_0805_5% 15 VCC5
16
VCC5
17
GND
18
RESERVED
19 GND
20
VCC12
21 VCC12 GND 24
22 23
VCC12 GND

OCTEK_SAT-22SU1G_NR
CONN@

2 2

Placea caps. near ODD CONN.

+5VS_HDD 0.1U_0402_16V4Z 10U_0805_10V4Z

1 1 1 1
C273 C272 C266 C267

2 2 2 2

1000P_0402_50V7K 1U_0402_6.3V4Z SATA ODD Conn.

JSATA2

1
C292 1 SATA_PTX_C_DRX_P1 1
13 SATA_PTX_DRX_P1 2 0.01U_0402_16V7K 2
C288 1 SATA_PTX_C_DRX_N1 2
13 SATA_PTX_DRX_N1 2 0.01U_0402_16V7K 3 3
4
C284 1 SATA_DTX_PRX_N1 4
13 SATA_DTX_C_PRX_N1 2 0.01U_0402_16V7K 5
C283 1 SATA_DTX_PRX_P1 5
13 SATA_DTX_C_PRX_P1 2 0.01U_0402_16V7K 6
6
7
R270 1 @ 7
2 1K_0402_1% 8
8
9
+5VS_HDD 9
+5VS 1 2 10 10
R239 0_0805_5% 11
11
12
12
13
13
14 16
14 GND
15 17
3 15 GND 3

OCTEK_SLS-13DB1G_NR

CONN@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title
HDD & ODD & MINI CARD &CARDREADER Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 31 of 60
A B C D E F G H
 A B C D E

For Wireless LAN For TV-Tuner/HW MPEG

+3VS +1.5VS +3VS
+3VS +1.5VS +5VS

1 1 1 1 1 1
C653 C348 C670 C349 C358 C320 1 1 1 1 1 1
C641 C642 C664 C644 C677 C681
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z mini2@ mini2@ mini2@ mini2@ mini2@ mini2@
2 2 2 2 2 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
1 +5VS 1

JMINI1 JMINI2
PCH_PCIE_WAKE# R677 1 @ 2 0_0402_5% 1 2 +3VS PCH_PCIE_WAKE#
1 @ 2 1 2 +3VS
15,33 PCH_PCIE_WAKE# 1 2 1 2
3 4 R679 0_0402_5% 3 4
3 4 3 4
5 5 6 6 +1.5VS 5 5 6 6 +1.5VS
14 MINI1_CLKREQ# 7 8 14 MINI2_CLKREQ# 7 8
7 8 7 8
9 9 10 10 9 9 10 10
14 CLK_PCIE_MINI1# 11 11 12 12 14 CLK_PCIE_MINI2# 11 11 12 12
14 CLK_PCIE_MINI1 13 14 14 CLK_PCIE_MINI2 13 14
13 14 13 14
15 15 16 16 15 15 16 16

17 18 17 18
17 18 WL_OFF# 17 18
19 20 WL_OFF# 37 19 20
19 20 PCIE_RST# 19 20 PCIE_RST#
21 22 PLT_RST_BUF# 17 21 22
21 22 R680 1 21 22
14 PCIE_DTX_C_PRX_N2 23 23 24 24 2 0_0603_5% +3VS 14 PCIE_DTX_C_PRX_N4 23 23 24 24
14 PCIE_DTX_C_PRX_P2 25 26 R682 1 2 0_0603_5% +3VALW 14 PCIE_DTX_C_PRX_P4 25 26
25 26 @ 25 26
27 27 28 28 27 27 28 28
29 30 PCH_SMBCLK PCH_SMBCLK 12,14 29 30 PCH_SMBCLK
29 30 PCH_SMBDATA 29 30 PCH_SMBDATA
14 PCIE_PTX_C_DRX_N2 31 32 PCH_SMBDATA 12,14 14 PCIE_PTX_C_DRX_N4 31 32
31 32 31 32
14 PCIE_PTX_C_DRX_P2 33 34 14 PCIE_PTX_C_DRX_P4 33 34
33 34 33 34
35 35 36 36 USB20_N4 17 35 35 36 36 USB20_N5 17
37 37 38 38 USB20_P4 17 37 37 38 38 USB20_P5 17
+3VS 39 40 +3VS 39 40
39 40 39 40
41 42 (MINI1_LED#) 41 42 (MINI1_LED#)
41 42 41 42
43 44 Mini1_LED# 38 43 44
43 44 43 44
45 46 45 46
0_0402_5% 45 46 45 46
47 47 48 48 (9~16mA) 47 47 48 48

1
R668 1 2 E51TXD_P80DATA_R 49 50 E51TXD_P80DATA_R 49 50
37 E51TXD_P80DATA E51RXD_P80CLK 49 50 E51RXD_P80CLK 49 50
51 52 R694 51 52
37 E51RXD_P80CLK 51 52 51 52
@ 100K_0402_5%
2 G1 2
G2
G3
G3

G1
G2
G3
G3
2
FOX_AS0B226-S99N-7F FOX_AS0B226-S99N-7F
53
54
55
56

53
54
55
56
CONN@ CONN@

5.2 mm 高 +3VALW
9.2 mm 高
Mini Card Power Rating
Power Primary Power (mA) Auxiliary Power (mA)
Peak Normal Normal
+3VS 1000 750
+3V 330 250 250 (wake enable)
+1.5VS 500 375 5 (Not wake enable)

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2007/12/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD (WLAN & TV-Tuner)
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 32 of 60
A B C D E
 5 4 3 2 1

+3V_LAN
60mil
+3VALW R8 1 2

0_1206_5%
1 1
C9 C375

4.7U_0805_10V4Z
D U30 2 2 D
0.1U_0402_16V4Z
42 25 +LAN_BIASVDDH
+3V_LAN VDDC BIASVDDH

+1.2V_LAN 0.1U_0402_16V4Z 6 14 +LAN_XTALVDDH

VDDC XTALVDDH
1 1 1 1 15
C382 C385 C389 C376 VDDC
41 VDDC
30 +LAN_AVDDH
4.7U_0603_6.3V6K AVDDH
2 2 2 2 SPROM_CLK SPROM_DOUT
AVDDH 36
0.1U_0402_16V4Z 0.1U_0402_16V4Z (EECLK) (EEDATA)
27 AVDDL
33 37 LAN_MIDI3- On chip 1 0
+LAN_AVDDL AVDDL TRD3_N LAN_MIDI3- 34
39
AVDDL LAN_MIDI3+
38 LAN_MIDI3+ 34
TRD3_P AT24C02 1 1

35 LAN_MIDI2-
TRD2_N LAN_MIDI2- 34 +3V_LAN
34 LAN_MIDI2+
+LAN_GPHYPLLVDDL24 TRD2_P LAN_MIDI2+ 34
C8 1 2 0.1U_0402_16V4Z
GPHY_PLLVDDL
31 LAN_MIDI1-
TRD1_N LAN_MIDI1- 34

1
32 LAN_MIDI1+
TRD1_P LAN_MIDI1+ 34
R3 R4
+LAN_PCIEPLLVDD 18 @ 1K_0402_5% 1K_0402_5%
PCIE_PLLVDDL LAN_MIDI0- U1 @
TRD0_N 29 LAN_MIDI0- 34
21 8 1

2
PCIE_PLLVDDL LAN_MIDI0+ VCC A0
28 LAN_MIDI0+ 34 7 2
TRD0_P SPROM_CLK WP A1
6 3
C SPROM_DOUT SCL NC C
5 SDA GND 4

AT24C02_SO8

1
LINKLED# 48 2 1 LAN_LINK# 34
R378 R6 R7
0.1U_0402_16V7K 47 0_0402_5% 1K_0402_5% 1K_0402_5%
SPD100LED#
14 PCIE_DTX_C_PRX_P1 1 2 C394 PCIE_DTX_PRX_P1 17 PCIE_TXD_P @
14 PCIE_DTX_C_PRX_N1 1 2 C393 PCIE_DTX_PRX_N1 16 46

2
PCIE_TXD_N SPD1000LED#
22 PCIE_RXD_P
0.1U_0402_16V7K 23 45 2 1
LAN_PME# PCIE_RXD_N TRAFFICLED# R379 LAN_ACTIVITY# 34
14 PCIE_PTX_C_DRX_P1 4 WAKE#
LAN_RESET# 2 0_0402_5%
14 PCIE_PTX_C_DRX_N1 REST#
20 PCIE_REFCLK_P
R388 1 @ 2 0_0402_5% 19
15,32 PCH_PCIE_WAKE# PCIE_REFCLK_N
37 EC_PME# R384 1 2 0_0402_5%
+3V_LAN R382 1 24.7K_0402_5%
20mil
R389 1 20_0402_5% L24
5,17,37 PLT_RST#
5 +LAN_XTALVDDH 1 1 2
MODE +3V_LAN
C388 BLM18AG601SN1D_2P
14 CLK_PCIE_LAN
0.1U_0402_16V4Z
14 CLK_PCIE_LAN#
2
20mil
L23
43 SPROM_DOUT +LAN_BIASVDDH 1 1 2
EEDATA C387 BLM18AG601SN1D_2P
44 SPROM_CLK
R380 1 EECLK
+3VS 2 1K_0402_5% 40 0.1U_0402_16V4Z
VMAIN_PRSINT 2
20mil
R385 1 2 10K_0402_5% 1 L21
LOW_PWR +LAN_AVDDH
1 1 1 2
C378 C383 BLM18AG601SN1D_2P
B +1.2V_LAN_L B
SR_LX 11 1 2 +1.2V_LAN
L1 S INDUC_ 4.7UH +-20% SIA4012-4R7M 0.1U_0402_16V4Z 0.1U_0402_16V4Z
XTALO 13 8 2 2
XTALO SR_VFB 1 1
C384
LAN_XTALI 12 C11 20mil
XTALI 0.1U_0402_16V4Z 10U_0805_10V4Z L25
2 2 +LAN_PCIEPLLVDD 1 2 +1.2V_LAN
1 1 BLM18AG601SN1D_2P
R392
C390 C395
1 2 LAN_RDAC 26 RDAC 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
SR_VDDP 10 +3V_LAN 2 2
1.24K_0402_1% 1 1
9 C10 C386
SR_VDD

2 2 20mil
3 L26
14 LAN_CLKREQ# CLKREQ# 4.7U_0805_10V4Z 0.1U_0402_16V4Z +LAN_GPHYPLLVDDL 1 2 +1.2V_LAN
7 1 1 BLM18AG601SN1D_2P
NC C391 C396
PAD

0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2
49

BCM57780A0KMLG_QFN48_7X7 20mil
L22
+LAN_AVDDL 1 2 +1.2V_LAN
1 1 BLM18AG601SN1D_2P
C379 C380

LAN_XTALI 0.1U_0402_16V4Z 4.7U_0603_6.3V6K

2 2
XTALO
A A
1

R11
200_0402_1%
2

Y1
1 2 LAN_XTALO Security Classification Compal Secret Data Compal Electronics, Inc.
1 1 Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

C14
25MHZ_20PF_7A25000012
C34
Broadcom BCM57780
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
27P_0402_50V8J 27P_0402_50V8J Size Document Number Rev
2 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NALG0 M/B LA-5681P Schematic 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 23, 2009 Sheet 33 of 60
5 4 3 2 1
 5 4 3 2 1

D D

JRJ1
LAN_ACTIVITY# 12
T1 33 LAN_ACTIVITY# Yellow LED-
1 24 +3V_LAN 2 1 11
LAN_MIDI0+ TCT1 MCT1 RJ45_MIDI0+ R394 1K_0402_5% Yellow LED+
33 LAN_MIDI0+ 2 23
LAN_MIDI0- TD1+ MX1+ RJ45_MIDI0- RJ45_MIDI3-
33 LAN_MIDI0- 3
TD1- MX1-
22 8
PR4- Guide Pin
4 21
LAN_MIDI1+ TCT2 MCT2 RJ45_MIDI1+ RJ45_MIDI3+
33 LAN_MIDI1+ 5 20 1 7
LAN_MIDI1- TD2+ MX2+ RJ45_MIDI1- PR4+
6 19

220P_0402_50V7K
33 LAN_MIDI1- TD2- MX2- C392
7 18 RJ45_MIDI1- 6
LAN_MIDI2+ TCT3 MCT3 RJ45_MIDI2+ PR2-
33 LAN_MIDI2+ 8 17
LAN_MIDI2- TD3+ MX3+ RJ45_MIDI2- 2 RJ45_MIDI2-
33 LAN_MIDI2- 9 16 5
TD3- MX3- PR3-
10 15
LAN_MIDI3+ TCT4 MCT4 RJ45_MIDI3+ RJ45_MIDI2+
33 LAN_MIDI3+ 11 14 4
LAN_MIDI3- TD4+ MX4+ RJ45_MIDI3- PR3+
33 LAN_MIDI3- 12 13
TD4- MX4- RJ45_MIDI1+ 3
350uH_GSL5009-1 LF PR2+
RJ45_MIDI0- 2
PR1-
14
RJ45_MIDI0+ SHLD2
1
PR1+
13
SHLD1

1
LAN_LINK# 10
33 LAN_LINK# Green LED-
1 1 1 1 R395 R396 2 1 9
+3V_LAN Green LED+
C37 C33 C13 C12 75_0402_1% 75_0402_1% R409 1K_0402_5%
SUYIN_100073FR012G101ZL

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z conn@
2 2 2 2 1 2
R403 R408
0.1U_0402_16V4Z 0.1U_0402_16V4Z 75_0402_1% 75_0402_1% LAN_ACTIVITY# C419
LAN_LINK# 220P_0402_50V7K

2
RJ45_GND
Place close to TCT pin RJ45_GND LANGND
40mil 1 2 40mil

2
C D2 1 1 C
C420
PJDLC05_SOT23-3 1000P_1206_2KV7K C418 C421
4.7U_0805_10V4Z
@ 2 2

0.1U_0402_16V4Z

1
LAN_ACTIVITY# 1 2
C5
68P_0402_50V8J
@

LAN_LINK# 1 2
C6
68P_0402_50V8J
@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NALG0 M/B LA-5681P Schematic 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 23, 2009 Sheet 34 of 60
5 4 3 2 1
 A B C D E

Finger Print Conn. ESATA CONN

R717 1 2 0_0402_5%
D23
Function L69 @
D0 D1 USB20_N8_R USB20_P8
17 USB20_N8 1 1 2 2 +USB_VCCA 4 VIN IO1 2
0 0 defalut; CH0/CH1 ->0dB
USB20_N8 3 1
USB20_P8_R IO2 GND
0 1 CH0->2.5dB pre-emphasis;CH1->0dB 17 USB20_P8 4 4 3 3
PRTR5V0U2X_SOT143-4
1 0 CH1->2.5dB pre-emphasis;CH0->0dB WCM2012F2S-900T04_0805 @

1 1 1 CH0/CH1->2.5dB pre-emphasis 1 2
1
R718 0_0402_5%

+3VS

1U_0402_6.3V4Z 0.1U_0402_16V4Z COAL LAY JeSATA1

+3VS +USB_VCCA
1 1 1
C589 C538 C539 JUSB2
1
eDriver@ eDriver@ eDriver@ USB20_N8_R VCC
2 D-

1
+3VALW +3VS 2 2 2 USB20_P8_R 3
R614 R613 D+
4 GND
4.7K_0402_5% 4.7K_0402_5% 0.1U_0402_16V4Z
@ @ 5
GND1
1

2
R256 R255 ESATA_D0 ESATA_D1 GND2
7 GND3
0_0603_5% 0_0603_5% 8
GND4

1
@ FP@ +USB_VCCA
JFP1 R612 R611 eDriver@ W=60mils SUYIN_020173MR004G565ZR
2

FP@ C264 6 0_0402_5% 0_0402_5% 1000P_0402_50V7K CONN@

0.1U_0402_16V4Z G2 eDriver@
5 1
G1
2 1 4 1 1

2
4 R601 @ +
17 USB20_N11 3 3 1 2 470_0402_5% C511 C519 @
2 eDriver@ C461
17 USB20_P11 2
1 eDriver@ 150U_B_6.3VM_R40M JESAT1
1
3

SATA_PTX_DRX_P4 R597 1 2 0_0402_5% SATA_PTX_RPO_DRX_P4 2 2 2 1 USB

13 SATA_PTX_DRX_P4 SATA_PTX_DRX_N4 SATA_PTX_RPO_DRX_N4 USB20_N8_R VBUS
D12 ACES_85201-04051 R600 1 2 0_0402_5% 470P_0402_50V7K 2
13 SATA_PTX_DRX_N4 D-
SM05T1G_SOT23-3 CONN@ USB20_P8_R 3
SATA_DTX_C_PRX_N4R603 1 D+
13 SATA_DTX_C_PRX_N4 2 0_0402_5% SATA_DTX_RPI_PRX_N4 4 GND
@ SATA_DTX_C_PRX_P4R607 1 2 0_0402_5% SATA_DTX_RPI_PRX_P4 eDriver@
13 SATA_DTX_C_PRX_P4
eDriver@ eDriver@ 5 GND
1

2 eDriver@ SATA_PTX_RPO_DRX_P4C543 2 SATA_PTX_C_DRX_P4 2

10.01U_0402_25V7K 6 A+
eDriver@ U39 +3VS SATA_PTX_RPO_DRX_N4C548 2 SATA_PTX_C_DRX_N4
10.01U_0402_25V7K 7 A- ESATA
2 1 7 EN
VCC 6
+3VS 8 GND SHIELD 12
eDriver@ R610 10K_0402_5% SATA_DTX_RPI_PRX_N4 C552 2 SATA_IRX_DTX_N5
0.01U_0402_25V7K
SATA_PTX_DRX_P4 C545 2 SATA_PTX_RPI_DRX_P4 VCC 10 SATA_DTX_RPI_PRX_P4 C557 2
1
SATA_IRX_DTX_P5
9 B- SHIELD 13
1 0.01U_0402_25V7K 1 RX_0P VCC 16 10.01U_0402_25V7K 10 B+ SHIELD 14
SATA_PTX_DRX_N4 C551 2 1 0.01U_0402_25V7K SATA_PTX_RPI_DRX_N4 2 RX_0N
VCC 20 eDriver@ 11 GND SHIELD 15
eDriver@ eDriver@
SATA_DTX_C_PRX_P4 C560 2 1 0.01U_0402_25V7K SATA_DTX_RPO_PRX_P4 5 TX_1P ESATA_D0 TYCO_1909574-1
SATA_DTX_C_PRX_N4 C553 2 D0 9
1 0.01U_0402_25V7K SATA_DTX_RPO_PRX_N4 4 TX_1N D1 8
ESATA_D1 CONN@
eDriver@
eDriver@ 3 GND SATA_PTX_RPO_DRX_P4
TX_0P 15 SATA_PTX_RPO_DRX_N4
13 GND
R721 1 @ TX_0N 14
+3VS 2 0_0402_5% 17 GND
R722 1 eDriver@2 0_0402_5% 18 GND SATA_DTX_RPI_PRX_N4
R723 1 eDriver@2 0_0402_5% RX_1N 12 SATA_DTX_RPI_PRX_P4
19 GND
RX_1P 11
21 PAD

2
R724 SN75LVCP412RTJR_QFN20_4X4~D
0_0402_5% eDriver@
eDriver@

1
Bluetooth Conn.
To USB/B Connector USB CONN.
3 R719 1 3
2 0_0402_5%
+3VALW +3VS D9
L70 @
1 2 USB20_N0_R 4 2 USB20_P0
17 USB20_N0 1 2 +USB_VCCA VIN IO1
USB20_N0 3 1
USB20_P0_R IO2 GND
1 1 17 USB20_P0 4 3
C687 C694 4 3 PRTR5V0U2X_SOT143-4
WCM2012F2S-900T04_0805 @
0.1U_0402_16V4Z 1U_0603_10V4Z 80mil
3

2 2
S
G JUSB3 1 2
1 2 2 1 +5VALW R720 0_0402_5%
37 BT_ON# 1
R690 10K_0402_5% Q53
AO3413_SOT23-3 2 2 +USB_VCCA
3 3
D
SYSON# 43
1

150U_B_6.3VM_R40M

1 4 4

470P_0402_50V7K
C684 W=40mils 5 5 USB20_N1 17
0.1U_0402_16V4Z
+BT_VCC 6 6 USB20_P1 17 1
2 7 7 + C708
1
C709
1 1 8 8 USB_OC#0 17
1

C683 C678 +USB_VCCA +3VALW

R689 GND 9
4.7U_0805_10V4Z 300_0603_5% GND 10 2 2
+5VALW 80mil

1
2 2 ACES_85201-08051 JUSB1 R168
0.1U_0402_16V4Z 1 U20 0_0402_5%
2

USB20_N0_R VCC R164

CONN@ 2 1 8 1 2 USB_OC#2 17
+5VALW USB20_P0_R D- GND OUT 100K_0402_5%
3 2 7
D+ IN OUT
1

D
4 3 6

2
Q54 GND IN OUT
2 1 4 5 1 2 USB_OC#4 17
G 2N7002_SOT23 C239 EN# FLG R169
1 5
C346 GND1 TPS2061DRG4_SO8 10K_0402_5%
S 6 1
3

GND2 4.7U_0805_10V4Z C201

7
4.7U_0805_10V4Z GND3 2
8 GND4
4 2 0.1U_0402_16V4Z 4
+BT_VCC SUYIN_020173MR004G565ZR 2
CONN@ CONN@
ACES_87213-0800G 43 SYSON#
8 8 GND 10
7
7
17 USB20_P10 6 6
17 USB20_N10 5
4
5
4
Security Classification Compal Secret Data Compal Electronics, Inc.
3 3 Issued Date 2009/5/12 Deciphered Date 2009/12/31 Title
2
1
2
9 NEW CARD & eSATA Connector
1 GND THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
JBT1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 35 of 60
A B C D E
 5 4 3 2 1

+3VS +3VS_READER +REG18_PLL 2 1 +REG18

R361 0_0402_5%

R364 1 2 0_1206_5% U29

C363 2 1 0.1U_0402_16V4Z 1 AV_PLL

3 NC
7 NC
D +XDPW R_SDPW R_MSPW R +XDPW R_SDPW R_MSPW R 9 D
CARD_3V3
+3VS_READER 11 D3V3
33 10 C367 1 2 1U_0402_6.3V4Z
D3V3 VREG
1 1 C693 MS_D4 22
C362 0.1U_0402_16V4Z 30
+3VS_READER @ NC
8 3V3_IN
4.7U_0603_6.3V6K RST# 44
2 2 MODE_SEL RST#
2 45 MODE_SEL
XTLO 47 43 XDCLE
XTLI XTLO XD_CLE_SP19 XDCE#
48 XTLI XD_CE#_SP18 42
@ R343 41 XDALE
100K_0402_5% XD_ALE_SP17 SDDAT2_XDRE#
17 USB20_N9 4 DM SD_DAT2/XD_RE#_SP16 40
Internal 200K Pull UP 17 USB20_P9 5 39 SDDAT3_XDW E#
1

DP SD_DAT3/XD_WE#_SP15 XD_RDY
44 5IN1_LED# 14 GPIO0 XD_RDY_SP14 38
37 SDDAT4_XDW P#_MSD7
R345 1 SD_DAT4/XD_WP#/MS_D7_SP13
Vender suggesttion 2 0_0402_5% RST#
SD_DAT5/XD_D0/MS_D6_SP12 35 SDDAT5_XDD0_MSD6
1 34 SDCLK_XDD1_MSCLK_L R330 2 1 0_0402_5% SDCLK_XDD1_MSCLK
SD_CLK/XD_D1/MS_CLK_SP11 SDDAT6_XDD7_MSD3
SD_DAT6/XD_D7/MS_D3_SP10 31
C352 29 MS_INS#
1U_0402_6.3V4Z MS_INS#_SP9 SDDAT7_XDD2_MSD2
SD_DAT7/XD_D2/MS_D2_SP8 28
2 SDDAT0_XDD6_MSD0
SD_DAT0/XD_D6/MS_D0_SP7 27
26 SDDAT1_XDD3_MSD1
SD_DAT1/XD_D3/MS_D1_SP6 XDD5_MSBS
XD_D5_SP5 25
23 XDD4_SDDAT1
XD_D4/SD_DAT1_SP4 SDCD
SD_CD#_SP3 21
20 SDW P
SD_WP_SP2 XDCD
XD_CD#_SP1 19
EEDI 18
C R356 2 1 6.19K_0402_1% 2 13 XTAL_CTR R348 2 1 0_0603_5% +3VS_READER
C
RREF XTAL_CTR
MS_D5 24
12 DGND
MODE_SEL 32 15
DGND EEDO
EECS 16
CARD_AGND 6 17
AGND EESK
1

1 46 36 SD_CMD
C357 R347 AGND SD_CMD

2
@ 0_0402_5%
47P_0402_50V8J <BOM Structure> R363
2 RTS5159-GR_LQFP48_7X7
2

0_0603_5% <BOM Structure>

1126. RTS5158E,RTS5159
12 CLK_SD_48M R353 1 2 0_0402_5% add C345 will have power drop
issue when insert Card.
@
1 2 XTLI +CARDPW R
C361 6P_0402_50V8D
1

+CARDPW R +CARDPW R
R355
@ 33_0402_5% JREAD1 1 1 1
1

3 21 C328
B Y5 XD-VCC SD-VCC @ C306 C327 B
28
2

12MHZ_16PF_6X12000012 SDDAT5_XDD0_MSD6 MS-VCC 10U_0805_10V4Z 0.1U_0402_16V4Z

1 32 XD-D0
@ SDCLK_XDD1_MSCLK SDCLK_XDD1_MSCLK 2 2 2
10 7 IN 1 CONN 20
2

@ C366 SDDAT7_XDD2_MSD2 XD-D1 SD_CLK SDDAT0_XDD6_MSD0

9 XD-D2 SD-DAT0 14
22P_0402_50V8J SDDAT1_XDD3_MSD1 8 12 XDD4_SDDAT1 0.1U_0402_16V4Z
2 @ XDD4_SDDAT1 XD-D3 SD-DAT1 SDDAT2_XDRE#
7 XD-D4 SD-DAT2 30
1 2 XTLO XDD5_MSBS 6 29 SDDAT3_XDW E#
C359 6P_0402_50V8D SDDAT0_XDD6_MSD0 XD-D5 SD-DAT3 SDDAT4_XDW P#_MSD7
5 XD-D6 SD-DAT4 27
SDDAT6_XDD7_MSD3 SDDAT5_XDD0_MSD6
EMI 4 XD-D7 SD-DAT5 23
18 SDDAT6_XDD7_MSD3
SDDAT3_XDW E# SD-DAT6 SDDAT7_XDD2_MSD2
34 XD-WE SD-DAT7 16
SDDAT4_XDW P#_MSD7 33 25 SD_CMD
XDALE XD-WP SD-CMD SDCD
35 XD-ALE SD-CD-SW 1
XDCD 40
XD_RDY XD-CD SDW P
39 XD-R/B SD-WP-SW 2
SDDAT2_XDRE# 38
XDCE# XD-RE
37 XD-CE
XDCLE 36 26 SDCLK_XDD1_MSCLK
XD-CLE MS-SCLK SDDAT0_XDD6_MSD0
MS-DATA0 17 1
11 15 SDDAT1_XDD3_MSD1
+XDPW R_SDPW R_MSPW R 7IN1 GND MS-DATA1 SDDAT7_XDD2_MSD2 C337
31 7IN1 GND MS-DATA2 19
+CARDPW R 24 SDDAT6_XDD7_MSD3 @ 22P_0402_50V8J
MS-DATA3 MS_INS# 2
MS-INS 22
XDD5_MSBS
40~60 mil 1 2 41
MS-BS 13

R354 0_0603_5% 7IN1 GND

42 7IN1 GND
2

1
TAITW _R015-A10-LM_NR
A
R362 C364 CONN@ A
100K_0402_5% 0.1U_0402_16V4Z
2
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2009/08/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader RTS5159
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 36 of 60
5 4 3 2 1
 5 4 3 2 1

For EC Tools
+3VALW L16
FBMA-L11-160808-800LMT_0603 KSI[0..7] +3VALW
KSI[0..7] 38
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VALW _EC 1 2 +EC_VCCA JP29
R272 1 1 1 1 2 2 KSO[0..17] 1
KSO[0..17] 38 1
0_0805_5% C287 C299 C312 C282 C274 C275 <BOM Structure>
1 2 E51RXD_P80CLK
2 E51TXD_P80DATA
3 3
2 2 2 2 1 1
1000P_0402_50V7K C302
4 4 AD_ProjectID
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K 2 0.1U_0402_16V4Z R712 ACES_85205-0400

ECAGND
@ 3.3V Switchable
DIS only@ 1.5V DIS only
D
SD028100380 +3VALW 0V UMA D

111
125
22
33
96

67
U25

9
100k_0402_5%

2
VCC
VCC
VCC
VCC
VCC
VCC

AVCC
Rc R713
100K_0402_5%
R293 0_0402_5% DIS@
EC_GA20 1 21 2 @ 1 INVT_PW M
INVT_PW M 28

1
18 EC_GA20 EC_KBRST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP# AD_ProjectID
18 EC_KBRST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 BEEP# 40
SERIRQ 3 26
13 SERIRQ SERIRQ# FANPWM1/GPIO12

2
LPC_FRAME# 4 27 ACOFF 1
13 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 48,49
C289 LPC_AD3 5 2 1 ECAGND R712 C701
13 LPC_AD3 LAD3
@ 22P_0402_50V8J
13 LPC_AD2
LPC_AD2 7 LAD2 PWM Output C314 0.01U_0402_16V7K Rd 0_0402_5% @
2 1 R289 2 1 @ 33_0402_5% 13 LPC_AD1 8 63 BATT_TEMP UMA only@
LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 46 2
LPC_AD0 BATT_OVP
13 LPC_AD0 10 LAD0 LPC & MISC 64 BATT_OVP 48

1
BATT_OVP/AD1/GPIO39 ADP_I 0.1U_0402_16V4Z
ADP_I/AD2/GPIO3A 65 ADP_I 48
12 AD Input 66 AD_BID0
17 CLK_PCI_LPC PCICLK AD3/GPIO3B
5,17,33 PLT_RST# 13 PCIRST#/GPIO05 AD4/GPIO42 75
+3VALW R309 2 1 47K_0402_5% EC_RST# 37 76 AD_ProjectID
EC_SCI# ECRST# SELIO2#/AD5/GPIO43 +3VALW
18 EC_SCI# 20 SCI#/GPIO0E
C313 2 1 0.1U_0402_16V4Z 38
15 PM_CLKRUN# CLKRUN#/GPIO1D
DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG 28

2
70 EN_DFAN1
EN_DFAN1/DA1/GPIO3D EN_DFAN1 42 +3VALW
DA Output 71 IREF R307
+3VALW IREF/DA2/GPIO3E IREF 48
KSI0 55 KSI0/GPIO30 DA3/GPIO3F 72 CALIBRATE#
CALIBRATE# 48 Ra 100K_0402_5%
KSI1 56 KSI1/GPIO31

2
1 2 EC_SMB_CK1 KSI2 57

1
R285 2.2K_0402_5% KSI3 KSI2/GPIO32 EC_MUTE# R741 AD_BID0
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE 41
C 1 2 EC_SMB_DA1 KSI4 59 KSI4/GPIO34 PSDAT1/GPIO4B 84 VGA_idle
VGA_idle 22
100K_0402_5% C

2
R291 2.2K_0402_5% KSI5 60 85 PW R_SAVE_LED# PW R_SAVE_LED# 38 1
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C T/P_LOCK_LED# R306 C304
61 PS2 Interface 86 T/P_LOCK_LED# 38

1
KSI6/GPIO36 PSDAT2/GPIO4D
1 2 LID_SW # KSI7 62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK
TP_CLK 38
VGA_idle Rb 33K_0402_1%
R267 100K_0402_5% KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 38 2
KSO1 40

1
KSO1/GPIO21
1 2 KSO1 KSO2 41 KSO2/GPIO22
0.1U_0402_16V4Z
R313 47K_0402_5% KSO3 42 97 3S/4S#
KSO3/GPIO23 SDICS#/GPXOA00 3S/4S# 48
1 2 KSO2 KSO4 43 KSO4/GPIO24 SDICLK/GPXOA01 98 65W /90W #
65W /90W # 48
+5VS
R314 47K_0402_5% KSO5
10/1 ENE Recommand KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW #
Program_LED# 38
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW # 38
KSO7 46 SPI Device Interface TP_CLK 2 1
KSO7/GPIO27
1 2 EC_PME# KSO8 47 KSO8/GPIO28
4.7K_0402_5% R288
R266 @ 10K_0402_5% KSO9 48 119 EC_SI_SPI_SO TP_DATA 2 1
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 38
KSO10 49 120 EC_SO_SPI_SI 4.7K_0402_5% R286
+3VALW KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 38
KSO11 50 SPI Flash ROM 126 EC_SPICLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK 38 +3VALW
KSO12 51 128 EC_SPICS#/FSEL#
KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# 38
KSO13 52
KSO14 KSO13/GPIO2D 10/1 EC Recommand
53 KSO14/GPIO2E
5

KSO15 54 73 EC_RCIRRX 3S/4S# 2 1

KSO16 KSO15/GPIO2F CIR_RX/GPIO40 PCH_TEMP_ALERT# R269 100K_0402_5%
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 PCH_TEMP_ALERT# 18
3 4 EC_SMB_DA1 KSO17 82 89 FSTCHG
38 EC_I2C_DA KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 48
90 65W /90W # 2 1
BATT_CHGI_LED#/GPIO52 BATT_Blue_LED# 44
Q28B 91 CAPS_LED# R268 100K_0402_5%
CAPS_LED#/GPIO53 CAPS_LED# 44
2

2N7002DW -T/R7_SOT363-6 EC_SMB_CK1 77 GPIO 92

46 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_Amber_LED# 44
EC_SMB_DA1 78 93 PW R_LED
46 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PW R_LED 44
6 1 EC_SMB_CK1 EC_SMB_CK2 79 SM Bus 95 SYSON
38 EC_I2C_CK 14,22 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 43,51
EC_SMB_DA2 80 121 VR_ON
14,22 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 55
2N7002DW -T/R7_SOT363-6 Q28A 127 ACIN EC_RCIRRX 1 2 +3VALW
B AC_IN/GPIO59 ACIN 15,43,44,45 B
R303 10K_0402_5%
PM_SLP_S3# 6 100 EC_RSMRST#
15 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 15
PM_SLP_S5# 14 101 EC_LID_OUT#
15 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 14
EC_SMI# 15 102 EC_ON Analog Board ID definition,
18 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 39
ME_EN 16 103 EC_SW I#
+3VS 13 ME_EN LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SW I# 15 Please see page 3.
BACKUP_LED# 17 104 EC_PW ROK
38 BACKUP_LED# SUSP#/GPIO0B ICH_PWROK/GPXO06 EC_PW ROK 15
BT_LED# 18 GPO 105 BKOFF#
38 BT_LED# PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 28
EC_I2C_INT1_D 19 GPIO 106 W L_OFF# EC_CRY1 EC_CRY2
EC_PME#/GPIO0D WL_OFF#/GPXO09 W L_OFF# 32
EC suggested 2.2K for SMBus... INVT_PW M R300 2 1 0_0402_5% 25 EC_THERM#/GPIO11 GPXO10 107 EC_CYP_RST#
EC_CYP_RST# 38
1 2 EC_SMB_CK2 42 FAN_SPEED1
FAN_SPEED1 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 PCH_SPKR
PCH_SPKR 13,40 1 1
R292 2.2K_0402_5% BT_ON# 29 C278 C277
35 BT_ON# FANFB2/GPIO15

4
1 2 EC_SMB_DA2 32 E51TXD_P80DATA
E51TXD_P80DATA 30 EC_TX/GPIO16
R290 2.2K_0402_5% E51RXD_P80CLK 31 110 15P_0402_50V8J 15P_0402_50V8J

IN

OUT
32 E51RXD_P80CLK EC_RX/GPIO17 PM_SLP_S4#/GPXID1 PM_SLP_S4# 15 2 2
ON/OFF 32 112 ENBKL
39 ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL 16
PW R_SUSP_LED 34 114 EAPD
44 PW R_SUSP_LED PWR_LED#/GPIO19 GPXID3 EAPD 40
NUM_LED# 36 GPI 115 SUS_PW R_ACK
44 NUM_LED# NUMLED#/GPIO1A GPXID4 SUS_PW R_ACK 15
SUSP#

NC

NC
GPXID5 116 SUSP# 39,43,48,50
1 @ 2 PCH_TEMP_ALERT# 117 PBTN_OUT#
GPXID6 PBTN_OUT# 5,15
R298 2.2K_0402_5% 118 EC_PME#
EC_PME# 33

3
EC_CRY1 GPXID7
122 XCLK1
EC_CRY2 123 124
XCLK0 V18R X2
1
AGND

C276 32.768KHZ_12.5P_MC-306
GND
GND
GND
GND
GND

4.7U_0805_10V4Z C315 100P_0402_50V8J

KB926QFD3_LQFP128_14X14 2 BATT_TEMP 2 1
11
24
35
94
113

69

20mil C316 100P_0402_50V8J

A
L15 BATT_OVP 2 1 A
ECAGND 2 1 C280 100P_0402_50V8J
FBMA-L11-160808-800LMT_0603 ACIN 2 1
+3VALW 1 2
R598 100K_0402_5%
1 2 EC_I2C_INT1_D
38,39 EC_I2C_INT1
D29
CH751H-40PT_SOD323-2 Security Classification Compal Secret Data Compal Electronics, Inc.
caps@ 2009/4/15 2010/04/15 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB926
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 37 of 60
5 4 3 2 1
 U23
+3VALW 1
R257
2
0_0603_5%
C265 1 2 0.1U_0402_16V4Z EC_SPICS#/FSEL#
SPI_WP#
1
3
CS# VCC
8
6
+SPI_VCC
EC_SPICLK_R
To TP/B Conn.
WP# SCLK JTP1
SPI_HOLD# 7 5 EC_SO_SPI_SI
+SPI_VCC HOLD# SI EC_SI_SPI_SO
4 2 +5VS 6 8
GND SO TP_CLK 6 8
37 TP_CLK 5 7
U24 @ MX25L512AMC-12G_SO8 TP_DATA 5 7
37 TP_DATA 4
EC_SPICS#/FSEL# LEFT_BTN# 4
37 EC_SPICS#/FSEL# 1
CE# VDD
8 use 128KB EC ROM SA00002C100 3
3
R275 1 2 4.7K_0402_5% SPI_WP# 3 6 EC_SPICLK_R R261 1 2 0_0402_5% EC_SPICLK 37
RIGHT_BTN# 2
WP# SCK 2
+3VALW R264 1 2 4.7K_0402_5% SPI_HOLD# 7 5 R259 1 2 0_0402_5% EC_SO_SPI_SI 37 1
HOLD# SI R273 1 1
4 2 2 0_0402_5% EC_SI_SPI_SO 37 1 1
VSS SO C263 SW4 SW5
MX25L8005M2C-15G_SOP8 C270 ACES_85201-0605 SMT1-05-A_4P SMT1-05-A_4P
100P_0402_50V8J 100P_0402_50V8J LEFT_BTN# 3 1 RIGHT_BTN# 3 1
2 2
CONN@
4 2 4 2
ENE suggestion SPI Frequency over 66MHz

5
6

5
6
SST: 50MHz TP_CLK
MXIC: 70MHz +5VS TP_DATA
ST: 40MHz

3
C245
D16
0.1U_0402_16V4Z @
PSOT24C_SOT23

1
KSI[0..7] +5VS +3VS MCVCC
KSI[0..7] 37
KSO[0..17] +3VS
KSO[0..17] 37
SW3
JKB1 SMT1-05-A_4P
LED9
KSO0 3 1 KSI2 R304
(Left) KSO0 1 R251 R250 2 1 1 2ON_0FF_TP LED#
1 T/P_lock_LED# 37

1
KSO1 2 4 2
2

1
KSO2 3 499_0402_1%
KSO3 3 R252 HT-121UD_AMBER
4

0_0603_5%

0_0603_5%
To Media/B Conn.

5
6
KSO4 4 @
5 0_0603_5%
KSO5 5
6

2
KSO6 6
7

2
KSO7 7
8
KSO8 8
9
KSO9 9
10
KSO10 10
11
KSO11 11
12
KSO12 12
13
KSO13 13
KSO14
14
15
14
15
JMedi1 FN/B
KSO15 16 1
KSO16 16 1
17 2
KSO17 17 R246 1 2
18 37 EC_I2C_CK 2 0_0402_5% MEDIA_CK 3 NAL90
KSI0 18 3
19 37,39 EC_I2C_INT1 4
KSI1 19 R247 1 4 Jfunc2
20 37 EC_I2C_DA 2 0_0402_5% MEDIA_DA 5
KSI2 20 MC_RST+# 5
21 37 EC_CYP_RST# 1 2 6 1 +3VS
KSI3 21 R240 6 1 KSO0
22 7 2
22 7 2

2
KSI4 23 @ 0_0402_5% 8 3 MINI1_LED#
23 8 3 MINI1_LED# 32
KSI5 24 +3VALW 2 1 R249 9 4 KSI1
KSI6 24 R241 10K_0402_5% 10K_0402_5% GND 4 KSI5
25 27 10 5
KSI7 25 G1 @ GND 5 KSI3
26 28 6
26 G2 ACES_85201-08051 6 KSI4
7

1
CONN@ 7 BT_LED#
(Right) 8
8 BT_LED# 37
ACES_85201-26051 9
9 BACKUP_LED# 37
CONN@ 10
10 PWR_SAVE_LED# 37
13 11
GND 11
14 12
GND 12
To BTN/B Conn. ACES_85201-1205N
KSO16 C570 1 2 100P_0402_50V8J CONN@
KSO15 C571 1 2 100P_0402_50V8J KSO0 KSO3
KSO17 C569 1 2 100P_0402_50V8J
KSO14 C572 1 2 100P_0402_50V8J KSI1 WL_BTN# Program_BTN#
KSO13 C573 1 2 100P_0402_50V8J KSO7 C579 1 2 100P_0402_50V8J KSI2 T/P lock_BTN#
KSO12 C574 1 2 100P_0402_50V8J KSO6 C580 1 2 100P_0402_50V8J KSI3 Back up_BTN# Volum up_BTN#
KSO5 C581 1 2 100P_0402_50V8J KSI4 BT_BTN# Volum down_BTN#
KSI0 C568 1 2 100P_0402_50V8J
KSO4 C582 1 100P_0402_50V8J KSI5 Power save_BTN#
KSO11 C575 1 2 100P_0402_50V8J
2 NALG0
KSO10 C576 1 2 100P_0402_50V8J KSO3 C583 1 2 100P_0402_50V8J
JFunc1
KSI1 C567 1 2 100P_0402_50V8J KSI4 C564 1 2 100P_0402_50V8J 1 +3VS
1 KSO0
2
KSO2 C584 1 100P_0402_50V8J 2 KSO3
2 3
KSI2 C566 1 100P_0402_50V8J 3 KSI1
2 4
KSO1 C585 1 100P_0402_50V8J 4 KSI3
2 5
KSO9 C577 1 100P_0402_50V8J 5 KSI4
2 6
6 BACKUP_LED#
7
KSI3 C565 1 100P_0402_50V8J KSO0 C586 1 100P_0402_50V8J 7 BT_LED#
2 2 8
8 MINI1_LED#
9
KSO8 C578 1 100P_0402_50V8J KSI5 C563 1 100P_0402_50V8J 9 Program_LED#
2 2 10 Program_LED# 37
10
13 11
KSI6 C562 1 2 100P_0402_50V8J Lid Switch 14
GND
GND
11
12
12

KSI7 C561 1 2 100P_0402_50V8J

ACES_85201-1205N
CONN@
(Hall Effect Switch)
+3VALW
1

2
2

C38 R20 47K_0402_5%

VDD

0.1U_0402_16V4Z
1 D3
2

3 1 2 LID_SW# LID_SW# 37
OUTPUT
CH751H-40PT_SOD323-2
GND

1
C41
U3
1

A3212ELHLT-T_SOT23W-3 10P_0402_50V8J
2

Anpec p/n:SA00003B900
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 38 of 60
 A B C D E

Power Button
HDA MDC Conn.
+3VALW
+3VALW

ON/OFF switch 15mil

1
C700
JMDC1

2
1 +MDC_VCC 1U_0603_10V4Z 1
1 1 2 2 1 2
R308 3 4 R706 0_0402_5% 2
13 HDA_SDOUT_MDC 3 4
5 5 6 6 +3VALW
100K_0402_5% 13 HDA_SYNC_MDC 7 8
SW1 HDA_SDIN1_MDC 7 8
13 HDA_SDIN1 1 2 9 10

1
EVQPLHA15_4P D17 R701 33_0402_5% 9 10
13 HDA_RST_MDC# 11 11 12 12 HDA_BITCLK_MDC 13
3 1 2 ON/OFF 37

1
1 ACES_88018-124N
4 2 3 51ON# CONN@ R710
51ON# 45
0_0402_5%
DAN202UT106_SC70-3
5
6

2
1
C698

1
2 22P_0402_50V8J
C305 D18 MCVCC 2

1
1000P_0402_50V7K RLZ20A_LL34 51ON#
1 R173 Caps@
For EMI

2
510K_0402_5%

1
MCVCC +3VS D

2
1 2 Q24 Caps@

2
D

10K_0402_5%
G
EC_ON 2 Q32 R175 Caps@ S 2N7002_SOT23
37 EC_ON

3
@
G
2

S 2N7002_SOT23 10K_0402_5%
3

R177
R322

1
D
10K_0402_5% 2 Q23 Caps@
37,38 EC_I2C_INT1
G
1

2 2
S 2N7002_SOT23

3
Power ON Circuit

+3VALW +3VALW

U16A U16B
SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14

14

For PCH
P

14,52 VGA_PWROK 1 2 3 4 DGPU_PWROK_BUF 18

I O I O
2
G

C190
7

1U_0603_10V6K
@ 1

+5VALW

+3VS

2
+3VALW +3VALW R448
100K_0402_5%
1

3 DIS@ 3
R158 @

1
10K_0402_1% U16C U16D
14

14

R154 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14

10K_0402_1% DGPU_PWR_EN#
P

P
2

1 2 5 6 9 8 +RTCBATT
37,43,48,50 SUSP# I O I O VS_ON 50,51,53
2
G

G
1

D
For +VCCP/+1.05VS

1
SUSP C184 D
43,50 SUSP 2
7

G 0.1U_0402_16V7K DGPU_PWR_EN 2

2
Q22 S 1 G
3

2N7002_SOT23 Q38 S R329

3
1
2N7002_SOT23 1K_0402_5%
R447 DIS@
100K_0402_5%

1 1
DIS@
D19

2
+3VS
+3VALW +3VALW +RTCVCC
C180

2
1

1 2 0.1U_0402_16V4Z
R86 BAS40-04_SOT23-3
31.6K_0402_1% U16E U16F
14

14

+CHGRTC
R85 @ SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 1
10K_0402_1% C319
P

P
2

18 DGPU_PWR_EN 1 2 11 10 13 12 VGA_ON 24,43,52

DIS@ I O I O 0.1U_0402_16V4Z
G

G
1

D 2
2
DGPU_PWR_EN# 2 C179 DIS@
7

G
4 Q13 1U_0603_10V6K 4
S
3

2N7002_SOT23 1

DIS@
DGPU_PWR_EN 1 @ 2
R84 0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK, Reset,RTC, CIR, MDC
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 39 of 60
A B C D E
 A B C D E F G H

1 2
R683 0_0805_5%
+5VAMP
60mil U40
(output = 300 mA)
+3VS +VDDA L51 1 2 1
+5VS
FBMA-L11-201209-221LMA30T_0805 IN
OUT 5 40mil +VDDA
1 1 2 GND
L52 1 2 C652 C648 1 4.75V
FBMA-L11-201209-221LMA30T_0805 3 4 C669
10U_0805_10V4Z SHDN BYP

1
R781 2 2
0.1U_0402_16V4Z G9191-475T1U_SOT23-5 4.7U_0805_10V4Z
1

1
R676 @ C662 2

10K_0402_5%
D30 20K_0402_5%
CH751H-40PT_SOD323-2
1 2 1

2
2

2
0.01U_0402_16V7K
C646
BOM Option
MONO_IN
1 2 ALC268 268@
1U_0402_6.3V6K
ALC888S-VB 888VB@

1
C643 C 1 2
R671 Q50 R675 2.4K_0402_1%
37 BEEP# 1 2 1 2 2
B ALC888S-VC 888VC@
1U_0402_6.3V6K 560_0402_5% E 2SC2411K_SOT23

3
C645
R672
1 2 1 2
13,37 PCH_SPKR
HD Audio Codec ANALOG MIC

1
1U_0402_6.3V6K 560_0402_5%
D28
CH751H-40PT_SOD323-2
L18 JMIC3
10mil +3VS_DVDD 1 2 DMIC_DATA_R 1
+3VS
2 MBK1608121YZF_0603 DMIC_CLK_R 1
2
2
1 1 1
C682 C679 C360
3
+AVDD_HDA 0.1U_0402_16V4Z 10U_0805_10V4Z G1
4 G2
L53 2 2 2
FBMA-L11-160808-800LMT_0603 10U_0805_10V4Z ACES_88266-02001
1 2 0.1U_0402_16V4Z
40mil CONN@
+VDDA
1 1
C350
C699
2 10U_0805_10V4Z 2

25

38

9
2 2 U28

DVDD_IO
AVDD1

AVDD2

DVDD
MIC2_VREFO

14 35 AMP_LEFT
LINE2-L FRONT_L AMP_LEFT 41

1
15 36 AMP_RIGHT R365
LINE2-R FRONT_R AMP_RIGHT 41
2.2K_0402_5%
R331 1K_0402_5% 1 2 MIC2_C_L 16 39 HP_LEFT 15mil AMIC@
MIC2_L SURR_L HP_LEFT 41
DMIC_CLK_R 2 1 INT_MIC_R C343 AMIC@ 4.7U_0603_6.3V6M

2
AMIC@ 1 2 MIC2_C_R 17 41 HP_RIGHT DMIC_CLK_R
MIC2_R SURR_R HP_RIGHT 41
C342 AMIC@ 4.7U_0603_6.3V6M
LINE_L 1 2 LINE_C_L 23 45 @ DMIC_DATA_R 1
41 LINE_L LINE1_L SIDE_L PAD T7
C339 4.7U_0603_6.3V6M R366 AMIC@ 0_0603_5%
LINE_R 1 2 LINE_C_R 24 46 DMIC_CLK_268 1 2 DMIC_CLK C368
41 LINE_R LINE1_R SIDE_R
C338 4.7U_0603_6.3V6M For EMI R359 @ 0_0402_5% 220P_0402_50V7K
18 43 2 AMIC@
CD_L CENTER
20 44 1 2 1 2 C356
CD_R LFE R346 0_0402_5% 22P_0402_50V8J
19
CD_GND
6 HDA_BITCLK_AUDIO 13
MIC1_L MIC1_C_L BITCLK
41 MIC1_L 1 2 21
C341 4.7U_0603_6.3V6M MIC1_L

41 MIC1_R
MIC1_R 1
C340
2 MIC1_C_R
4.7U_0603_6.3V6M
22 MIC1_R SDATA_IN 8 HDA_SDIN0_AUDIO 1
R344
2
33_0402_5%
HDA_SDIN0 13 Digital MIC
MONO_IN 12 37 +3VS
PCBEEP PIN37_VREFO
29 JMIC2
LINE1_VREFO DMIC@
13 HDA_RST_AUDIO# 11 1
3 RESET# DMIC_CLK R372 0_0603_5% DMIC_CLK_R 1 3
LINE2_VREFO 31 2 2
10 10mil DMIC_DATA DMIC_DATA_R 3 5
13 HDA_SYNC_AUDIO SYNC 3 G1
28 MIC1_VREFO_L R371 0_0603_5% 4 6
MIC1_VREFO_L DMIC@ 4 G2
13 HDA_SDOUT_AUDIO 5 SDATA_OUT
Place close to Codec 32 MIC1_VREFO_R ACES_88266-04001
HDA_GPIO0 MIC1_VREFO_R CONN@
2
HDA_GPIO3 SPDIFO2
3 30 MIC2_VREFO
R334 1 SENSE_A GPIO0/DMIC_CLK MIC2_VREFO
41 LINEIN_PLUG# 2 10K_0402_1% 13 10mil 1 2
R337 2 SENSE A CODEC_VREF
41 MIC_PLUG# 1 20K_0402_1% 34 27 @
SENSE B VREF C371 C372
1 1
R338 2 1 39.2K_0402_1% 47 40 C351 220P_0402_50V8J @ 220P_0402_50V8J
41 HP_PLUG# 37 EAPD SPDIFI/EAPD JDREF 2 1
C353

1
C365 100P_0402_50V8J 1 2 SPDIF_R 48 SPDIFO SENSE C 33 0.1U_0402_16V4Z 10U_0805_10V4Z
41 SPDIF R360 0_0402_5% R358 2 2
1 2
DMIC_DATA 1 2 4 26 20K_0402_1%
GPIO1/DMIC_DATA AVSS1
1 R697 2 0_0402_5% 7 42
R696 @ 0_0402_5% DVSS AVSS2

2
ALC888S-VC_LQFP48_7x7
Sense Pin Impedance Codec Signals 1 2
1
R674
2
0_0805_5%
1
R691
2
0_0805_5%
R695 @ 0_0402_5%
39.2K PORT-A (PIN 39, 41) DGND AGND
1 2 1 2
R287 0_0805_5% R663 0_0805_5%
20K PORT-B (PIN 21, 22)
SENSE A
1 2 1 2
10K PORT-C (PIN 23, 24) DMIC_DATA 1 2 HDA_GPIO0 R704 0_0805_5% R658 0_0805_5%
R700 @ 0_0402_5%
SPDIF_HDMI 1 2
SPDIF_HDMI
5.1K PORT-D (PIN 35, 36) R702 0_0402_5%

DMIC_DATA 1 @ 2 HDA_GPIO3 GND GNDA GND GNDA

4 R698 0_0402_5% 4
39.2K PORT-E (PIN 14, 15) DMIC_CLK 1 2
R357 FBMA-L10-160808-301LMT_0603
20K PORT-F (PIN 16, 17)
SENSE B
10K PORT-G (PIN 43, 44)
Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-H (PIN 45, 46) Issued Date 2009/5/12 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC888S-VC
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 40 of 60
A B C D E F G H
 A B C D E

+5VAMP Int. Speaker Conn.

W=40mil 20mil JSPK1
+3VS
1 1 SPKL+ R407 1 2 0_0603_5% SPK_L+ 1
SPKL- R406 0_0603_5% SPK_L- 1
1 1 2 2
C649 C672 SPKR+ R405 0_0603_5% SPK_R+ 2
1 2 3 3 G1 5
C650 0.1U_0402_16V4Z SPKR- R404 1 2 0_0603_5% SPK_R- 4 6
C688 0.1U_0402_16V4Z 2 2 4 G2
0.47U_0603_16V4Z 2 4.7U_0805_10V4Z ACES_88266-04001

2
1 2 AMP_RIGHT_C-1 1 2 AMP_RIGHT_C
40 AMP_RIGHT C673 1U_0402_6.3V6K D5

15

17

25
CONN@

7
1 2 AMP_LEFT_C-1 1 2 AMP_LEFT_C U41 D4 SM05T1G_SOT23-3
40 AMP_LEFT C689 C674 1U_0402_6.3V6K SM05T1G_SOT23-3 @

CVDD

HVDD

PVDD
PVDD

VDD
1

1
0.47U_0603_16V4Z @
R693 R692

1
1 1
2.2K_0402_5% 2.2K_0402_5% 27 19 SPKR+
INR_A ROUT+ SPKR-
1 18

2
INL_A ROUT-
HPF Fc = 604Hz For ESD 10/11
R684 1 2 100K_0402_5% 24 5 SPKL+
/AMP EN LOUT+ SPKL-
LOUT- 6
HP_EN 21
HP_EN HPOUT_R
HP_R 13
+5VAMP HP_RIGHT 1 2 HP_RIGHT_C 1 2 HP_RIGHT_R 28 16 HPOUT_L +5VAMP
40 HP_RIGHT C355 2.2U_0805_10V6K R340 39K_0402_5% HP_LEFT_R INR_H HP_L
2
HP_LEFT HP_LEFT_C INL_H +5VAMP
40 HP_LEFT 1 2 1 2 NC 3
C354 2.2U_0805_10V6K R339 39K_0402_5% VOL_AMP 23 14 HP_PLUG#
SET NC HP_PLUG# 40

3
R333 15K_0402_5% R660
12 100K_0402_5%
VSS

2
1 9 1 Q49B
CP+ C654 R659 2N7002DW-T/R7_SOT363-6
11 26 5

6 1
VOL_AMP C668 CP- GND Q48
4 1U_0603_10V4Z 100K_0402_5%
PGND AO3413_SOT23-3
1U_0603_10V4Z 22 20

4
BIAS PGND
1

D 2 2
10

1
CGND
1

3
S
1 2 1 29
R336 39K_0402_5% G EC_MUTE 37 GND G
SPDIF_PLUG# Q49A
2 2
C347 Q35 C651 APA2051QBI-TRG_TQFN28_4X4 2N7002DW-T/R7_SOT363-6
S
S/PDIF Out JACK
3

2N7002_SOT23 2.2U_0603_10V6K D

1
3

2
2
0.01U_0402_16V7K 2
LINE Out/Headphone Out
2

+5VSPDIF D25
PJDLC05_SOT23-3

1
20mil
@
Gain= 11dB 2 2 D24
C627 C626 PJDLC05_SOT23-3
2 @ 2

1
330P_0402_50V7K 330P_0402_50V7K
R662 1 1 JHP1
VOL_AMP 1 2 HP_EN 56.2_0603_1% 1

3
R681 HPOUT_L 1 2 HPOUT_L_1 1 2 HPOUT_L_2 2
5.1K_0402_5% L46 FBM-11-160808-700T_0603 6
1 HPOUT_R 1 2 HPOUT_R_1 1 2 HPOUT_R_2 3
C707 L45 FBM-11-160808-700T_0603
R661 SPDIF_PLUG# 5
0.047U_0402_16V7K 56.2_0603_1%
2 4
SPDIF 7
40 SPDIF
+5VSPDIF 8
1 10
C635
100P_0402_50V8J 9
2 SINGA_2SJ-E373-T01
CONN@

40 LINEIN_PLUG#
LINE-IN JACK

1
JLINE1
8
7
D27
PJDLC05_SOT23-3
LINEIN_PLUG# 5
@
R670 L50 4
3 75_0603_1% FBM-11-160808-700T_0603 3

3
1 2 LINE_R_1 1 2 LINE_R_R 3
40 LINE_R
6
1 2 LINE_L_1 1 2 LINE_L_R 2
40 LINE_L
L49 1
R669 FBM-11-160808-700T_06031 1
75_0603_1% SINGA_2SJ-E351-S03
C639 C640 CONN@
220P_0402_50V7K 220P_0402_50V7K
2 2 (HDA Jack)
For ESD
I/O status:
a. input/output mount 75 ohm 40 MIC_PLUG#
MIC JACK
b. input only mount 1K ohm
JMIC1
MIC1_VREFO_L MIC1_VREFO_R 8
7

1
R664 R667 5
2.2K_0402_5% 2.2K_0402_5%
R666 L48 4
75_0603_1% FBM-11-160808-700T_0603

2
40 MIC1_R 1 2 MIC1_R_1 1 2 MIC1_R_R 3
6
1 2 MIC1_L_1 1 2 MIC1_L_R 2
40 MIC1_L
L47 1

2
R665 FBM-11-160808-700T_0603
1 1
75_0603_1% SINGA_2SJ-E351-S01
C637 C638 CONN@
220P_0402_50V7K D26
4 2 2 @ 4
PJDLC05_SOT23-3 (HDA Jack)
220P_0402_50V7K

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 41 of 60

A B C D E
 FAN1 Conn
+5VS
C105 10U_0805_10V4Z
1 2

U10
1 8 H1 H8 H15 H2 H3 H11 H16
EN GND H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2
2 VIN GND 7
+VCC_FAN1 3 6
VOUT GND @ @ @ @ @ @ @
37 EN_DFAN1 4 5
VSET GND

1
APL5607KI-TRG_SO8

C134
10U_0805_10V4Z
1 2 H9 H10 H12 H13 H4
H_4P2 H_4P2 H_4P2 H_4P2 H_3P7
+3VS C123 @ @ @ @ @
1000P_0402_50V7K
1 2

1
1
R60
10K_0402_5%
40mil
Jfan1 H17 H24 H20 H23 H19 H22 H14
2

+VCC_FAN1 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2

1 @ @ @ @ @ @ @
37 FAN_SPEED1 2
3
1

1
C131 ACES_85205-03001
1000P_0402_50V7K CONN@ @ @

2
H_3P3 H_3P3
H18 H21 H7
H_4P7X3P7N H_5P1X4P1N H_10P0X6P0N
@ @ @

1
FD2 FD1 FD4 FD3

@ @ @ @

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & COVER LIGHT& Screw Hole
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 42 of 60
 A B C D E

+1.5V to +1.5VSDGPU Transfer +5VALW

+5VALW TO +5VS

2
+1.5V +1.5VSDGPU
+5VALW +5VS R711
100K_0402_5%

4
U42 PJ25
5 @

1
6 3 2 1
2 1

10U_0805_6.3V6M
10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z
7 2 1 1 SYSON#
35 SYSON#

470_0603_5%

10U_0805_6.3V6M
1 1 8 1 C696 C697 R709 JUMP_43X118

6
10U_0805_10V4Z
1 1
C705 C706
C675 C676 SI4800BDY-T1-E3_SO8 2 2 Q57A

1
1 2 2 DIS@ DIS@ SYSON 2 1
2 2 37,51 SYSON
2N7002DW-T/R7_SOT363-6

1
R708
Q56B U33 250mil(6A) 100K_0402_5%
+VSB 2 1 5VS_GATE 2N7002DW-T/R7_SOT363-6 5 SUSP 8 1
R699 D S
1 7 2

2
D S

2
200K_0402_5% 1 C434 6 3 1 1

4
D S
6

C691 10U_0805_10V4Z 5 4 C427 C426 R441

DIS@ D G DIS@ DIS@ 470_0603_5%
Q56A 0.1U_0603_25V7K 2 SI4856ADY_SO8 10U_0805_10V4Z DIS@
SUSP 2 2
2N7002DW-T/R7_SOT363-6 DIS@ 2 2
0.1U_0402_16V4Z

3 1
1

+VSB 1 DIS@ 2 1.5VSDGPU_GATE Q37B 2N7002DW-T/R7_SOT363-6

R444 510K_0402_1% 5 1 DIS@ 2 VGA_ON#

6
1 DIS@ R439 0_0402_5%
C428

4
Q37A 0.1U_0603_25V7K
+3VALW TO +3VS

2
VGA_ON# 1 DIS@ 2 2 DIS@
R440 0_0402_5% DIS@ 2
+3VALW +3VS 2N7002DW-T/R7_SOT363-6 R728

1
@ 2.2M_0402_1%
4

U43 +5VALW

1
5
6 3

2
D
7 2 1 1 2N7002_SOT23

470_0603_5%
10U_0805_10V4Z

1 1 8 1 C695 C692 1U_0603_10V4Z R707 2 ACIN R703

Q59
10U_0805_10V4Z

10U_0805_10V4Z

C686 C685 G 100K_0402_5%

@ S

3
SI4800BDY-T1-E3_SO8 2 2
1 1

1
2 2 2 SUSP 2
D 39,50 SUSP
2 SUSP

3
G
S Q55
3

5VS_GATE 2N7002_SOT23 Q57B

37,39,48,50 SUSP# 5
2N7002DW-T/R7_SOT363-6

4
1
R705
+1.8VS to +1.8VSDGPU Transfer 10K_0402_5%

+1.5V to +1.5VS +1.8VS +1.8VSDGPU

2
PJ26 @
+1.5V +1.5VS 2 1
2 1
SI4856ADY_SO8 JUMP_43X118
5
D G 4 DIS@
6 D S 3
7 2 1 1 U34 SI4800BDY-T1-E3_SO8 100mil(1.5A)
D S
2

8 C293 C294
S 1
1 1 8 1
C281 C279 D R295 1 7 2

2
U26 10U_0805_10V4Z C442 6 3
2 2 1 1
10U_0805_10V4Z 1U_0603_10V4Z 470_0603_5% 10U_0805_10V4Z 5 C443 C437 R458
2 2
10U_0805_10V4Z DIS@ DIS@ DIS@ 470_0603_5%
3 1

2 10U_0805_10V4Z DIS@

4
2 2
0.1U_0402_16V4Z

3 1
+5VALW
Q31B R451
2 1 1.5VS_GATE 2N7002DW-T/R7_SOT363-6 5 SUSP 510K_0402_1% 2N7002DW-T/R7_SOT363-6
+VSB

2
R296 1 DIS@ 2 1.8VSDGPU_GATE Q40B
3 +VSB 3
47K_0402_5% 1 5 1 DIS@ 2 VGA_ON# R456
4

6
C296 1 DIS@ R449 0_0402_5% 100K_0402_5%
6

C433

4
0.1U_0603_25V7K Q40A 0.1U_0603_25V7K DIS@

1
Q31A 2 VGA_ON# DIS@ 2 DIS@
1 2
SUSP 2N7002DW-T/R7_SOT363-6 R454 0_0402_5% DIS@ 2
2
2N7002DW-T/R7_SOT363-6 VGA_ON#
1 VGA_ON#
2
1

2
R299
2.2M_0402_1%

1
R326 2.2M_0402_1% D
@
@ 24,39,52 VGA_ON 2
1

G DIS@

1
Q41 S

3
1

1
D 2N7002_SOT23 2N7002_SOT23
2N7002_SOT23

1
D R459
15,37,44,45 ACIN 2
G Q30 2 ACIN 100K_0402_5% DIS@
S @ Q58 G
3

@ S

2
+1.05VSDGPU
2

R499
DIS@ 470_0603_5%
+1.1VS_VTT +1.05VS +0.75VS +1.8VS +1.5V
1
2

R32 R654 R688 R453 R687 D

470_0603_5% 470_0603_5% 22_0402_5% 470_0603_5% 470_0603_5% 2 VGA_ON#
@ DIS@ G
4 Q42 4
S
1

2N7002_SOT23
1

D D D D D
2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SYSON#
G G G G G
S Q5 S Q46 S Q52 S Q39 S Q51
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 43 of 60
A B C D E
 5 4 3 2 1

MEDIA_LED NUM_LED CAPS_LED

Enlightener LED
+3VS +3VS +3VS
+3VALW +3VALW ON/OFF LED LEFT (BLUE) (BLUE) (BLUE)
(BLUE) (BLUE)

2
LED8

2
R381 R383
100_0402_1% 100_0402_1% +3VS 1 2 2 1 PW R_LED# R377 R376 R375
R386 191_0402_1% HT-191NBQA_BLUE_0603 243_0402_1% 470_0402_5% 470_0402_5%
D LED5 D
1

1
1 2 2 1 PW R_LED#
R373 243_0402_1% HT-191NBQA_BLUE_0603

2
LED1
2

2
LED2 LED3 LED4
LED7 LED6 1 2 2 1 PW R_LED# HT-191NBQA_BLUE_0603 HT-191NBQA_BLUE_0603 HT-191NBQA_BLUE_0603
HT-191NBQA_BLUE_0603 HT-191NBQA_BLUE_0603 R367 191_0402_1% HT-191NBQA_BLUE_0603

1
MEDIA_LED# NUM_LED# NUM_LED# 37 CAPS_LED# CAPS_LED# 37
1

1
ACIN# ACIN#

+3VS

Q14A

2
2N7002DW -T/R7_SOT363-6

36 5IN1_LED# 1 6

SATA_LED# 4 3 MEDIA_LED#
13 SATA_LED#

Q14B

5
ACIN# +3VS 2N7002DW -T/R7_SOT363-6
C C

D
1

2 Q18
15,37,43,45 ACIN
G
S 2N7002_SOT23
3

PW R_LED#
6

Q36A
2N7002DW -T/R7_SOT363-6
37 PW R_LED 2
1

R342

10K_0402_5%
2

PW R_SUSP_LED#
3

B Q36B B
2N7002DW -T/R7_SOT363-6
37 PW R_SUSP_LED 5
1

R341

10K_0402_5%
2

Compal Footprint
1 3
Blue 2 4 Amber

LED11

1 2 2 1 PW R_LED# LED10 Blue

+3VALW B
R349 100_0402_1%
+3VALW 1 2 2 B 1 BATT_Blue_LED# 37
+3VALW 1 2 4 A 3PW R_SUSP_LED# R351 191_0402_1%
R350 191_0402_1%
+3VALW 1 2 4 A 3 BATT_Amber_LED# 37
A HT-297UD/CB _BLUE/AMB_0603 R352 470_0402_5% A
AMB
HT-297UD/CB _BLUE/AMB_0603

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/5/12 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR/B
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 44 of 60
5 4 3 2 1
 A B C D

1 1

PR1
DC231000500 1M_0402_1%
<BOM Structure>
1 2
SINGA_2DC-G756I200 PL1
SMB3025500YA_2P
VIN VIN
VS
VIN
DC_IN_S1 1 2DC_IN_S2
1

1
@ PR2 PR3
G 2 10K_0402_5% 84.5K_0402_1%
G
48,49 PACIN PR6 PR4

8
3 PC3 PR5 10K_0402_1% 22K_0402_5%

2
PC1 PC2 100P_0402_50V8J PC4 0_0402_5% 3 1 2

P
PJP1 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K +
1 2 1 2 1

2
15,37,43,44 ACIN 0

20K_0402_1%
- 2

1
PR7
PU1A

1
PC5
LM358DT_SO8 PC6

0.1U_0603_25V7K
4
PR8 PD1 1000P_0402_50V7K

2
10K_0402_1% GLZ4.3B_LL34-2

2
2

2
PR9
1 2 PR10
10K_0402_1%
1 2
10_0603_5% RTCVREF
PQ1 MCVCC PQ2
@ SI2301BDS-T1-E3_SOT23-3 @ SI2301BDS-T1-E3_SOT23-3
+3VALWP

S
1 Vin Dectector
S

3 3

D
1 RTCVREF
D

2 2

Min. Typ Max.

G
G
2

2
1

@ PR11
200K_0402_1%
PR12
@ 200K_0402_1%
H-->L 16.976V 17.525V 17.728V
L-->H 17.430V 17.901V 18.384V
2

PJ1 PJ4

1
D
+1.05VSP 2 2 1 1 +1.05VS 2 2 1 1 +VGFX_CORE
2 +VGFX_COREP
G @ PQ3 JUMP_43X118 JUMP_43X118
PQ4 S 2N7002W -T/R7_SOT323-3 PJ2 PJ5
3
1

D @ 2N7002W -T/R7_SOT323-3 2 2 1 1 2 2 1 1
2
G SPOK 46,47 JUMP_43X118 JUMP_43X118
S
3

VIN PJ7
+1.5VP 2 2 1 1 +1.5V
PJ3
2

2 1 JUMP_43X118
PD2 +3VALWP 2 1 +3VALW PJ9
LL4148_LL34-2 JUMP_43X118 2 2 1 1
PD3 JUMP_43X118
1

3
LL4148_LL34-2 3

BATT+ 2 1
1

PJ6 PJ10
PR13 PR14 2 1 2 1
PQ5 68_1206_5% 68_1206_5% +5VALWP 2 1 +5VALW +1.1VS_VTTP 2 1 +1.1VS_VTT
TP0610K-T1-E3_SOT23-3 JUMP_43X118 JUMP_43X118
PR15 PJ12
2

200_0603_5% 2 2
CHGRTCP 1 N1 1 1
2 3 1
VS PJ8
JUMP_43X118
1

2 1 PJ31
+VSBP 2 1 +VSB
1

PR16 PC8 2 1
100K_0402_1% PC7 0.1U_0603_25V7K JUMP_43X39 +1.1VS_VTT 2 1 +1.05VS
0.22U_0603_25V7K JUMP_43X118
2

PR17
2

22K_0402_1% PJ32
1 2 2 2 1 1
39 51ON#
JUMP_43X118
PJ11
2 1 PJ14
+1.8VSP 2 1 +1.8VS +VGA_COREP 2 2 1 1 +VGA_CORE
RTCVREF JUMP_43X118
1

JUMP_43X118
PR18 PJ15
PU2 200_0603_5% 2 2
PR19 PR20 G920AT24U_SOT89-3 1 1
560_0603_5% 560_0603_5% 3.3V PJ13 JUMP_43X118
2

1 2 1 2 3 2 N2 2 1
OUT IN +0.75VSP 2 1 +0.75VS
+CHGRTC
JUMP_43X79
1

4 GND PC10 4

PC9
10U_0805_10V4Z 1
1U_0805_25V4Z - PBJ1 + +RTCBATT
2

2 1
+RTCBATT

ML1220T13RE
<BOM Structure>
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0
Date: Friday, October 23, 2009 Sheet 45 of 60
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C

VL
VL
VL
VMB

2
PL2 PR21

1
1 1

PJP2 SMB3025500YA_2P 47K_0402_1%

1 1 BATT_S1 1 2 BATT+ PH1 PC11
MAINPW ON 18,47,49
2 100K_0402_1%_NCP15W F104F03RC 0.1U_0603_25V7K PR22

1
2 47K_0402_1%
3 3

1
4 EC_SMCA 1 2

2
4 EC_SMDA PC12 PC13 PR23
5 5

8
6 1000P_0402_50V7K 0.01U_0402_25V7K 12.4K_0402_1%

2
6

1
PD4 PQ6 D
7 1 2 3

P
7 +
O 1 2 1 2
SUYIN_250133MR007G115ZL TM_REF1 2 G 2N7002W -T/R7_SOT323-3
-

G
PU3A LL4148_LL34-2 S

3
LM393DG_SO8

4
2

1
0.22U_0603_16V7K
PR24 PR25
100_0402_1% 100_0402_1% PR169

15.8K_0402_1%
1

1
PC14
PR27 1M_0402_1%

PR26
100K_0402_1%

1000P_0402_50V7K
1

2
2 1 VL

1
PR28

PC15
6.49K_0402_1%

2
2 1

2
+3VALWP

1
1

PR29
PR30 100K_0402_1%
1K_0402_1%

2
2

2 2

BATT_TEMP 37

EC_SMB_CK1 37 PH2 near main Battery CONN :

BAT. thermal protection at 79 degree C
EC_SMB_DA1 37

VL

2
@ PR31
VL 47K_0402_1%
@ PR32
47K_0402_1%

1
1 2

1
PQ7
TP0610K-T1-E3_SOT23-3
@ PH2
100K_0402_1%_NCP15W F104F03RC VL

B+
3 1 +VSBP

2
0.22U_1206_25V7K

@ PR34
0.1U_0603_25V7K
1

8
13.7K_0402_1% @ PD5
1

1
PC16

PC17

PR33 1 2 5 LL4148_LL34-2

P
100K_0402_1% +
O 7 2 1
@ @ TM_REF1 6
2

G
1
3 3

PR35 PU3B
2

1
VL 22K_0402_1% LM393DG_SO8

4
1 2 @ PC18 @ PR36
0.22U_0603_16V7K 15.4K_0402_1%

2
2

PR37
100K_0402_1%

PR38
1

0_0402_5% PQ8 D
1 2 2
45,47 SPOK G 2N7002W -T/R7_SOT323-3
0.1U_0402_16V7K

S
3
1

PC19

@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0
Date: Friday, October 23, 2009 Sheet 46 of 60
A B C D
 5 4 3 2 1

ISL6237_B+
ISL6237_B+

PR39
PJ16 0_0805_5%
2 1 1 2
D
B+ 2 1
D
JUMP_43X118

2200P_0402_50V7K

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

1
VL
2200P_0402_50V7K

2200P_0402_50V7K

4.7U_1206_25V6K

4.7U_1206_25V6K
1

5
6
7
8
PC22

PC23

PC24
1

8
7
6
5

1
PC27
2
PC20

PC21

PC25

PC26
1U_0603_10V6K
2

2
PQ10
2

2
2
PQ9 PC28 AO4466_SO8

2
@ @ AO4466_SO8 0.1U_0603_25V7K 4

4.7U_0603_6.3V6M
1
PC29
4

1
DCR=37m ohm(typ)

PC30
1
+5VALWP
40m ohm(max)

3
2
1
PL4

1
2
3
PL3 4.7UH_PCMC063T-4R7MN_5.5A_20%

7
4.7UH_PCMC063T-4R7MN_5.5A_20% PU4 PC31 2 1
1 2 1U_0603_10V6K

LDO
VIN

VCC
+3VALWP 33 TP PVCC 19 1 2 DCR=37m ohm(typ)

5
6
7
8

1
4.7_1206_5%
40m ohm(max)

8
7
6
5
DH3 DH5

PR42
26 UGATE2 UGATE1 15
PR41 PR43 PR44 2.2_0603_5% PQ12
4.7_1206_5% PQ11 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8
BOOT2 BOOT1
1

AO4712_SO8 2.2_0603_5%

63.4K_0402_1%
1

2
2

2
PR40 PC34 4

2
PC32 + PC33 0.1U_0603_25V7K

PR45
0_0402_5% 4

2
330U_D2E_6.3VM_R25M 0.1U_0603_25V7K

680P_0402_50V7K
1

1
1
LX3 25 16 LX5 1
2

2 PC35 PHASE2 PHASE1

PC36
3
2
1

2
C 680P_0402_50V7K + PC37 C

1
2
3
DL3 23 18 DL5 150U_D2E_6.3VM_R18

1
LGATE2 LGATE1
2
Rds(on)=15m ohm(typ)
2

10K_0402_1%
22
PGND 18m ohm(max)

2
FB3 30
@ PR46 OUT2

PR47
10K_0402_1% Rds(on)=15m ohm(typ) OUT1 10
VL 32
18m ohm(max)
1

REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC38 0.22U_0603_10V7K
BYP 9
8 LDOREFIN
+3.3VALWP Ipeak=7A ; Imax=4.9A @ PR48 0_0402_5%
29 2 1 VL
Choke DCRmax=40m ohm, DCRtyp=37m ohm SKIP
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) PR49 0_0402_5%
Vlimit=(5E-06 * 330K)/10=165mV 1 2
20 NC POK2 28
Ilimit=165mV/18m ~ 165mV/15m PD6 PR50
=9.167A ~ 11A GLZ5.1B_LL34-2 100K_0402_1%
1 2 1 2 4 13 SPOK 45,46
Iocp=Ilimit+Delta I/2 VS EN_LDO POK1 PR52 pull high VL=5V
2

=10.134A ~ 11.967A 330K_0402_1%

200K_0402_5%

B ILM1 B
PR51

14 12 2 1
Delta I=1.934A (Freq=300KHz) PC39 EN1 ILIM1
0.22U_0603_25V7K
1

27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2
1

NC
2

PD15 PR53
0_0402_5%

1SS355_SOD323-2 VL @ PR54
2
ISL6237IRZ-T_QFN32_5X5 330K_0402_1%

21
0_0402_5%
PR55
2
2

PR56
1

1
806K_0603_1%
1U_0603_10V6K
1

PR58 @ PR59 PR57

+5VALWP Ipeak=7A ; Imax=4.9A
2VREF_ISL6237
1

2
0_0402_5% 47K_0402_5% 0_0402_5%
PC40

2 1 1 2 Choke DCRmax=40m ohm, DCRtyp=37m ohm

2
1

Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)

0.047U_0402_16V7K

2VREF_ISL6237

18,46,49 MAINPWON
Vlimit=(5E-06 * 330K)/10=165mV
1

PC41

Ilimit=165mV/18m ~ 165mV/15m
2

=9.167A ~ 11A
1

@ PC42 Iocp=Ilimit+Delta I/2

3

0.047U_0402_16V7K
2

=10.147A ~ 11.980A
Delta I=1.96A (Freq=400KHz)
A 2 PQ13 A
TP0610K-T1-E3_SOT23-3
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0
Date: Friday, October 23, 2009 Sheet 47 of 60
5 4 3 2 1
 A B C D

Iada=0~4.74A(90W/19V=4.736A)
ADP_I = 19.9*Iadapter*Rsense
CP = 85%*Iada ; CP = 4.07A B+
Iada=0~3.42A(90W/19V=3.421A) CP = 85%*Iada ; CP = 2.91A

P2 P3 B+ CHG_B+
PQ14 AO4407A_SO8 PQ15 AO4407A_SO8 PR60 0.02_2512_1% PQ16 AO4407A_SO8
PJ17
VIN 8 1 1 8 1 4 2 2 1 1 1 8
7 2 2 7 2 7
6 3 3 6 2 3 JUMP_43X118 CSIN 3 6
5 5 5

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_25V7K
0.1U_0603_25V7K
1 1
CSIP PR61

5600P_0402_25V7K
4

4
1

1
PC44

PC45
47K_0402_1%
VIN

PC46

PC47
PQ17 TP0610K-T1-E3_SOT23-3 1 2

PC43

2
1

3 1 DCIN

1
P3

2
PR62 PD8

1
47K_0402_1% PR65 ACOFF

100K_0402_1%
0.1U_0603_25V7K
1 2

1
PR63 PQ18 10K_0402_1%

1
PC48

PR64
200K_0402_1% PDTC115EU_SOT323 1SS355_SOD323-2
2

PR67

1 1
PD9 200K_0402_1%

2
PR66 2 FSTCHG 1 2
FSTCHG 37 VIN

2
3

2 1 2 1
47K PQ19 PD10 1SS355_SOD323-2 3 SUSP#
PDTA144EU_SOT323-3 1 2 6251VDD 100K_0402_1% SUSP# 37,39,43,50 PQ20 PD11
2 BAS40CW _SOT323-3 PDTC115EU_SOT323 2 1 2

2.2U_0603_6.3V6K
47K

PC49
PR68

3
1
10K_0402_5% wrong Value 1SS355_SOD323-2
2 1 PU5 PC50
37 FSTCHG
1

0.1U_0603_25V7K

0.1U_0603_25V7K
2

1
PQ21 1 2 1 24 DCIN 2 1 PQ23D
1

VDD DCIN
1

1
PC52
PDTC115EU_SOT323 PR70 47K_0402_5% PC51 2 PACIN

100K_0402_1%
6251VDD 1 2 0.1U_0402_16V7K 2N7002W
G -T/R7_SOT323-3

PR71
2 PR69 2 23 S

3
ACSET ACPRN

1
150K_0402_1% PR72
PQ24 20_0402_5%
2

2
1

PQ22 D PDTC115EU_SOT323 6251_EN CSON

3 EN CSON 22 1 2

2
2 PC53
3

5
6
7
8
G 2N7002W -T/R7_SOT323-3 2 0.047U_0402_16V7K
37 3S/4S#
S 4 21 1 2 CSOP PQ25
3

1
CELLS CSOP PR73 AO4466_SO8
2
PC54 6800P_0402_25V7K 20_0402_5% 2

3 1 2 5 ICOMP CSIN 20 2 1
1

2
PQ26 D PR74 4
PC56 20_0402_5%
2
G 2N7002W -T/R7_SOT323-3 1 2 1 PR75 2 10K_0402_1% 6 19 0.1U_0603_25V7K
1 2 TCR=50ppm / C
<40,41>

1
PR77 VCOMP CSIP PR76 PL5
S
3

PC55 1 2 100_0402_1% 2_0402_5% 10UH_PCMB104T-100MS_6A_20% BATT+

3
2
1
ACON 0.01U_0402_25V7K PC57 1 2 7 18 LX_CHG 1 2 CHG 1 4 PR78
49 ACON ICM PHASE
@ 100P_0402_50V8J 0.02_1206_1%

4.7_1206_5%
5
6
7
8

1
37 ADP_I 2 3

PR80
PR79 PC58 6251VREF 8 17 DH_CHG
22K_0402_5% PR81 VREF UGATE PR82 PC59
1 2
PACIN 80.6K_0402_1% 0_0603_5% 0.1U_0603_25V7K

10U_1206_25V6M

10U_1206_25V6M
45,49 PACIN 1 2
2 1 0.1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1 PQ27 @

2
37 IREF CHLIM BOOT

1
PD12 4
0.01U_0402_25V7K

AO4466_SO8
1

1
PC62

PC63
PQ28 PR84

1
PC60

PDTC115EU_SOT323 PR83 6251VREF 1 6251aclim 6251VDDP

680P_0402_50V7K
2 10 ACLIM VDDP 15

PC61
100K_0402_1% RB751V-40_SOD323-2
2

2
1
2.37K_0402_1%
PR85
11.5K_0402_1% 20K_0402_1% 1 26251VDD

3
2
1

2
ACOFF 2 PR87 11 14 DL_CHG @
37,49 ACOFF
2

1 VADJ LGATE

2
PR86
4.7_0603_5%
12 13 PC64
2

1
GND PGND 4.7U_0603_6.3V6M
3

2
1

PQ29 D ISL6251AHAZ-T_QSOP24
2
37 65W/90W# G 2N7002W -T/R7_SOT323-3
S
3

3
CP mode 3

0826 PR88 18.2K change to 15.4K VMB

Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) <40,41>
CALIBRATE# = 1.899V
where Vaclm=1.502V, Iinput=4.07A PR88
15.4K_0402_1% Kv=9.451

1
1 2
37 CALIBRATE#
2

VS PR89
PR90 LI-3S :13.5V----BATT-OVP=1.5012V 340K_0402_1%
CC=0.6~4.48A 31.6K_0402_1%

2
BATT-OVP=0.1112*VMB

0.01U_0402_25V7K
IREF=0.7224*Icharge
1

Per cell=3.5V

PC65

1
IREF=0.43V~3.24V Vcell = (0.175 * Vadj) + 3.99
PR91

2
499K_0402_1%
CALIBRATE# Pre Cell

2
8
PR92 PU1B
3.3V 4.35V 10K_0402_1% LM358DT_SO8 5

P
+
1 2 7 0
37 BATT_OVP 6
-

G
1.899V 4.20V

0.01U_0402_25V7K
4

1
PR93

PC66
105K_0402_1%
Charging Voltage
BATT Type CV mode

2
(0x15)

2
4 4

Normal 3S LI-ON Cells

12600mV 12.60V

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
-
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0
Date: Friday, October 23, 2009 Sheet 48 of 60
A B C D
 5 4 3 2 1

VS

8
PU6A
3
P
+
D 1 O D
- 2
G

LM393DG_SO8
4

PR95 B+
VL 2.2M_0402_5% PR94
2 1 1K_1206_5%
1 2

TP0610K-T1-E3_SOT23-3
PR97 PQ30
PD13

1
VIN 1K_1206_5%
PR96 2 1 1 2 3 1
B+
VS 499K_0402_1%
1

PR99
PR98 LL4148_LL34-2 1K_1206_5%

2
100K_0402_1% 1 2

100K_0402_5%

100K_0402_5%
1

1
PR101
PR100
2

PR102
18,46,47 MAINPWON PD14 PU6B 1K_1206_5%

2
2 5 1 2
P

C + C
1 7 O
48 ACON 3 6

0.01U_0402_25V7K

2
-
G

1
32.4

PC69
BAS40CW _SOT323-3 LM393DG_SO8 PR103

1000P_0402_50V7K
4
1

PC68 191K_0402_1%
PC67 PR104

2
0.1U_0603_25V7K
2

PRG++ 2

1
499K_0402_1%
PR105

1
100K_0402_5%
PQ31
PDTC115EU_SOT323

1 2
PR106 1 PR107
34K_0402_1% PQ32D 47K_0402_5% 37,48 ACOFF 2
2 1 2 2 1 PQ33
RTCVREF 2N7002W
G -T/R7_SOT323-3 PACIN 45,48 PDTC115EU_SOT323

1
S
3

PQ57 2

3
1

PDTC115EU_SOT323
@ PR108
66.5K_0402_1% 2 +5VALW

3
2

ACIN
Precharge detector
Min. typ. Max.
B B
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V
BATT ONLY
Precharge detector
Min. typ. Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PRECHARGE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0
Date: Friday, October 23, 2009 Sheet 49 of 60
5 4 3 2 1
 5 4 3 2 1

@ PJ18 B+
51117_1.8V_B+ 2 1
2 1
JUMP_43X118

4.7U_0805_25V6-K

4.7U_0805_25V6-K
EN_PSV

1
PC70

PC71
1. GND=>Disable SMPS
2. FLOAT=>PWM_only mode

5
6
7
8

2
3. HIGH=>Auto_skip mode @ PQ58 @ @
AO4466_SO8

D D
@ PR109 4
280K_0402_1%
1 2
DCR=18m ohm(typ)
20m ohm(max)

3
2
1
1.8V_EN BST_1.8V

@ PR112 PL6

15

14
+1.8VSP

1
@ PU7 0_0603_5% @ PC72 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
1 2 BST_1.8V-1 1 2 LX_1.8V-1 1 2

EN/DEM

NC

BOOT
2 13 UG_1.8V 0.1U_0603_25V7K
TON UGATE

1
@ PR170
3 12 LX_1.8V 1 2
VOUT PHASE

5
6
7
8
@ PR114 1
4 11 0_0603_5% +5VALW @ PQ59 4.7_1206_5%
VDD CS

1
@
AO4712_SO8 + PC74

2
5 10 330U_6.3V_M PC218 PC219
FB VDDP 22U_0805_6.3V6M 22U_0805_6.3V6M

2
1
@ PR115 100_0603_1% LG_1.8V 2
6 9 4
open-drain PGOOD LGATE

PGND
1 2 @ PC75

GND
+5VALW
680P_0603_50V8J

2
1
7.68K_0402_1%
1
Layout Note: @ PC78 RT8209BGQW _W QFN14_3P5X3P5 @ PC76

3
2
1
1

4.7U_0805_10V6K

PR116
47P_0402_50V8J
Place near V5FILT Pin

2
@ PC77 1 2
4.7U_0603_6.3V6K VFB=0.75V
2

@
Vo=VFB*(1+PR117/PR118)=1.8V

2
Rds(on)=15m ohm(typ)
Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=4.14E-7
@ PR117 18m ohm(max) Freq=282KHz
C C
59K_0402_1% VFB=0.75V
1 2
Cesr=15m ohm
Ipeak=3.98A Imax=2.786A
1

Delta I=((19-1.8)*(1.8/19))/(L*Freq)=2.469A
@ PR118 Vtrip=Rtrip*10uA=0.0768V
41.2K_0402_1% Iocp-min=Vtrip/(Rds(on)(max)*1.2)+Delta I / 2 = 4.79A
2

Iocp-max=Vtrip/(Rds(on)(typ)*1.2)+Delta I / 2 = 5.5A
+1.5V Iocp=4.79~5.5A
@ PJ33
2 1 LX_1.8V-1
2 1

1
@ PR113 JUMP_43X118
47K_0402_5% PJ19

1
2

2 1 1.8V_EN PR110 JUMP_43X79

VFB=0.8V PR174 0_0402_5%
2

2
316K_0402_1%
@ PR171
2 1 SUSP# 37,39,43,48 PU8

2
0_0402_5% 1 6 +3VALW
1

PR173 @ PR111 VIN VCNTL

+1.8VSP 402K_0402_1% PU17 0_0402_5% 2 5
1

GND NC

1
1 2 1 FB EN/SYNC 10 2 1 VS_ON 39,51,53

1
PC79 3 7 PC80
REFEN NC

1
2 9 4.7U_0603_6.3V6M PR119 1U_0402_6.3V6K

2
PC127 .1U_0402_16V7K GND GND @ PC73 1K_0402_1% 4 VOUT NC 8
1 2 3 8 0.1U_0402_16V7K

2
SW SW
9

2
GND
+5VALW 4 IN IN 7
APL5336KAI-TRL SO8
1

B 5 6 B
BS POK
1

@ PD16 PR120

0.1U_0402_16V7K
+0.75VSP

1
PC123 PC124 12.4K_0402_1% PQ60 D
TP 11
10U_0805_10V4Z 10U_0805_10V4Z
39,43 SUSP

PC81
B340A_SMA2 1 2 2 PR121
2

1
MP2121DQ-LF-Z_QFN10_3X3 G 2N7002W -T/R7_SOT323-3
2

2
1
S PC83

3
PR120 change to 12.4K PC82 1K_0402_1% 10U_0805_6.3V6M

2
0.1U_0402_16V7K

2
PC127 change to SE076104K80

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VSP/+0.75VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0
Date: Friday, October 23, 2009 Sheet 50 of 60
5 4 3 2 1
 A B C D

@ PJ20 B+
51117_1.5V_B+ 2 1
2 1
EN_PSV
JUMP_43X118

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1. GND=>Disable SMPS
2. FLOAT=>PWM_only mode

1
3. HIGH=>Auto_skip mode

PC84

PC85
5
6
7
8

2
PQ61
1 AO4466_SO8 1

PR122 4
280K_0402_1%
1 2

3
2
1
1.5V_EN BST_1.5V

PR123 PR125 PL7

15

14
PC86
+1.5VP

1
0_0402_5% PU9 0_0603_5% 1UH_PCMB103T-1R0MS_13A_20%
1 2 1 2BST_1.5V-1 1 2 1 2

EN/DEM

NC

BOOT
1

37,43 SYSON @ PR124 1 2 TON UGATE 13 UG_1.5V 0.1U_0603_25V7K

1
47K_0402_5% @ PC87
0.1U_0402_16V7K 3 12 LX_1.5V
2

VOUT PHASE

5
6
7
8
@ PR295 1
2

4 11 +5VALW PQ62 4.7_1206_5%

VDD CS AO4456_SO8 + PC88

2
5 10 330U_D2E_2.5VM
PR296 FB VDDP

1
100_0603_1% LG_1.5V 2
6 9 4
open-drain PGOOD LGATE

PGND
1 2 @ PC89 VFB=0.75V

GND
+5VALW
680P_0603_50V8J
Vo=VFB*(1+PR298/PR299)=1.52V

2
1
11K_0402_1%
1
Layout Note: @ PC92 RT8209BGQW _W QFN14_3P5X3P5 PC90 Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=3.8E-7

3
2
1
1

4.7U_0805_10V6K

PR297
47P_0402_50V8J Freq=282KHz(min) , 300KHz(typ)
Place near V5FILT Pin

2
PC91 1 2
4.7U_0603_6.3V6K
2

Cesr=15m ohm

2
2
Rds=4.5mΩ(Typ) Ipeak=15.58A Imax=10.906A 2

PR298 5.6mΩ(Max) Delta I=((19-1.5)*(1.5/19))/(L*Freq)=4.61A

59K_0402_1% VFB=0.75V Vtrip=Rtrip*10uA=0.11V
1 2 Iocp-min=Vtrip/(Rds(on)(max)*1.2)+Delta I / 2= 18.674A
Iocp-max=Vtrip/(Rds(on)(typ)*1.2)+Delta I / 2=22.675A
1

Iocp=18.674~22.675A
PR299
57.6K_0402_1%
2

@ PJ21 B+
51117_1.05V_B+ 2 1
2 1
JUMP_43X118

4.7U_1206_25V6K

4.7U_1206_25V6K
EN_PSV
1. GND=>Disable SMPS

1
PC93

PC94
2. FLOAT=>PWM_only mode

5
6
7
8
3. HIGH=>Auto_skip mode

2
PQ63
AO4466_SO8

PR300 4
3
280K_0402_1% 3

1 2

3
2
1
1.05V_EN BST_1.05V

PR301 PR302 PL8

15

14

PC95
1

,53 VS_ON 9.76K_0402_1% PU10 0_0603_5% 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%

1 2 1 2BST_1.05V-1 1 2 1 2 +1.05VSP
EN/DEM

NC

BOOT
1

@ PR303 2 13 UG_1.05V 0.1U_0603_25V7K

TON UGATE

1
47K_0402_5% PC96
1U_0402_6.3V6K 3 12 LX_1.05V
2

VOUT PHASE
5
6
7
8
@ PR304 1
2

4 11 +5VALW 4.7_1206_5%
VDD CS + PC97 VFB=0.75V

2
5 10 330U_D2E_2.5VM
FB VDDP Vo=VFB*(1+PR308/PR309)=1.05V

1
PR305 100_0603_1% LG_1.05V 2 Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=2.74E-07
6 9 4
open-drain PGOOD LGATE
PGND

1 2 @ PC98 Freq=282KHz , 300KHz(typ)

GND

+5VALW
680P_0603_50V8J
2
1
7.32K_0402_1%
1

Layout Note: @ PC101 RT8209BGQW _W QFN14_3P5X3P5 PC99 PQ64 Cesr=15m ohm

7

3
2
1
1

4.7U_0805_10V6K
PR306

47P_0402_50V8J AO4456_SO8 Ipeak=10.9A Imax=7.63A

Place near V5FILT Pin
2

1 2
Delta I=((19-1.05)*(1.05/19))/(L*Freq)=1.837A
2

PC100 Vtrip=Rtrip*10uA=0.0732V
2

4.7U_0603_6.3V6K Rds(on)=4.5m ohm(typ) Iocp-min=Vtrip/(Rds(on)(max)*1.2)+Delta I / 2= 11.81A

@ PR307 PR308 5.6m ohm(max) Iocp-max=Vtrip/(Rds(on)(typ)*1.2)+Delta I / 2=14.47A
23.7K_0402_1% 24K_0402_1% VFB=0.75V Iocp=11.81~14.47A
2 1 1 2
4
+1.05VS 4
1

PR309
59K_0402_1%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/08/10 Deciphered Date 2009/08/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP / 1.05VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0
Date: Friday, October 23, 2009 Sheet 51 of 60
A B C D
 5 4 3 2 1

VGA@ PJ24
B+ 2 2 1 1 B+_core

JUMP_43X118
VGA_CORE
Ipeak=16A
Imax=11.2A

10U_1206_25V6M

10U_1206_25V6M
LX_VCORE

1
VGA@ PR310
14,39 VGA_PWROK Delta I / 2 = 3.33A , Freq=1/ 75E-12*PR153=230K Hz

1
PC102
DH_VCORE 1 2 DH_VCORE-1

PC103
VGA@ PR311 0_0603_5% Iocp(min)=1.1*Ipeak+Delta I / 2 = 20.93A

2
BST_VCORE
1 2 1 2

2
VGA@ 2.2_0603_5% Rsen=Iocp(min)*1.2*Rds(on)(max)/ISEN(min)=3.57K ohm
D VGA@ VGA@ PC104 D
open-drain
+5VS 0.1U_0603_25V7K ISEN(min)=19uA , Rds(on)=5.6m ohm(max) ,4.5m ohm(typ)
Iocp(max)=ISEN(min)*Rsen/(1.2*Rds(on)(typ))=25.12A

5
VGA@ PR312
0_0603_5%
Iocp=22.97~25.12A

16

15
8

1
PU15 VGA@ PR313

2
1 2 6269_VCORE 4

UG

BOOT
PHASE
GND

PGOOD
4.7_0603_5% VGA@ PQ42
+3VS 3 VIN PVCC 14 1 2VGA@ PC105
TPCA8030-H_SOP-ADV8-5
DCR=1.6m ohm

3
2
1
6269_VCORE 2.2U_0603_6.3V6K
VGA@ PL15
VGA@ PC106 4 13 DL_VCORE
2.2U_0603_6.3V6K VCC LG 0.56UH_ETQP4LR56WFC_21A_20% +VGA_COREP
2

1
1 2

5
6
7
8
@ PR314

5
6
7
8

1
10K_0402_5% 12 VGA@ PQ43 VGA@ PQ44 1

2
PGND AO4456_SO8 AO4456_SO8 VGA@ PR315

2
VGA@ PR316 4.7_1206_5% +
1

0_0402_5%
VGA@ PR148 VGA@ PC107
9,43 VGA_ON

PR149
VGA_ON 1 2 5 11 ISEN_VCORE
1 2 4 330U_6.3V_M

1 2
EN ISEN 2
4

COMP
30K_0402_1% 3.57K_0402_1% VGA@ PC206

FSET

1
1

VGA@

VO
FB
VGA@ PC108 680P_0603_50V7K 1 2

3
2
1

2
VGA@ PR150 +NVVDD_SENSE 23
2

10

3
2
1
C 0.1U_0402_16V7K VGA@ ISL6268CAZ-T_SSOP16 C
10_0402_1%

2
Rds=4.5mΩ(Typ)
5.6mΩ(Max) Material Note:
VGA@ PR151
2.4K_0402_1% 330uF/6 mΩ, number
are 3, Power 1, HW 2

1
1

1
22P_0402_50V8J
1

1
VGA@ PR152 VFB=0.6V +3VS_DELAY
PC207

PR153
2200P_0402_25V7K
22K_0402_1% VGA@ PC208
0.01U_0402_25V7K
2

2
2

2
VGA@ VGA@ VGA@ PR154

PC209
23.7K_0402_1% @ PR155
57.6K_0402_1%
10K_0402_5%
2

1 1
1
VGA@ VGA@ PR157
GPU_VID1 22

1
D VGA@ PQ45 10K_0402_1%
VGA@ PR156 2 1 2
2N7002W-T/R7_SOT323-3
G

2
6.98K_0402_1% S

1
VGA@ PR158
VGA@ PC210 10K_0402_1%
0.022U_0402_25V7K

1
+1.5V

1
B
VGA@ PR159
6.34K_0402_1%
+3VS_DELAY B
1

2
+5VS VGA@ PR160

2
@ PJ23 0824 PR159 13K(0.9V) change to 6.34K for 1.033V
1

+3VS JUMP_43X118 10K_0402_5%

@ PR161
2

4.7K_0402_5%

1
GPU_VID0 22
1

1
1 2 VGA@ PQ46 D VGA@ PR162
2

VGA@ PC211 2N7002W-T/R7_SOT323-3 2 1 2

1U_0402_6.3V6K G
2

@ PR163 S 10K_0402_1%

3
2

1
VGA@
6

10K_0402_5% PU16 VGA@ PC217 @ PR164

5 VGA@ PC212 0.022U_0402_25V7K 10K_0402_1%
VCNTL

2
VIN 4.7U_0603_6.3V6M
7
2

POK N11M
4
1

2
VGA@ PR165 VOUT

VOUT 3 +1.05VSDGPU
10K_0402_1% 1 GPU_VID0 GPU_VID1 Core Voltage Level
VGA_ON 1 2 8 2
24,39,43 VGA_ON EN FB
1

VGA@ VGA@ PC213

GND

9 VGA@ PR166 PC214 22U_0805_6.3V6M 0 0 0.8 V

2

VIN
1

1.15K_0402_1%
2

VGA@ PC216 S IC APL5913-KAC-TRL SO 8P 0.01U_0402_25V7K

1

0.1U_0402_16V7K 0 1 0.85 V
2

@ PC215
FB=0.8V 22U_1206_6.3V6M 1 0 1.03 V
A A
1

1 1 reserve
VGA@ PR167 0824 change to 3.65K for 1.05V
Vout=FB*(1+PR166/PR167) 3.65K_0402_1%
PR167=3K, Vo=1.1V
2

PR167=3.65K, Vo=1.05V Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/12/18 Deciphered Date 2008/12/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_COREP/+1.1VSDGPU
Rds=4.5mΩ(Typ)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5.6mΩ(Max)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0
Date: Friday, October 23, 2009 Sheet 52 of 60
5 4 3 2 1
 5 4 3 2 1

PJ22
2 1 6268_B+
B+ 2 1
JUMP_43X118 PR126 +3VS
0_0402_5%

10U_1206_25V6M

10U_1206_25V6M
1 2
LX_1.1VS_VTT

1
H_VTTPWRGD 5

2K_0402_1%
PC109

PC110
Layout Note: DH_1.1VS_VTT 1 PR128 2 DH_1.1VS_VTT-1

PR127
PR129 0_0603_5%
Place near high-side MOS Drain

2
BST_1.1VS_VTT
1 2 1 2
and low-side MOS Source @ PR130 0_0603_5%

2
D 1K_0402_1% PC111 D
1 2 +5VS 0.1U_0603_25V7K

5
PR131
0_0603_5% PQ34
SI7686DP-T1-E3_SO8
PR132

16

15
8

1
PU11 4.7_0603_5%

2
1 2 6268_VCORE_1.1VS_VTT 4

UG

BOOT
PHASE
GND

PGOOD
Layout Note: DCR=2.7mΩ(Typ)
3 14 1 2
VIN PVCC Close IC 3.0mΩ(Max)

3
2
1
PC112
2.2U_0603_6.3V6K
6268_VCORE_1.1VS_VTT
4 VCC 13 DL_1.1VS_VTT PL9
LG 1UH_PCMB103E-1R0MS_20A_20%
1 2 +1.1VS_VTTP

1
PC113 12 PQ35
2.2U_0603_6.3V6K PGND TPCA8028-H_SOP-ADVANCE8-5

2
PR134 @ PR133
57.6K_0402_1% 4.7_1206_5%
1 2 5 11 ISEN_1.1VS_VTT
1 2 4 4
39,50,51 VS_ON

1 2
EN ISEN
1

COMP
PR135

FSET
1
2.05K_0402_1% @ PC114 + PC116

VO
FB
@ PR136 PC115 680P_0603_50V7K 330U_D2_2V_Y

3
2
1

3
2
1

2
10K_0402_5% 0.1U_0402_16V7K ISL6268CAZ-T_SSOP16
Rds=2.3mΩ(Typ)

10
C 2 C
2

3.2mΩ(Max)
PQ36
TPCA8028-H_SOP-ADVANCE8-5

90.9K_0402_1%
1

57.6K_0402_1%
Material Note:

1
22P_0402_50V8J
Layout Note: Layout Note: 330uF/9 mΩ, number

1
單單單單單單Pin15

PR137
Close IC PC117 Close IC are 3, Power 1, HW 2

PR138
6800P_0402_25V7K
PC118
0.01U_0402_25V7K
2

2
2
1
PC119
PR139
0_0402_5%
1 2 +1.1VS_VTTP

2
PR140 PR168
4.99K_0402_1% 10_0402_1%
1 2 1 2 VTT_SENSE 7
VFB=0.6V
+3VS

180K_0402_1%
2

PR142
PR141

2
78.7K_0402_1%
1
B +3VS B
1

100K_0402_5%
PR144

1
1

D 4.7K_0402_5% @
PR143 2 2 1

PR145
6.49K_0402_1% G
S
2

1
PQ37

0.1U_0402_16V7K
2N7002W-T/R7_SOT323-3

PC120

1
2

1
2 2 1 H_VTTVID1 7
PR146

0.01U_0402_16V7K
3

PMBT2222A_SOT23-3
PQ38
+1.1VS_VTT 10K_0402_5% Voltage Select

100K_0402_5%
2
Ipeak=18.06A VID Vout

PC121
Imax=12.642A

PR147
High 1.06 V 0724 1.05V change to 1.06V
Delta I / 2 = 2.176A , Freq=230K Hz

2
Low 1.1 V

1
Iocp(min)=Ipeak + Delta I / 2 = 20.236A
Rsen=Iocp(min)*1.2*Rds(on)(max)/ISEN(min)=2.05K ohm
ISEN(min)=19uA , Rds(on)=3.2m ohm(max) ,2.3m ohm(typ)
Iocp(max)=ISEN(min)*Rsen/(1.2*Rds(on)(typ))=28.225A
Iocp=20.236~28.225A
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/4/15 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.1VS_VTTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0
Date: Friday, October 23, 2009 Sheet 53 of 60
5 4 3 2 1
 5 4 3 2 1

Intel Auburndale CPU(Integrate Graphics) Imax=15A

OCP calculation : Assume DCR=1.1m ohm
G1=Rn/(Rn+Rsum)=0.617
where Rn=PR277 // (PR274+PH3)=5.875k ohm
Rsum=PR269=3.65k ohm
LL=2*Rdroop*G1*DCR/Ri= 6.96m V/A
D D
where Rdroop=PR271=8.66k ohm, Ri=PR283=1.69k ohm
Iocp=OCP Threshold*Rdroop/LL=24.89A

B+ @ PJP3
1 2 GFX_B+

2
PAD-OPEN 4x4m

10U_1206_25V6M

10U_1206_25V6M
2200P_0402_50V7K
UMA@ PR263
@ PC188 0_0603_5% VSS_AXG_SENSE
UMA@ PC187

UMA@ PC125

UMA@ PC126

0.22U_0603_25V7K
1

1
0.1U_0402_25V6 UMA@ PR264

UMA@ PC190
+5VALW 2 1

1 1

2
1_0603_5%
2

2
UMA@ PC189
1U_0402_6.3V6K UMA@ PR265 UMA@ PC191
22.6K_0402_1% 0.22U_0402_6.3V6K

1
1
UMA@ PR292
GFXVR_IMON 8
2 1 ISUM+

5
10_0402_1% UMA@ PC192
1000P_0402_50V7K ISUM-
1 2 BST_GFX 1 2 1 2
8 VSS_AXG_SENSE
1

C UMA@ PR266 UMA@ PC193 UMA@ PQ39 C

UMA@ PC194 0_0603_5% 0.22U_0603_25V7K 4 FDMS8692 1N
8 VCC_AXG_SENSE 330P_0402_50V7K

29

10

11

12

13

14
1 2
2

9
+VGFX_COREP UMA@ PR293 UMA@ PC195
DCR=1.1 mOHM

AGND

RTN

ISUM+

VDD

VIN

IMON

BOOT
ISUM
2 1 330P_0402_50V7K

3
2
1
10_0402_1%
UMA@ PL10
7 15 DH_GFX 0.45UH_PCMB104T-R45MN_25A_20% +VGFX_COREP
VSEN UGATE
6 UMA@ PU12 16 LX_GFX 4 1
FB ISL62881HRZ-T_QFN28_4X4 PHASE

5
6
7
8

5
6
7
8
5 17 3 2
COMP VSSP

1
4 18 DL_GFX UMA@ PQ40 @ PR268 1
VW LGATE

1
UMA@ PR294 AO4456_SO8 2.2_1206_5% UMA@
UMA@ PR272 2 1 3 19 UMA@ UMA@ PR269 PR270 +
UMA@ PR271 825K_0402_1% UMA@ PC197 RBIAS VCCP PQ41 3.65K_0805_1% UMA@ PC130
47K_0402_1% 4 4 0_0402_5%

2
8.66K_0402_1% 1000P_0402_50V7K 2 20 UMA@ PR273 AO4456_SO8 330U 2V M X LESR6M SX H1.9
PGOOD VID0 2
2 1 1 2 1 2 2 1 1 2 +5VALW

2
147K for CPU 1 21 0_0603_5% UMA@ PR274 UMA@ PH3

DPRSLPVR
CLK_EN# VID1

2
UMA@ PC196 1 2 1 2
47K for GPU

3
2
1

3
2
1
1
100P_0402_50V8J +VGFX_COREP @ PC199

VR_ON
470P_0603_50V8J 2.61K_0402_1% 10K +-5% TSM0A103J4302RE 0402

VID6

VID5

VID4

VID3

VID2

1
UMA@ PC201 UMA@ PC198

2
22P_0402_50V8J 2.2U_0603_6.3V6K
2 1 2 1 1 2 2 1

28

27

26

25

24

23

22
1 2
UMA@ PR276 UMA@ PR277
Rds=4.5mOHM(typ)
1

UMA@ PC200 UMA@ PR275 8.06K_0402_1% 11K_0402_1% Material Note:

150P_0402_50V8J 17.8K_0402_1% Rds=5.6mOHM(max) Layout Note: 330uF/6 mΩ, number are 3, PW
@ PR279
10K_0402_1% Place near Choke 1 2 1, HW 1, 1 of HW is backup
2

UMA@ PC202
.1U_0402_16V7K

B GFX_CORE_PWRGD B
1 2

2
0_0402_5% 2 UMA@
1 PR280 UMA@ PC203
0_0402_5% UMA@ PR281 GFXVR_VID_0 8 .1U_0402_16V7K @ PR284
2 1
0_0402_5% UMA@ PR282 GFXVR_VID_1 8 UMA@ PR283
2 1 100_0402_1%
0_0402_5% UMA@ PR285 GFXVR_VID_2 8 UMA@ PR288 1.69K_0402_1%
2 1
0_0402_5% UMA@ PR286 GFXVR_VID_3 8 82.5_0402_1%
2 1

1
0_0402_5% UMA@ PR287 GFXVR_VID_4 8
2 1 1 2 1 2
0_0402_5% UMA@ PR289 GFXVR_VID_5 8
2 1
GFXVR_VID_6 8

2
0_0402_5% 2 UMA@
1 PR290 UMA@ PC204
0_0402_5% UMA@ PR291 GFXVR_EN 8 0.01U_0402_16V7K @ PC205
2 1
GFXVR_DPRSLPVR 8
180P 50V J NPO 0402

1
ISUM+

ISUM-

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/4/15 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GFX_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0
Date: Friday, October 23, 2009 Sheet 54 of 60
5 4 3 2 1
 8 7 6 5 4 3 2 1

PL12
+CPU_B+ FBMA-L18-453215-900LMA90T_1812
Intel Auburndale CPU(Integrate Graphics) , Ipeak = 48A
OCP calculation : Assume DCR=1.1m ohm 2 1 B+
G1=Rn/(Rn+Rsum/2)=0.763
PR210 0_0402_5% where Rn=PR258 // (PR251+PH6)=5.875k ohm

10U_1206_25V6M

10U_1206_25V6M
2200P_0402_50V7K
0.1U_0603_25V7K
H 7 CPU_VID0 1 2 Rsum=PR221, PR253 =3.65k ohm 1 H
PR211 0_0402_5%
LL = 2*Rdroop*G1*(DCR/2)/Ri = 1.81mV/A

1
+ PC122

@ PC153

PC155

PC156
7 CPU_VID1 1 2
PR212 0_0402_5% 220U_25V_M

PC154
where Rdroop=PR239=2.61k ohm , Ri=PR256=1.21k ohm
7 CPU_VID2 1 2

2
PR213 0_0402_5% Iocp= OCP Threshold*Rdroop/LL=40E-06*2.61E03/1.81E-03=57.68A 2

5
7 CPU_VID3 1 2
PR214 0_0402_5%
1 2 PQ49
7 CPU_VID4
PR215 0_0402_5% TPCA8030-H_SOP-ADV8-5 @ PQ50
1 2 TPCA8030-H_SOP-ADV8-5
7 CPU_VID5
PR216 0_0402_5% 4 4
7 CPU_VID6 1 2

PR217 PC157
2.2_0603_5% 0.22U_0603_25V7K

3
2
1

3
2
1
PR218 0_0402_5% BOOT2 2 1 BOOT2_2 1 2
1 2 PL13
37 VR_ON
UGATE2 0.36UH_PCMC104T-R36MN1R17_30A_20%
G PR219 499_0402_1% G
1 2 PHASE2 4 1 +CPU_CORE
7 H_DPRSLPVR
3 2 V2N
12 CLK_ENABLE#

10K_0402_5%
3.65K_0805_1%
1

1
PQ51
+3VS PR224 TPCA8028-H_SOP-ADVANCE8-5 PR220 PR223
1.91K_0402_1% 2.2_1206_5% 1_0402_5%

PR222
CLK_ENABLE# @ PR225

PR221
1 2
LGATE2 4 4 0_0402_5%

2
1

1 2 V1N
PR226 VGA@ PQ52
1.91K_0402_1% TPCA8028-H_SOP-ADVANCE8-5
PR227 @ PD7 VSUM+

3
2
1

3
2
1

1
0_0402_5% RB751V-40TE17_SOD323-2
2

1 2 2 1 PC158 ISEN2 VSUM-

12,15 VGATE
680P_0402_50V7K

2
Pull up 3V
@ PR228 100K_0402_5%
F F
+1.1VS_VTT 1 2

PR230 0_0402_5%
7 H_PSI# 1 2
PR229
GNDA_VCORE 1 2
147K_0402_1%
PC159
1 2 1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31

+1.1VS_VTT
PU14 1 2
PR231 68_0402_5%
CLK_EN#

VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON

5 H_PROCHOT# 1 2
30
PR232 0_0402_5% BOOT2
29
UGATE2
1 28
@ PC160 56P_0402_50V8 PGOOD PHASE2 PR234
2 27
PSI# VSSP2 0_0402_5%
1 2 3 26
H_PROCHOT#_R RBIAS LGATE2 PR235 0_0402_5%
4 25 1 2 +5VALW
PR233 4.02K_0402_1% PH5 VR_TT# VCCP
E 5 24 1 2 E
NTC PWM3
GNDA_VCORE 1 2 2 1 6 23
VW LGATE1
7 22
470KB_0402_5%_ERTJ0EV474J COMP VSSP1
8 21
GNDA_VCORE FB PHASE1
1 2 9
ISEN3
UGATE1

10 ISL62883HRZ-T_QFN40_5X5~D
BOOT1
ISUM+

ISEN2
ISEN1

ISUM-
VSEN

IMON

PC161
249K_0402_1%

8.06K_0402_1%

VDD
1000P_0402_50V7K

RTN

VIN

22P_0402_50V8J 41
AGND
1

PC163
PC162

1U_0603_10V6K
@ PR236

PR237

11
12
13
14
15
16
17
18
19
20

PR238
2

562_0402_1% PC164 GNDA_VCORE

1 2 1 2
2

390P_0402_50V7K
PR239 PR240 0_0402_5%
2.61K_0402_1% 1 2
1 2 1 2 7 IMVP_IMON
PC165 PR241 0_0402_5% +CPU_B+
D 10P_0402_50V8J 1 2 +CPU_B+ D
ISEN2
0.22U_0603_25V7K

1 2 1 2
ISEN1 PR245 1_0402_5%
PC166 PR242 1 2 +5VALW

2200P_0402_50V7K
0.22U_0402_10V6K

0.22U_0402_10V6K

150P_0402_50V8J 412K_0402_1%

10U_1206_25V6M

10U_1206_25V6M
0.1U_0603_25V7K
1

1
PC167

PC168

PC169

PC170

PC171
1U_0603_10V6K

0.22U_0603_25V7K

1
PR246

@ PC172

PC173

PC174

PC175
2

8.25K_0402_1%
BOOT1

2
5

5
Layout Note:
2

PH5 place near Phase1 L-MOS VSSSENSE PQ53

VSUM- TPCA8030-H_SOP-ADV8-5
GNDA_VCORE
VSUM+ UGATE1 4 4 @ PQ54
TPCA8030-H_SOP-ADV8-5
1 2
82.5_0402_1%

+CPU_CORE
PR249 PC176
1

C PR247 10_0402_1% 2.2_0603_5% 0.22U_0603_25V7K C

2700P_0402_50V7K

3
2
1

3
2
1
1

BOOT1_1 1
PR248

2 1 2
2.61K_0402_1%
0.22U_0603_10V7K

0.068U_0603_16V7K

PL14
PR251

0.36UH_PCMC104T-R36MN1R17_30A_20%
1

1
@ PC177

PC178

PC179

7 VCCSENSE 1 2
0.01U_0402_25V7K
2

PHASE1 4 1 +CPU_CORE
2

PR250 0_0402_5%
2

2
1

3 2 V1N
1

5
PC180

1
330P_0402_50V7K
PC181

10K_0402_5%
3.65K_0805_1%
2

1
VGA@ PQ55

PR253
2

TPCA8028-H_SOP-ADVANCE8-5 PR252 PR255

2.2_1206_5% 1_0402_5%

PR254
GNDA_VCORE
LGATE1 4 4
330P_0402_50V7K

2
1

PR256 @ PR259
11K_0402_1%

2
1

PC182 1.21K_0402_1% PH6 0_0402_5%

PC183

PR258

1000P_0402_50V7K 1 2 PQ56 1 2 V2N

PR260 0_0402_5% 10K_0402_1%_TSM0A103F34D1RZ TPCA8028-H_SOP-ADVANCE8-5
2

3
2
1

3
2
1
7 VSSSENSE 1 2 VSUM-
2

1
B VSUM+ B
Layout Note:
PC184
Place near Phase1 Choke 680P_0402_50V7K ISEN1

2
PR261 10_0402_1%
1 2 1 2 1 2 VSUM-
@ PC185 @ PR262
1200P_0402_50V7K 100_0402_1%
GNDA_VCORE
0.1U_0402_16V7K
1

PC186
2

PJP5
1 2

A
PAD-OPEN1x1m A
GNDA_VCORE GNDA_VCORE
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/4/15 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0
Date: Friday, October 23, 2009 Sheet 55 of 60
8 7 6 5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 3

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D D
Modify chager circuit design change 0.1 48 Change PR60 to SD000001F00(0.02_2512_1%) 09/06/23 EVT
1
Cahnge PR115 to SD014100080 (S RES 1/10W 100 +-1% 0603 )
Modify 1.8V V5FILT PIN Avoid 2’nd source RT8209B can no power on 0.1 50 Cahnge PC77 to SE107475K80 (S CER CAP 4.7U 6.3V K X5R 0603) 09/07/21 DVT
2
Cahnge PR296 to SD014100080 (S RES 1/10W 100 +-1% 0603 )
Modify 1.5V V5FILT PIN Avoid 2’nd source RT8209B can no power on 0.1 51 Cahnge PC91 to SE107475K80 (S CER CAP 4.7U 6.3V K X5R 0603) 09/07/21 DVT
3
Cahnge PR305 to SD014100080 (S RES 1/10W 100 +-1% 0603 )
Modify 1.05V V5FILT PIN Avoid 2’nd source RT8209B can no power on 0.1 51 Cahnge PC100 to SE107475K80 (S CER CAP 4.7U 6.3V K X5R 0603) 09/07/21 DVT
4
Cahnge PR149 to SD028000080 (S RES 1/16W 0 +-5% 0402)
Modify VGA_COREP circuit design change 0.1 52 Cahnge PR150 to SD034100A80 (S RES 1/16W 10 +-1% 0402) 09/06/23 EVT
5
Cahnge PR139 to SD028000080 (S RES 1/16W 0 +-5% 0402)
Modify +1.1VS_VTTP circuit design change 0.1 53 Cahnge PR168 to SD034100A80 (S RES 1/16W 10 +-1% 0402) 09/06/23 EVT
6
Modify OTP circuit Link right component 0.1 46 Add PH1 to SL210031F00 (S THERM_ 100K +-1% TH11-4H104FT 0603) 09/06/25 EVT
7
Modify 5V/3V circuit Delete component 0.1 47 Delete PC42 to SE076473K80 (S CER CAP .047U 16V K X7R 0402) 09/06/25 EVT
C 8 C

Change PU16, PR165, PR166, PR167, PC211, PC212,

Modify 1.1VSDGPU circuit design change 0.1 52 09/06/26 EVT
9 PC213, PC214, PC215, PC216 BOM structure to VGA@

Modify chager circuit design change 0.1 48 Change PR78 to SD012200D80(S RES 1/2W 0.02 +-1% 1206) 09/06/26 EVT
10
Cahnge PR151 to SD034240180 (S RES 1/16W 2.4K +-1% 0402)
Modify VGA_COREP circuit design change(Voltage Level) 0.1 52 Cahnge PR156 to SD000002680 (S RES 1/16W 6.98K +-1% 0402) 09/06/30 EVT
11
Cahnge PR154 to SD034237280 (S RES 1/16W 23.7K +-1% 0402)
Modify VGA_COREP circuit design change(Voltage Level) 0.1 52 Cahnge PR159 to SD034130280 (S RES 1/16W 13K +-1% 0402) 09/06/30 EVT
12
Cahnge PQ6 to SB000006800 (S TR 2N7002W T/R7 1N SOT-323)
09/07/13
Modify OTP circuit design change 0.2 46 Add PR169 to SD034100480 (S RES 1/16W 1M +-1% 0402) DVT
13
Change PL7 to SH000009U00(S COIL 1UH +-20% 09/07/20
Modify 1.5VP circuit design change 0.2 51 DVT
14 FDUE1040D-1R0M=P3 21.3A)

09/07/20
Modify VGA_COREP circuit design change 0.2 52 Cahnge PR153 to SD034576280 (S RES 1/16W 57.6K +-1% 0402) DVT
15
B B
Cahnge PQ35 to SB00000GL00 (S TR TPCA8028-H 1N SOP ADVANCE)
09/07/20
Modify +1.1VS_VTTP circuit design change 0.2 53 Cahnge PQ36 to SB00000GL00 (S TR TPCA8028-H 1N SOP ADVANCE) DVT
16
Cahnge PC107 to SF000002000 (S ELE CAP 330U 6.3V M 6.3X5.9 LESR15M VU) 09/07/20
Modify VGA_COREP circuit design change 0.2 52 DVT
17
Cahnge PC74 to SF000002000 (S ELE CAP 330U 6.3V M 6.3X5.9 LESR15M VU) 09/07/20
Modify 1.8V circuit design change 0.2 50 DVT
18 and BOM structure to @

Modify CPU circuit design change 0.2 55 Cahnge PR226 to SD000009O80 (S RES 1/16W 1.91K +-1% 0402) 09/07/20 DVT
19
Modify +1.1VS_VTTP circuit design change 0.2 53 Cahnge PC116 to SGA20331E10 (S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9) 09/07/21 DVT
20
Modify CPU circuit design change 0.2 55 Cahnge PC179 to SE026683K80 (S CER CAP .068U 16V K X7R 0603) 09/07/22 DVT
21
Cahnge PC53 to SE076473K80 (S CER CAP .047U 16V K X7R 0402)
Modify chager circuit design change 0.2 48 Cahnge PC64 to SE107475M80 (S CER CAP 4.7U 6.3V M X5R 0603 H0.8) 09/07/22 DVT
22
A Cahnge PC212 to SE107475M80 (S CER CAP 4.7U 6.3V M X5R 0603 H0.8) A
Modify 1.1VSDGPU circuit design change 0.2 52 09/07/22 DVT
23

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
PIR (PWR)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 23, 2009 Sheet 56 of 60
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 2 of 3

Item Fixed Issue Reason for change Rev. PG# Modify List
for PWR Date Phase

D D
Modify GFX_COREP circuit design change 0.2 54 Cahnge PC189 to SE000000K80 (S CER CAP 1U 6.3V K X5R 0402) 09/07/22 DVT
24
Add PR170 to SD013000080 (S RES 1/10W 0 +-5% 0603)and BOM structure to @
Modify 1.8V circuit design change 0.2 50 Change PR109, PR117, PC72, PQ58, PQ59 BOM structure to @ 09/07/28 DVT
25
Add PU17 to SA00003KL00(S IC MP2121DQ-LF-Z QFN 10P PWM)
Modify 1.8V circuit design change 0.2 50 Add PD16 to SCS00001I80(S SCH DIO B340A SMA VISHAY) BOM structure to @ 09/07/28 DVT
26 Add PR173 to SD034402380(S RES 1/16W 402K +-1% 0402)
Add PR174 to SD034316380(S RES 1/16W 316K +-1% 0402)
Modify 1.8V circuit design change 0.2 50 Add PR171 to SD028000080(S RES 1/16W 0 +-5% 0402)BOM structure to @ 09/07/28 DVT
27 Add PR113 to SD028470280(S RES 1/16W 47K +-5% 0402)
Add PC123,PC124 to SE053106Z80(S CER CAP 10U 10V Z Y5V 0805)
Modify 1.8V circuit design change 0.2 50 09/07/28 DVT
28 Add PC127 to SE076103K80(S CER CAP .01U 16V K X7R 0402)
Add PC218, PC219 to SE000000I10(S CER CAP 22UF 6.3V M X5R 0805 H1.25)
Modify 1.8V circuit design change 0.2 50 09/07/28 DVT
29 Add PR41, PR42 to SD001470B80(S RES 1/4W 4.7 +-5% 1206)
add snubber(PR42 PC36),(PR41 PC35) Add PC35, PC36 to SE074681K80(S CER CAP 680P 50V K X7R 0402)
Modify 5V/3V circuit add boost PR43, PR44 0.2 47 09/07/28 DVT
Add PR43, PR44 to SD013220B80(S RES 1/10W 2.2 +-5% 0603)
30
Add PR311 to SD013220B80(S RES 1/10W 2.2 +-5% 0603)and BOM structure to VGA@
add snubber(PR315 PC206) Change PR315 PC206 BOM structure to VGA@
Modify VGA_COREP circuit 0.2 52 09/07/28 DVT
C 31 add boost PR311 C

Add PR220, PR252 to SD011220B80(S RES 1/4W 2.2 +-5% 1206)

add snubber(PR220 PC158),(PR252 PC184)
Modify CPU circuit 0.2 55 Add PC158, PC184 to SE074681K80(S CER CAP 680P 50V K X7R 0402) 09/07/28 DVT
32 add boost PR217, PR249
Add PR217, PR249 to SD013220B80(S RES 1/10W 2.2 +-5% 0603)
Cahnge PR141 to SD034787280(S RES 1/16W 78.7K +-1% 0402)
Modify +1.1VS_VTTP circuit design change 0.2 53 09/07/28 DVT
33 Cahnge PR143 to SD034649180(S RES 1/16W 6.49K +-1% 0402)

Cahnge PH1 to SL200000U00(S THERM_ 100K +-1% TSM0B104F4251RZ 0402)

Modify OTP circuit design change 0.2 46 09/07/28 DVT
34 Cahnge PH2 to SL200000U00(S THERM_ 100K +-1% TSM0B104F4251RZ 0402)

Cahnge PR135 to SD034280180(S RES 1/16W 2.8K +-1% 0402)

Modify +1.1VS_VTTP circuit design change(OCP) 0.2 53 09/07/29 DVT
35
36 Modify GFX_COREP circuit design change 0.2 54 Cahnge PH3 to SL200000Y00(10K +-5% TSM0A103J4302RE 0402) 09/07/29 DVT

37 Modify CPU circuit design change 0.2 55 Cahnge PH6 to SL200000W00(10K +-1% TSM0A103F34D1RZ 0402) 09/07/29 DVT

38 Modify 1.5V circuit Change to 3mm height choke for thermal issue 0.2 51 Cahnge PL7 to SH00000AB00(S COIL 1UH +-20% PCMB103T-1R0MS 13A) 09/08/06 DVT
B B
design change Cahnge PR159 to SD034634180(S RES 1/16W 6.34K +-1% 0402)
39 Modify VGA_COREP circuit (GS sample define 1.03V,+1.05VSDGPU Vo=1.05V) 0.3 52
Cahnge PR167 to SD034365180(S RES 1/16W 3.65K +-1% 0402)
09/08/24 PVT

40 Modify 1.8V circuit design change 0.3 50 Cahnge PC127 to SE076104K80(S CER CAP .1U 16V K X7R 0402) 09/08/24 PVT

Cahnge PR88 to SD034154280(S RES 1/16W 15.4K +-1% 0402)

Modify chager circuit design change 0.3 48 09/08/26 PVT
41 Change PR81 to SD034154380(S RES 1/16W 154K +-1% 0402)

Change PR160 BOM structure to VGA@

Modify VGA_COREP circuit design change 0.3 52 09/09/03 PVT
42 VID pull high voltage change to +3VS_DELAY

Change PR130 BOM structure to @

Modify +1.1VS_VTTP circuit design change 0.3 53 09/09/03 PVT
43
Modify 0.75V circuit design change 0.3 50 Cahnge PR120 to SD034280180(S RES 1/16W 2.8K +-1% 0402) 09/09/11 PVT
44
Cahnge PR316 to SD034300280(S RES 1/16W 30K +-1% 0402)
Modify VGA_COREP circuit design change 0.3 52 09/09/11 PVT
45 Change PR164 BOM structure to @

A A
Modify +1.1VS_VTTP circuit design change 0.3 53 Cahnge PR135 to SD034205180(S RES 1/16W 2.05K +-1% 0402)
46

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
PIR (PWR)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 23, 2009 Sheet 57 of 60
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 3 of 3

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D Change PR23 to SD00000AJ80(S RES 1/16W 12.4K +-1% 0402) D

Modify OTP circuit design change 0.3 46 Change PR26 to SD034158280(S RES 1/16W 15.8K +-1% 0402) 09/09/14 PVT
47
Change PL6 to SH000009Q00(S COIL 2.2UH 20%
Modify 1.8V circuit design change 0.3 50 MSCDRI-74A-2R2M-E 6.5A) 09/09/16 PVT
48
Change PU4 to SA00001TN00(S IC ISL6237IRZ-T QFN 32P)
Modify 5V/3V circuit design change 0.3 47 09/09/16 PVT
49
Change PR120 to SD00000AJ80(S RES 1/16W 12.4K +-1% 0402)
Modify 0.75V circuit design change 0.3 50 09/10/08 PVT
50

51

52

53

C 54 C

55

56

57

58

59

60

61
B B

62

63

64

65

66

67

68
A A

69

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
PIR (PWR)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 23, 2009 Sheet 58 of 60
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 3

for HW
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D
R72 bom structure D

1 4 7/23 0.2

2 5 reserve R735 7/23 0.2

3 8 rename CPU VDDQ from +1.5V to +1.5V_CPU 7/23 0.2

4 8 R146 BOM structure 7/23 0.2

5 11 reserve S3 power consumptiosn circuit 7/23 0.2

6 12 change Y1 Y4 Y6 footprint 7/23 0.2

7 13 add ME_EN# from EC to PCH 7/23 0.2

C 8 14 pop Y6,C254,C255 , and project ID pin 7/23 0.2 C

9 17 change USB port 8 to port 1 , port 2 to port 8 7/23 0.2

10 18 GPIO35 pin(VGa presetnt) modfiy 7/23 0.2

11 19 R605 and R628 BOM structure modify 7/23 0.2

12 22 add VGA thermal sensor from EC to VGA 7/23 0.2

13 23 pop R479,del R491 7/23 0.2

14 29 L29~L34 change from 0805 to 0603 7/23 0.2

15 30 Q45,Q47 gate voltage change from +3VS to +3VS_delay 7/23 0.2

B B

16 37 change R306 to 8.2K, add D29, rename EC_MUTE 7/23 0.2

17 38 Jfun1 pin3 change form KSO1 to KSO3 7/23 0.2

18 39 del SW2 7/23 0.2

19 41 change R333, R336 to 39k,15k, add R681,C707 7/23 0.2

20 43 reserve Q58,Q59,R728,R326, change U26,R688 7/23 0.2

21 24 reserve C710 7/23 0.2

22 28 reserve U44,U45 7/23 0.2

A A

23 19 update L7,L8,L10,L11 footprint 7/23 0.2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/07/01 Deciphered Date 2009/12/31 Title
PIR (HW)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 59 of 60
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 2 of 3

for HW
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D
pop R248, R271,R265 D

1 30 7/23 0.2

2 7 pop C165, del C170 7/23 0.2

3 18 unpop R532, R86 7/23 0.2

4 5 add R472 and C713 8/31 0.3

5 11 add C714 8/31 0.3

6 12 add C715 8/31 0.3

7 17 USB20 port 6 change to USB20 port 9 8/31 0.3

C 8 24 3VS_delay related circuit 8/31 0.3 C

9 30 del R236,C257 , pop R254,C268 in all sku 8/31 0.3

10 33 unpop R3 , U1, pop R6 , change R306 to 18K 8/31 0.3

11 37 ME_EN change from U25,75 to U25.16 8/31 0.3

12 29 pop Q6,Q7 in all sku 8/31 0.3

13 29 change L29~L34 footprint 8/31 0.3

14 41 del D25,D26,D27 8/31 0.3

15 43 update C705,C706 BOM structure 8/31 0.3

B B

16 14 unpop R112 8/31 0.3

17 7 change C165 p/n 8/31 0.3

18 40 pop C353 9/10 0.3

19 change R157,R527,R570,R575,R582,R634,R239,R64 to 0 ohm 0.3

20 5 add R746,R747 9/10 0.3

21 12 U27 clk gen change to siligo 9/10 0.3

22 40 del C371,C372 9/10 0.3

A A

23 3 Modify BOM Config add S3@ on all SKU 10/20 1.0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/07/01 Deciphered Date 2009/12/31 Title
PIR (HW)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 60 of 60
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 3 of 3

for HW
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D
Change R209,C254,C255,Y6 BOM config to UMA@ D

1 14 10/20 1.0

2 19 Added C257 10/20 1.0

3 22 Change N11 to A2 (P/N SA00003HZ10) 10/20 1.0

4 22 Added R748 and R749 as I2C pull high resistor. 10/20 1.0

5 22 Pop R36,R37 as DIS@ 10/20 1.0

6 28 Change Q11,Q19 BOM config to SG@ 10/20 1.0

7 28 Change R502,R484 BOM config to DIS only@ 10/20 1.0

C 8 37 Change R306 to 33k(Board ID) 10/20 1.0 C

9 38 Change LED9 PN to SC5191UD00 10/20 1.0

10 43 Change R296 to 47K,R295 to 470 10/20 1.0

11 44 Change LED Resistors: 10/20 1.0

12 R373 to 243,R381 and R383 to 100,R377 to 243,

13 R375 and R376 to 470,R349 to 100,R350 to 191

14 R304 to 499 1.0

15 17 Change C256 to 22u 10/22

B B

16 18 ADD R750 10K pull hig resistor 10/22 1.0

17

18

19

20

21

22
A A

23

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/07/01 Deciphered Date 2009/12/31 Title
PIR (HW)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 60 of 60
5 4 3 2 1
www.s-manuals.com