Electronic Devices Final Exam Formula Sheet Daniel Townsend

MOSFETs Large Signal and DC Response

F F m A
ox = 3.9o = 3.9 × 8.854 · 10−12 ' 3.45 · 10−11 Units: tox = m Cox = µ= k=
m m2 V·s V2

d
NMOS PMOS
             
W W ox W W W ox W
kn = kn0 = (µn Cox ) = (µn ) kp = kp0 = (µp Cox ) = (µp )
L L tox L L L tox L

n
1 1 1 1
2
(VOV ) = (VGS − Vtn )2
rDS = = (|VOV |)2 = (VSG − |Vtp |)2 rDS = =
gDS kn vOV gDS kp |vOV |
Cut-off (vGS < Vtn ) Cut-off (vSG < |Vtp |)
iD = 0 iD = 0

nse
Tri. Region
 (vGS > Vtn ) & (vGD > Vtn = vDS < vOV ) Tri. Region
 (vSG > |Vtp |) & (vDG > |Vtp | = vSD < |vOV |)
1 1
iD = kn vOV − vDS vDS iD = kp |vOV | − vSD vSD
2 2
Sat. Region (vGS > Vtn ) & (vGD ≤ Vtn = vDS ≥ vOV ) Sat. Region (vSG > |Vtp |) & (vDG ≤ |Vtp | = vSD ≥ |vOV |)
1 1
iD = kn (VOV )2 · (1 + λvDS ) iD = kp (|VOV |)2 · (1 + |λ|vSD )
2 2
2
Note: Do not forget the in the saturation equation!

MOSFETs Small Signal Response (linear region of saturation mode)

NMOS PMOS
gm =
id
vgs
= kn VOV

D ow
ro =
VA
ID
=
1
λID
gm =
id
vgs
= kp |VOV |

gm vgs
ro =
|VA |
ID
=
1
|λ|ID
lT
G gm vgs ro G ro
+ +
vgs 1
vgs gm
−
−

S S
Hybrid-π model T-Model
BJTs Large Signal and DC Response
nie

vBE
iC = IS e VT iC = αiE = βib iE β Area For NPN change
iB = α= IS ∝
β+1 β+1 Base Width vBE to vEB

Symbol Cut-off Active Saturation

C C C
C
+
B βIB − 0.2V
DC Equivalent Circuits
NPN

B
+
−

+
−

B B
Da

E 0.7V 0.7V
E E E
VBE < 0 & VCB < 0 VCE > .7V iC < βiB
E E E
E
−
+

−
+

B B
0.7V 0.7V
PNP

B βIB
+
B − 0.2V

C
C C C
VEB < 0 & VBC < 0 VEC > .7V iC < βiB
Electronic Devices Final Exam Formula Sheet Daniel Townsend
BJTs Small Signal Response (linear region of active mode)

IC VT VT |VA | α β
gm = rπ = re = ro = re = rπ = rπ = (β + 1)re
VT IB IE IC gm gm

d
C C

n
gm vbe

ro gm vbe B ro
+
vbe re

nse
rπ
−
B + −
vbe
E E
Hybrid-π Model T-Model
Amplifier Design

vin 
vo 
Rsig Rin = Av o =
iin vin RL =∞
+ +
vsig
+
− Rin
−
vin gm vin

ow
Ro
−
vo RL

Diode Bias Models

Ro =

vtest 
itest vi =0
or make an equivalent
resistance excluding RL
Av =

Gv =
vo
vi
vo
vsig

Ideal Diode Model Exponential Model Exponential Model, iterative analysis

lT
Assume V1 = .7V, I1 = 1mA
VD VD R I
+ − ID = IS e nVT
P N
Symbol ID +
+
Constant Voltage Drop Model VDD − V
P N −
Foward ID > 0
VD = .7V
VDD − Vk
Ik+1 =
nie

P N R
Reverse + VD < 0 −
+
−

P N 
Ik+1

.7V Vk+1 − Vk = (2.3)(n)(VT ) log
Ik

Small Signal Model

 
VD +vd VD vd vd vd ID vd nVT
iD = IS e nVT
= IS e nVT
e nVT
= ID e nVT
' ID 1 + ∴ id = ∴ rd =
nVT nVT ID

Zener Diodes Line / Load Regulation

Da

IZ IZ Small Signal Zener Shunt Regulator

+ + + Line Regulation Line Regulation

VZO −
   
∆Vo  rd total  mV ∆Vo  rZ  mV
VZ VZO + rZ IZ =
  =
 
∆V + RS + rd total  V ∆V + RS + rZ  V

− rZ Load Regulation Load Regulation

−

∆Vo mV ∆Vo mV
VZ = Nominal Voltage = |rd total | = |rZ |
∆IL mA ∆IL mA