library ieee;

use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;

entity problema3 is
port (clck: in std_logic; u: buffer std_logic_vector(3 downto 0); d: buffer
std_logic_vector(3 downto 0); c: buffer std_logic_vector(3 downto 0); enable: in
std_logic; reset: in std_logic);
end problema3;

architecture solucion of problema3 is

begin

process (reset,clck)
begin
if reset='1' then
u<="0000"; d<="0000";c<="0000";
else if rising_edge (clck) then
if enable='1' then
u<=u+1;
if u="1010" then
u<="0000";
d<=d+1;
if d="1010" then
d<="0000";
c<=c+1;
if c="1010" then
c<="0000";
end if;
end if;
end if;
end if;
end if;

end if;
end process;

end solucion;