Professional Documents
Culture Documents
12-1 微波電路講義
12.1 Two-port power gains
Zs
+ transistor +
[S] s L
Vs V1 V2 ZL
- (Zo) -
in out
s in, Pin, Zin out L, PL, ZL
PL
power gain G (S , L )
Pin
Pavn
available power gain GA (S , S )
Pavs
PL
transducer power gain GT (S , S , L )
Pavs
Pin (in ), Pavs ( s ) Pin in *S
, PL ( L ), Pavn (out ) PL L *out
12-2 微波電路講義
Discussion
1. Z in
V1 V s V1 V1 V1 (1 Γin ),
Z s Z in
Z in Z o Zs Zo
Γin , Γs
Z in Z o Zs Zo
Vs Z in V s 1 Γs
V1
1 Γin Z s Z in 2 1 Γ s Γin
2
2 2
2 1 V1 2 Vs 1 Γs 2
Pin Ps (1 Γin ) (1 Γin ) 2
(1 Γin )
2 Zo 8Z o 1 Γ s Γin
Vs 1 s
2. V2 S21V1 S22V2 ,V2 LV2 ,V1
2 1 s in
Vs S 21 (1 s )
V2
2 (1 S 22 L )(1 s in )
2
S 21 1 s
2 2 2
1 V2 Vs
PL Pout (1 L ) (1 L ) (1 L )
2 2 2
2 Zo 8Z o 1 S 22 L 2 1 s in 2
12-3 微波電路講義
1 s
2 2
Vs
3. Pavs Pin in *S
8Z o 1 s 2
S 21 1 s (1 out )
2 2 2 2
Vs S12 S 21 L
Pavn PL , in S11
L *out
8 Z o 1 S * 2
1 s in
2
1 S 22 L
22 out
S 21 1 s
2 2 2
Vs
Pavn
8Z o 1 S11 s 2 (1 out 2 )
S 21 (1 L )
2 2
PL
4. G ( S , L )
Pin (1 in 2 ) 1 S 22 L 2
S 21 (1 s )
2 2
P
GA ( S , s ) avn
Pavs (1 out 2 ) 1 S11 s 2
S (1 s )(1 L )
2 2 2
P
GT ( S , s , L ) L 21 21 , if s L 0)
2
( S
1 s in 1 S22 L
2 2
Pavs
12-4 微波電路講義
5.
input output
Zo transistor
matching matching Zo
[S]
circuit Gs circuit GL
Go
s in out L
1 s 1 L
2 2
GT Gs GoGL
2
S21
1 s in 1 S 22 L
2 2
1 L
2
1
in *s , out *L GT max
2
S21
1 s 1 S 22 L
2 2
1 s 1 L
2 2
1 1
s S11* , L S 22 GTU max selection of transistor
* 2
S 21
1 S11 1 S22
2 2
微波電路講義
12-5
6. Ex.12.1 A Si BJT@1GHz
S 11 0.38 158, S 12 0.1154, S 21 3.580, S 22 0.4 43
Zs=25, ZL=40, Zo=50
Z Zo Z Zo
s s 0.333, L L 0.111
Z s Zo Z L Zo
S S
in S11 12 21 L 0.365 152
1 S 22 L
S S
out S 22 12 21 s 0.545 43
1 S11 s
G 13.1, GA 19.8, GT 12.6
P P P P
GT L L G , GA avn L GT
Pavs Pin Pavs Pavs
12-6 微波電路講義
7. conjugate match using FET equivalent circuit (S12=0, or Cgd=0)
Ri jX
Ri
+
Vs Rds Cds jB Rds
Vgs Cgs gmVgs
-
s in out L
1
Z in Z S* X , Z out Z L* wCds B
wCgs
Vs 1
Vgs
2 Ri jwC gs
1 1
( g mVgs ) 2 Rds
PL 2 2 g m2 Rds Rds fT 2 gm
GTU ( ) : 6 dB / octave, f
2C gs
2 2 T
Pavs 1 1 2 4 w R C 4 R f
( Vs ) / Ri i gs i
2 2
12-7 微波電路講義
12.2 Stability (S, f)
unconditional stable Z s ,Z L in 1, out 1
conditional stable Z s ,Z L in 1, out 1
Discussion
1. S 12 0, Γin 1, Γout 1 S 11 1, S 22 1
2. S12 S21 L
in S11 1 output stability circle L CL RL
1 S 22 L
( S 22 S11
* *
) S12 S21
CL , RL
S 22 S 22
2 2 2 2
S12 S21 s
out S 22 1 input stability circle s Cs Rs
1 S11 s
( S11 S 22
* *
) S12 S21
Cs , Rs
S11 S11
2 2 2 2
(derivation in p.565)
12-8 微波電路講義
3. conditional stable
|S11|<1 |S11|>1
L-plane |in|=1 L-plane
output
stability
CL RL circle
L =0
|in|<1
RL
Rs
Cs CL
|S22|<1 |S11|<1
CS RS >1 CL RL >1
Cs CL
Rs RL
12-11 微波電路講義
12.3 Single-stage transistor amplifier design
2 4 C2
2 2
S S B B
*s in S11 12 21 L L
2
1 S22 L 2C2
B1 B12 4 C1
2
S12 S 21 s
*L out S22 s
1 S11 s 2C1
B1 1 S11 S 22 , B2 1 S 22 S11
2 2 2 2 2 2
C1 S11 S22
*
, C2 S 22 S11*
(derivation in p. 571 and 572)
12-12 微波電路講義
Discussion
1. linear amplifier design procedure
if |<1, K>1 then uses input and output simultaneously conjugate
matches for GTmax
if K<1 then draws input and output stability circles to see if input
and output simultaneously conjugate matches possible, otherwise
selects proper s and L for gain or noise figure considerations.
2. S 0 S * , S *
12 s 11 L 22
1 1
GTU max Gs max S 21 GL max
2 2
S 21
1 S11 1 S 22
2 2
12-13 微波電路講義
s* 0.872 123
G
1 L* 0.876 61
s* L*
1. y=1-j3.5
2. y=j3.5
2
0.12 0.206
GT
12-14 微波電路講義
• constant gain circle (S12=0, unilateral assumption)
1 s 1 L
2 2
1 s 1 L
2 2
1 1
Gs , Gs max , GL , GL max
1 S11 s 1 S11 1 S22 L 1 S22
2 2 2 2
Gs
gs constant gain circle in S -plane S CS RS
Gs max
GL
gL constant gain circle in L -plane L CL RL
GL max
1 g s (1 S11 )
2
g s S11*
Cs , Rs
1 (1 g s ) S11 1 (1 g s ) S11
2 2
1 g L (1 S22 )
* 2
g L S 22
CL , RL
1 (1 g L ) S 22 1 (1 g L ) S22
2 2
Gs 1
gs 1 S11 1 g s S11 ,
2 2
Gs max Gs max
GL 1
gL 1 S 22 1 g L S 22
2 2
GL max GL max
GS=0dB GL= 0dB
constant gain circles S Cs Rs , L CL RL
(1 S11 ) S11* 1 g s (1 S11 ) S11 (1 S11 )
2 2 2
g s S11* S11* S11
Cs , Rs
1 (1 g s ) S11 1 S11 1 S11 1 (1 g s ) S11 1 S11 1 S11
2 4 2 2 4 2
(1 S22 ) S22 1 g L (1 S 22 ) S 22 (1 S 22 )
* *2 * 2 2
g L S 22 S 22 S 22
CL , RL
1 (1 g L ) S 22 1 S 22 1 S 22 1 (1 g L ) S 22 1 S 22 1 S 22
2 4 2 2 4 2
Cs Rs , CL RL S L 0
12-16 微波電路講義
2. Centers of constant gain circles are distributed along the lines from
S11* and S22* to the Smith chart center, respectively.
S11* ,GS max *
S22 , GL max
g s S11* *
g L S22
Cs , CL
1 (1 g s ) S11 1 (1 g L ) S22
2 2
g s 1, g L 1 Cs ,1 S11* , CL ,1 S 22
*
S11* *
S22
Gs 1, GL 1 Cs ,2 , CL ,2 GS=0dB GL= 0dB
1 S11 1 S22
2 2
1 GT 1
2.
(1 U ) 2 GTU (1 U ) 2
S11 S 21 S12 S 22
U unilaterial figure of merit
(1 S11 )(1 S 22 )
2 2
12-17 微波電路講義
3. Ex.12.4 design an amplifier with GT=11dB @ 4GHz
S11 0.75 120, S12 0, S21 2.580, S22 0.6 70
GTU max 3.6 8 1.9 13.5dB
choose GTU 2 8 1 11dB
2 GT
1
*s *L 0.1 0.432
-RL
s* L*
f
frequency response (p.579, Fig.12.8)
12-18 微波電路講義
• constant noise figure circle
for a two-port amplifier
2
RN 2 4 RN s opt
F Fmin Ys Yopt Fmin 2
Gs Z o (1 2 ) 1
s opt
12-19 微波電路講義
Discussion
1. Ex.12.5 design a LNA with F=2dB and max. gain @ 4GHz
S11 0.6 60, S12 0.0526, S21 1.981, S22 0.5 60
Fmin 1.6dB, opt 0.62100, RN 20
U 0.059
1 GT 1
0.89 1.13,0.5dB GT GTU 0.53dB
(1 U ) 2
GTU (1 U ) 2
1 S 22
2
s 0.226 0.25
L
F=2dB Gs=1.7dB
L* 0.144 0.136
s*
s* L* 微波電路講義
12-20
2. Approach for single-stage linear amplifier design
Given transistor S-parameters
Design input and output matching Design input and output matching
circuits by properly selecting circuits
ΓS and ΓL based on constant gain
circle consideration
12-21 微波電路講義
3. Two approaches for multi-stage amplifier design
(1)
Zo Zo Zo Zo
(2)
Zo Zo
Zout Zin
12-22 微波電路講義
12.4 Broadband transistor amplifier design
• Balanced amplifier
a1 a1 A b2 A
b1 b1 A a2 A
S A
a1 B b2 B b2
b1 B a2B a2
S B
12-23 微波電路講義
Discussion
1. Derivation of S-parameters 1 2 b
a1 1A
1 j 1 j b1 a1 A
0 2 2
0 ú 0 2 2
0 ú
ú ú b1B
1 j ú b1 1 j ú a1 4
2 0 0 ú
2 ú a1 A ú 2
0 0 ú
2 ú b1 A ú 3 a1B
90 hybrid
o
ú, ú
j ú
1 ú a1B j 1 ú b1B ú
2 0 0 ú 0 0 ú
2ú 2 2ú 0
ú ú
0 j ú 0 j
0 ú
1 1
0
2 2 ú 2 2 ú
1 j
0 2 2
0 ú
b2 A 1 2
ú
a2 A 1 j ú b2 A a2 A
S12 A, B a1 A, B ú 2 ú
0 0
b1 A, B S11 A, B 2ú 0 ú b2 B
b ú S ú ú , ú ú a2
2 A, B 21 A, B S22 A, B a2 A, B b2 ú j 1 ú a2 ú a2 B
ú 0 0 ú 4 3 b2
a2 B ú 2 2 ú b2 B ú
ú
0 j
0 ú
1
2 2 ú
12-24 微波電路講義
1 j
b1 b1 A b1B
2 2
1 j
( S11Aa1 A S12 Aa2 A ) ( S11B a1B S12B a2 B )
2 2
1 1 j j j 1
( S11A a1 S12 A a2 ) ( S11B a1 S12B a2 )
2 2 2 2 2 2
1 j
( S11A S11B )a1 ( S12 A S12B )a2
2 2
j 1
b2 b2 A b2 B
2 2
j 1
( S21Aa1 A S22 Aa2 A ) ( S21B a1B S22B a2 B )
2 2
j 1 j 1 j 1
( S21A a1 S22 A a2 ) ( S21B a1 S22B a2 )
2 2 2 2 2 2
j 1
( S21A S21B )a1 ( S22 A S22B )a2
2 2
12-25 微波電路講義
2. amplifier A=amplifier B, good i/p and o/p match
good stability
0 jS12 A
jS ú
21A 0
12-26 微波電路講義
8. Power amplifier application
1/2W 1/4W 1W
1/4W 1W
6dB
1/4W 1W 2W
6dB
FET equivalent
circuit
drain line
gate line
12-28 微波電路講義
ld
Io
gm Vc1
lg
+
Vi +
-
Vc1
- Lg
Discussion Zg
C g C gs / lg
1. unit cell of gate line
jwC gs / lg
g jwLg ( jwC g )
1 jwRi C gs
Lg
G=1/Rilg small loss w2 Ri Z g C gs2 C gs
Cg jw Lg (C g )
jB=jwCgs/lg wRi C gs 1 2lg lg
g j g
12-29 微波電路講義
(derivation of 1)
Lg
jwC gs / lg G=1/Rilg
Z jwLg , Y jwC g
1 jwRi C gs Cg
jB=jwCgs/lg
Z small loss Lg
Zg
Y wRi C gs 1 C g C gs / lg
jwC gs / lg wRi C gs 1
jwC gs (1 jwRiC gs )
g ZY jwLg ( jwC g ) jwLg [ jwC g ]
1 jwRi Cgs lg
C gs ( jw)3 Lg Ri C gs2
( jw) Lg (C g
2
)
lg lg
1 1 1
1
( a b ) 2 a 2 a 2 b 3 2
2 Cgs
1 ( jw) Lg Ri C gs / lg
( jw) Lg (Cg
2
)
lg 2 jw Lg (C g C gs / lg )
12-30 微波電路講義
2. unit cell of drain line Ld
Zd
Cd Cds / ld
Ld
1 C
d jwLd [ jw(Cd ds )]
Rds ld ld
Cd G= jB = small loss Zd C
jw Ld (Cd ds )
1/Rdsld jwCds/ld Id 2 Rds ld ld
d jd
3. o/p current
1 N 1
I o I dn e ( N n ) d ld , I dn g mVcn ,Vcn Vi e
( n 1) g lg
( )
2 n 1 1 jwRi Cgs
N l
g mVi N d ld g lg N n ( g lg d ld ) g mVi e g g e N d ld
Io e e e
2 n 1 2 e g lg e d ld
12-31 微波電路講義
(derivation of 2) Ld
1 C
Z jwLd , Y jw(Cd ds )
Rds ld ld
Z small loss Ld
Cd G= jB =
Zd 1/Rdsld jwCds/ld Id
Y Rds ld 1 Cd Cds / ld
1 C C jwLd
d ZY jwLd [ jw(Cd ds )] ( jw) 2 Ld (Cd ds )
Rds ld ld ld Rds ld
1 1 1
1
( a b ) 2 a 2 a 2 b
2 Cds 1 1 jwLd
jw Ld (Cd )
ld 2 ( jw) 2 Ld (Cd Cds / ld ) Rds ld
Cds 1 Ld 1 C 1 1 Ld
jw Ld (Cd ) jw Ld (Cd ds )
ld 2 Rds ld Ld (Cd Cds / ld ) ld 2 Rds ld Cd Cds / ld
Cds 1 Zd
jw Ld (Cd ) d jd
ld 2 Rds ld
12-32 微波電路講義
(derivation of 3)
1 N 1
I o I dn e ( N n ) d ld , I dn g mVcn ,Vcn Vi e
( n 1) g lg
( )
2 n 1 1 jwRi Cgs
g N
g mVi N d ld g lg N n ( g lg d ld ) r (1 r N )
Io m
2
V
n 1
cn e ( N n ) d ld
2
e e e
n 1
,r
n
1 r
( N 1)( g lg d ld ) ( l d ld )
g V l e e g g e d ld
m i e N d ld e g g ( l l )
d ld
2 e g g d d 1 e
( N 1)( g lg d ld ) ( g lg d ld )
g V l e e
m i e ( N 1) d ld e g g g lg
2 e e d ld
N l
g mVi e g g e N d ld
2 e g lg e d ld
12-33 微波電路講義
4. For matched i/p and o/p ports
2
Io Zd 2
2 N g lg N d ld
2
Pout 2 I Z Z g Z Z e e
G o d g
m d g
l
e g g e d ld
2 2
Pin Vi Vi 4
2Z g
2
g m2 Z d Z g e N ( g lg j g lg ) e N ( d ld jd ld )
( l j l )
4 e g g g g e ( d ld jd ld )
under synchronization condition g lg d ld ( g d )
g m2 Z d Z g ( e N g lg e N d ld ) 2
G g l g d ld 2
,N G 0
4 (e e )
dG ln( g lg / d ld )
0 N opt
dN g l g d ld
For a lossless amplifier (R i =0, R ds ) and if Z d Z g Z o
g m2 Z d Z g N 2 gm Zo N 2
G ( ) ,G N 2
4 2 微波電路講義
12-34
5. Ex.12.8 Zd= Zg = Zo=50, Ri=5 , Rds=250 , Cgs=0.3pF,
gm=30mS
w2 Ri C gs2 Z o
g lg 0.1@16GHz
2
Zo
d ld 0.114@16GHz
2 Rds
N opt 9.4, frequency response (p.593, Fig.12.16)
N=16
G N=8
(dB)
N=4 16 GHz
N=2
f
12-35 微波電路講義
• Differential amplifier
2
0
0 1 1 0 0 ja ú
ú
1úú 0 úú 2 ú
1
j 1 0 0
2 1 0 0 1 ú 0 ú ja ú
ú ú ú
0 1 1 0 a 2 ú 3
0 ú
4
balun
Vi
Vgs
1 j Ri C gs
RD Rds g m RD Rds
Vo g mVgs Vi
RD Rds (1 j Ri C gs )( RD Rds )
Vo (Vo ) g m RD Rds
Ad =
Vi (Vi ) (1 j Ri C gs )( RD Rds ) output swing and fT doubled
12-36 微波電路講義
11.5 Power amplifiers
• nonlinear operationS(input power, f, DC, T, ZL)
FET nonlinear S G D
equivalent
circuit (large-signal
S-parameter)
Discussion
1. power amplifier characteristics: efficiency, gain, intermodulation
product, thermal conduction
Pout Pin
power added efficiency PAE
PDC
12-37 微波電路講義
2. DC bias consideration
Ids Vgs = 0V
high gain
high power
Vgs = - 1V
class A
LNA
Vgs = Vp
Vds
high efficiency
3. design consideration: large-signal source impedance Γs (source-pull
contour) and load impedance ΓL (load-pull contour)
s in out L
12-38 微波電路講義
4. Ex.12.9 a transistor has small-signal S-parameters at 2.3GHz as
S11 0.593178, S12 0.009 127, S21 1.77 106, S22 0.958175
For class A operation at VDS 28V and I D 0.6 A, Po 10W , G 16.4dB,
Z SP 10 j 3, Z LP 2.5 j 2.3, design the input and output matching
circuits.
12-39 微波電路講義