The processor consists of 5 main stages

1) Fetch: fetches instruction and forward it to the decode stage.

2) Decode: Check instruction code and hence prepare the data
 If the instruction is load or store it perform sign extension for the indirect address.
3) Execute:
 If the instructions are Load or Store, the module use the add module to calculate
effective address.
 If the instructions are Encrypt or Decrypt, the module forward the data to an
AMBA bus Master module.
 The master module forwards the data to the slave (AES module) to be encrypted
or Decrypted.
 The while processor stalls until this operation is done
 The returned burst data is added to the register file on the write back stage.
4) Memory stage:
 Only used on load and store, and the data is 32 bits width, to store 128 bits you
simple need to real 4 words starting from the 1st address
5) Write back, simply write directly in the register file