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Freescale Semiconductor Document Number: DSP56364

Rev. 4.1, 10/2007
Technical Data

DSP56364
24-Bit Audio Digital Signal Processor

1 Overview Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
The DSP56364 supports digital audio applications 2 Signal/Connection Descriptions . . . . . . . . . 2-1
requiring sound field processing, acoustic equalization, 3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . 3-1
and other digital audio algorithms. The DSP56364 uses 4 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
the high performance, single-clock-per-cycle DSP56300 5 Design Considerations . . . . . . . . . . . . . . . . 5-1
core family of programmable CMOS digital signal 6 Ordering Information . . . . . . . . . . . . . . . . . . 6-1
processors (DSPs) combined with the audio signal A IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
processing capability of the Freescale Symphony™ DSP
family, as shown in Figure 1-1. This design provides a
two-fold performance increase over Freescale’s popular
Symphony family of DSPs while retaining code
compatibility. Significant architectural enhancements
include a barrel shifter, 24-bit addressing, instruction
cache, and direct memory access (DMA). The
DSP56364 offers 100 million instructions per second
(MIPS) using an internal 100 MHz clock at 3.3 V.

Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2006, 2007. All rights reserved.

Overview

Data Sheet Conventions
This data sheet uses the following conventions:

OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active
when low.)

“asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low

“deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples: Signal/Symbol Logic State Signal State Voltage*

PIN True Asserted VIL / VOL

PIN False Deasserted VIH / VOH

PIN True Asserted VIH / VOH
PIN False Deasserted VIL / VOL

Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

4 12
5

PROGRAM RAM X Y
GPIO ESAI SHI 0.5K x 24 MEMORY MEMORY
RAM RAM
PROGRAM ROM 1K X 24 1.5K X 24
8K x 24
PERIPHERAL Bootstrap ROM
EXPANSION 192 x 24 MEMORY
AREA EXPANSION
YM_EB
PIO_EB

XM_EB
PM_EB

AREA
YAB ADDRESS
ADDRESS EXTERNAL
GENERATION UNIT XAB ADDRESS 18
PAB BUS
SIX CHANNELS DAB
DMA UNIT SWITCH
24-BIT CONTROL
DRAM & SRAM
DSP56300 BUS
6
CORE INTERFACE

DDB
YDB EXTERNAL DATA
INTERNAL
DATA BUS XDB DATA BUS 8
SWITCH SWITCH
PDB
GDB

POWER
MGMT
DATA ALU
PLL PROGRAM PROGRAM PROGRAM 24 X 24+56→56-BIT MAC
DECODE JTAG 4
INTERRUPT ADDRESS TWO 56-BIT
CLOCK CONT CONT GEN ACCUMULATORS OnCE™
GEN BARREL SHIFTER

EXTAL MODA/IRQA 24 BITS BUS
RESET MODB/IRQB
PINIT/NMI MODD/IRQD

Figure 1-1 DSP56364 Block Diagram

DSP56364 Technical Data, Rev. 4.1
1-2 Freescale Semiconductor

Overview

1.1 Features

1.1.1 Digital Signal Processing Core
• 100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.3V.
• Object Code Compatible with the 56000 core.
• Data ALU with a 24 × 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic
support.
• Program Control with position independent code support and instruction cache support.
• Six-channel DMA controller.
• PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors
(1 to 16) and power saving clock divider (2i: i = 0 to 7). Reduces clock noise.
• Internal address tracing support and OnCE™ for Hardware/Software debugging.
• JTAG port.
• Very low-power CMOS design, fully static design with operating frequencies down to DC.
• STOP and WAIT low-power standby modes.

1.1.2 On-Chip Memory Configuration
• 1.5K × 24 Bit Y-Data RAM.
• 1K × 24 Bit X-Data RAM.
• 8K × 24 Bit Program ROM.
• 0.5K × 24 Bit Program RAM and 192 × 24 Bit Bootstrap ROM.
• 0.75K × 24 Bit from Y Data RAM can be switched to Program RAM resulting in up to 1.25K × 24
Bit of Program RAM.

1.1.3 Off-Chip Memory Expansion
• External Memory Expansion Port with 8-bit data bus.
• Off-chip expansion up to 2 × 16M × 8-bit word of Data/Program memory when using DRAM.
• Off-chip expansion up to 2 × 256k × 8-bit word of Data/Program memory when using SRAM.
• Simultaneous glueless interface to SRAM and DRAM.

1.1.4 Peripheral Modules
• Enhanced Serial Audio Interface (ESAI): 6 serial lines, 4 selectable as receive or transmit and 2
transmit only, master or slave. I2S, Sony, AC97, network and other programmable protocols.
Unused pins of ESAI may be used as GPIO lines.
• Serial Host Interface (SHI): SPI and I2C protocols, 10-word receive FIFO, support for 8, 16 and
24-bit words.
• Four dedicated GPIO lines.

DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor 1-3

2 Documentation Table 1-1 lists the documents that provide a complete description of the DSP56364 and are required to design properly with the part. 4. pin and DSP56364 (this document) package descriptions DSP56364 Technical Data. a Freescale semiconductor sales office.1. a Freescale Literature Distribution Center.5 Packaging • 100-pin plastic TQFP package. Documentation is available from a local Freescale distributor.1 1-4 Freescale Semiconductor . 1.Overview 1. Table 1-1 DSP56364 Documentation Document Name Description Order Number DSP56300 Family Manual Detailed description of the 56000-family DSP56300FM architecture and the 24-bit core processor and instruction set DSP56364 User’s Manual Detailed description of memory. or through the Freescale DSP home page on the Internet (the source for the latest information). peripherals. and DSP56364UM interfaces DSP56364 Product Brief Brief description of the chip DSP56364P DSP56364 Technical Data Sheet Electrical and timing specifications. Rev.

1 Freescale Semiconductor 2-1 .1 Signal Groupings The input and output signals of the DSP56364 are organized into functional groups. some of the inputs can tolerate 5 V.2 Signal/Connection Descriptions 2. and control signals. data bus.3 V supply. including the external address bus. DSP56364 Technical Data. however. 4. which are listed in Table 2-1 and illustrated in Figure 2-1. Table 2-1 DSP56364 Functional Signal Groupings Number of Detailed Functional Group Signals Description Power (VCC) 18 Table 2-2 Ground (GND) 14 Table 2-3 Clock and PLL 3 Table 2-4 Address bus 18 Table 2-5 Data bus 8 Table 2-6 Port A1 Bus control 6 Table 2-7 Interrupt and mode control 4 Table 2-8 General Purpose I/O Port B2 4 Table 2-12 SHI 5 Table 2-9 ESAI Port C3 12 Table 2-10 JTAG/OnCE Port 4 Table 2-11 1 Port A is the external memory interface port. Rev. 3 Port C signals are the ESAI port signals multiplexed with the GPIO signals. A special notice for this feature is added to the signal descriptions of those inputs. The DSP56364 is operated from a 3. 2 Port B signals are the GPIO signals.

1 2-2 Freescale Semiconductor . 4. Rev.Signal Groupings PORT A ADDRESS BUS OnCE™ ON-CHIP EMULATION/ JTAG PORT A0-A17 TDI VCCA (4) TCK GNDA (4) TDO DSP56364 TMS PORT A DATA BUS D0-D7 VCCD (1) Port B GPIO GNDD (1) PB0-PB3 PORT A BUS CONTROL AA0-AA1/RAS0-RAS1 CAS RD WR TA VCCC (1) GNDC (1) RESERVED (4) SERIAL AUDIO INTERFACE (ESAI) Port C SCKT [PC3] FST [PC4] HCKT [PC5] SCKR [PC0] FSR [PC1] INTERRUPT AND MODE CONTROL HCKR [PC2] SDO0 [PC11] MODA/IRQA SDO1 [PC10] MODB/IRQB SDO2/SDI3 [PC9] MODD/IRQD SDO3/SDI2 [PC8] SDO4/SDI1 [PC7] RESET SDO5/SDI0 [PC6] PLL AND CLOCK VCCSS (3) GNDS (3) PINIT/NMI PCAP SERIAL HOST INTERFACE (SHI) VCCP MOSI/HA0 GNDP SS/HA2 MISO/SDA EXTAL SCK/SCL HREQ QUIET POWER VCCHQ (4) VCCLQ (4) GNDQ (4) Figure 2-1 Signals Identified by Functional Group DSP56364 Technical Data.

The user must provide adequate external decoupling capacitors. VCCLQ (4) Quiet Core (Low) Power—VCCLQ is an isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. Rev.3 Ground Table 2-3 Grounds Ground Name Description GNDP PLL Ground—GNDP is ground-dedicated for PLL use. This connection must be tied externally to all other chip ground connections. Power 2. The user must provide adequate external decoupling capacitors.47 μF capacitor located as close as possible to the chip package. VCCC (1) Bus Control Power—VCCC is an isolated power for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. VCCHQ (4) Quiet External (High) Power—VCCHQ is a quiet power source for I/O lines. The connection should be provided with an extremely low-impedance path to ground. This input must be tied externally to all other chip power inputsL. VCCD (1) Data Bus Power—VCCD is an isolated power for sections of the data bus I/O drivers. There are four GNDQ connections. 2. DSP56364 Technical Data. There are four VCCA inputs. The user must provide adequate external decoupling capacitors. GNDQ (4) Quiet Ground—GNDQ is an isolated ground for the internal processing logic. 4. This input must be tied externally to all other chip power inputs. There is one GNDP connection. GNDD (1) Data Bus Ground—GNDD is an isolated ground for sections of the data bus I/O drivers. The user must provide adequate external decoupling capacitors. There is one VCCC inputs. There is one VCCD inputs. VCCA (4) Address Bus Power—VCCA is an isolated power for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. There are three VCCS inputs. This input must be tied externally to all other chip power inputs.1 Freescale Semiconductor 2-3 .2 Power Table 2-2 Power Inputs Power Name Description VCCP PLL Power—VCCP is VCC dedicated for PLL use. The user must provide adequate external decoupling capacitors. There is one VCCP input. There is one GNDD connections. This input must be tied externally to all other chip power inputs. The user must provide adequate decoupling capacitors. The user must provide adequate external decoupling capacitors. VCCP should be bypassed to GNDP by a 0. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. VCCS (3) SHI and ESAI —VCCS is an isolated power for the SHI and ESAI. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. GNDA (4) Address Bus Ground—GNDA is an isolated ground for sections of the address bus I/O drivers. There are four VCCLQ inputs. The user must provide adequate external decoupling capacitors. There are four VCCHQ inputs. There are four GNDA connections.

2. There is one GNDC connections.1 2-4 Freescale Semiconductor . The user must provide adequate external decoupling capacitors. it tri-states the relevant port A signals: D0–D7. PINIT/NMI Input Input PLL Initial/Nonmaskable Interrupt—During assertion of RESET. Rev. the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register. PCAP Input Input PLL Capacitor—PCAP is an input connecting an off-chip capacitor to the PLL filter. RD. GNDS (3) SHI and ESAI —GNDS is an isolated ground for the SHI and ESAI. AA0. 2. determining whether the PLL is enabled or disabled. 4. This connection must be tied externally to all other chip ground connections. or left floating. WR.Clock and PLL Table 2-3 Grounds (continued) Ground Name Description GNDC (1) Bus Control Ground—GNDC is an isolated ground for the bus control I/O drivers. A0–A17 do not change state when external memory spaces are not being accessed. DSP56364 Technical Data. There are three GNDS connections. Connect one capacitor terminal to PCAP and the other terminal to VCCP. To minimize power dissipation.5 External Memory Expansion Port (Port A) When the DSP56364 enters a low-power standby mode (stop or wait). If the PLL is not used.4 Clock and PLL Table 2-4 Clock and PLL Signals State During Signal Name Type Signal Description Reset EXTAL Input Input External Clock Input—An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL. Otherwise. 2. GND. This input is 5 V tolerant. After RESET de assertion and during normal instruction processing. CAS.1 External Address Bus Table 2-5 External Address Bus Signals State During Signal Name Type Signal Description Reset A0–A17 Output Keeper active Address Bus—A0–A17 are active-high outputs that specify the address for external program and data memory accesses.5. AA1. the signals are kept to their previous values by internal weak keepers. the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized to internal system clock. PCAP may be tied to VCC. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

is asserted to enable completion of the bus cycle. these signals RAS0–RAS1 can be used as chip selects or additional address lines.5.3 External Bus Control Table 2-7 External Bus Control Signals State During Signal Name Type Signal Description Reset AA0–AA1/ Output Tri-stated Address Attribute or Row Address Strobe—When defined as AA. The number of wait states is determined by the TA input or by the bus control register (BCR). This signal is tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1. These signals are tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. bidirectional input/outputs that provide the Output bidirectional data bus for external program and data memory accesses. and is deasserted before the next bus cycle. 2. RD Output Tri-stated Read Enable—RD is an active-low output that is asserted to read external memory on the data bus. In typical operation. TA is deasserted at the start of a bus cycle. these signals can be used as RAS for DRAM interface. The BCR can be used to set the minimum number of wait states in external bus cycles. When defined as RAS. D0–D7 are tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. WR Output Tri-stated Write Enable— WR is an active-low output that is asserted to write external memory on the data bus. TA can operate synchronously or asynchronously. otherwise improper operation may result. The current bus cycle completes one clock period after TA is asserted synchronous to the internal system clock. . . DSP56364 Technical Data.1 Freescale Semiconductor 2-5 . This signal is tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. 2. In order to use the TA functionality. the BCR must be programmed to at least one wait state. External Memory Expansion Port (Port A) 2.5.2 External Data Bus Table 2-6 External Data Bus Signals Signal State During Type Signal Description Name Reset D0–D7 Input/ Tri-stated Data Bus—D0–D7 are active-high. whichever is longer. 4. This signal is tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. A zero wait state access cannot be extended by TA deassertion. otherwise improper operation may result. TA functionality may not be used while performing DRAM type accesses. Rev. depending on the setting of the TAS bit in the operating mode register (OMR). CAS Output Tri-stated Column Address Strobe— CAS is an active-low output used by DRAM to strobe the column address.infinity) may be added to the wait states inserted by the BCR by keeping TA deasserted. TA Input Ignored Input Transfer Acknowledge—If there is no external bus activity. These signals are tri-stateable outputs with programmable polarity.

This input is 5 V tolerant. multiple processors can be re synchronized using the WAIT instruction and asserting IRQD to exit the wait state. Schmitt-trigger input. and MODD select one of 8 initial chip operating modes. MODA. the chip is placed in the reset state and the internal phase generator is reset. MODA. maskable interrupt request input during normal instruction processing.Interrupt and Mode Control 2. DSP56364 Technical Data. latched into OMR when the RESET signal is deasserted. these inputs are hardware interrupt request lines. multiple processors can be re synchronized using the WAIT instruction and asserting IRQA to exit the wait state. This input is 5 V tolerant. The RESET signal must be asserted during power up. and MODD inputs. When asserted. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. This input is 5 V tolerant. When the RESET signal is deasserted.6 Interrupt and Mode Control The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. internally synchronized to the internal system clock. latched into OMR when the RESET signal is deasserted. If IRQB is asserted synchronous to the internal system clock. internally synchronized to the internal system clock. Table 2-8 Interrupt and Mode Control State During Signal Name Type Signal Description Reset MODA/IRQA Input Input Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low Schmitt-trigger input. This input is 5 V tolerant. MODA. If the processor is in the stop standby state and IRQA is asserted. MODB.1 2-6 Freescale Semiconductor . MODB. internally synchronized to the internal system clock. MODB/IRQB Input Input Mode Select B/External Interrupt Request B—MODB/IRQB is an active-low Schmitt-trigger input. multiple processors can be re-synchronized using the WAIT instruction and asserting IRQB to exit the wait state. and MODD select one of 8 initial chip operating modes. RESET Input Input Reset—RESET is an active-low. If IRQA is asserted synchronous to the internal system clock. maskable interrupt request input during normal instruction processing. If IRQD is asserted synchronous to the internal system clock. and MODD select one of 8 initial chip operating modes. MODB. MODB. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered. A stable EXTAL signal must be supplied before deassertion of RESET. maskable interrupt request input during normal instruction processing. the processor will exit the stop state. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered. the initial chip operating mode is latched from the MODA. MODD/IRQD Input Input Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low Schmitt-trigger input. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered. latched into the OMR when the RESET signal is deasserted. 4. Rev. After RESET is deasserted.

SDA should be connected to output VCC through a pull-up resistor. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event. DSP56364 Technical Data. Serial Host Interface 2. there is no need for an external pull-up in this state. the SCK signal is an input. data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. This signal is tri-stated during hardware. The data in SDA must be stable during the high period of SCL. SCL should be connected to VCC through a pull-up resistor. SDA Input or Tri-stated I2C Data and Acknowledge—In I2C mode. MISO Input or Tri-stated SPI Master-In-Slave-Out—When the SPI is configured as a master. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. the SCK signal is derived from the internal SHI clock generator. A high-to-low transition of the SDA line while SCL is high is a unique situation. When the SPI is configured as a slave. software. When the SPI is configured as a master. Thus. This input is 5 V tolerant. This input is 5 V tolerant.1 Freescale Semiconductor 2-7 . software. and individual reset. SDA is a Schmitt-trigger input when open-drain receiving and an open-drain output when transmitting. MOSI Input or Tri-stated SPI Master-Out-Slave-In—When the SPI is configured as a master. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. SDA carries the data for I2C transactions. Table 2-9 Serial Host Interface Signals Signal Signal State During Signal Description Name Type Reset SCK Input or Tri-stated SPI Serial Clock—The SCK signal is an output when the SPI is configured as a master output and a Schmitt-trigger input when the SPI is configured as a slave. An external pull-up resistor is not required for SPI operation. The data in SDA is only allowed to change when SCL is low. SDA is high. This signal is tri-stated during hardware. and tri-stated if configured for the SPI Slave mode when SS is deasserted. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. This signal is a Schmitt-trigger input when configured for the SPI Master mode. In both the master and slave SPI devices. and the clock signal from the external master synchronizes the data transfer. and is defined as the start event. Edge polarity is determined by the SPI transfer protocol. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events.7 Serial Host Interface The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode. MOSI is the slave data input line when the SPI is configured as a slave. an output when configured for the SPI Slave mode. there is no need for an external pull-up in this state. Rev. When the bus is free. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. and individual reset. Thus. SCL output is a Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. MISO is the output master data input line. SCL Input or Tri-stated I2C Serial Clock—SCL carries the clock for I2C bus transactions in the I2C mode. MOSI is the output master data output line. 4.

DSP56364 Technical Data. HA0 is ignored when configured for the I2C master mode. SS Input Input SPI Slave Select—This signal is an active low Schmitt-trigger input when configured for the SPI mode.Serial Host Interface Table 2-9 Serial Host Interface Signals (continued) Signal Signal State During Signal Description Name Type Reset HA0 Input Tri-stated I2C Slave Address 0—This signal uses a Schmitt-trigger input when configured for the I2C mode. HREQ is an input. This input is 5 V tolerant. it will trigger the start of the data word transfer by the master. personal reset. software. When configured for the slave mode. HREQ Input or Tri-stated Host Request—This signal is an active low Schmitt-trigger input when configured for Output the master mode but an active low output when configured for the slave mode. and individual reset. Rev. This signal is tri-stated during hardware. If SS is deasserted. the HA2 signal is used to form the slave device address. Thus. This input is 5 V tolerant. there is no need for an external pull-up in this state. a bus error condition is flagged. When configured for the master mode. this signal should be kept deasserted (pulled high). After finishing the data word transfer. 4. When asserted by the external slave device. software. When configured for the SPI Slave mode. software. the HA0 signal is used to form the slave device address. When configured for I2C slave mode. the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. HA2 is ignored in the I2C master mode. or when the HREQ1–HREQ0 bits in the HCSR are cleared. This input is 5 V tolerant. HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the I2C Slave mode. this signal is used to enable the SPI slave for transfer.1 2-8 Freescale Semiconductor . the master will await the next assertion of HREQ to proceed to the next transfer. This signal is tri-stated during hardware. there is no need for an external pull-up in this state. There is no need for external pull-up in this state. When configured for the SPI master mode. Thus. If it is asserted while configured as SPI master. HA2 Input Input I2C Slave Address 2—This signal uses a Schmitt-trigger input when configured for the I2C mode. This signal is tri-stated during hardware. and individual reset.

8 Enhanced Serial Audio Interface Table 2-10 Enhanced Serial Audio Interface Signals Signal State During Signal Type Signal Description Name Reset HCKR Input or output GPIO High Frequency Clock for Receiver—When programmed as an input. or internally disconnected. output. FST is the frame sync for the transmitters only. PC5 Input. FSR Input or output GPIO Frame Sync for Receiver—This is the receiver frame sync input/output signal. this signal can serve as a high frequency sample clock (e. output. 4. When configured as the input flag IF1. When configured as the output flag OF1. Rev. When this pin is configured as serial flag pin. output. For synchronous mode. The default state after reset is GPIO disconnected. output. this disconnected signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. output. RFSD=1). this signal is individually disconnected disconnected programmable as input. PC2 Input. or GPIO Port C 2—When the ESAI is configured as GPIO. the data value at the pin will be stored in the IF1 bit in the SAISR register. output. this signal is individually disconnected disconnected programmable as input. or as the transmitter external buffer enable control (TEBE=1. its direction is determined by the RFSD bit in the RCCR register.g. The default state after reset is GPIO disconnected. When programmed as an output. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). this signal can serve as a high-frequency sample clock (e. the FSR pin operates as the frame sync input or output used by all the enabled receivers. FST Input or output GPIO Frame Sync for Transmitter—This is the transmitter frame sync input/output disconnected signal. this pin will reflect the value of the OF1 bit in the SAICR register. it operates as either the serial flag 1 pin (TEBE=0). The default state after reset is GPIO disconnected. this signal is the frame sync for both transmitters and receivers. for external digital to analog converters [DACs]) or as an additional system clock. synchronized by the frame sync in normal mode or the slot in network mode. or GPIO Port C 1—When the ESAI is configured as GPIO. and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. HCKT Input or output GPIO High Frequency Clock for Transmitter—When programmed as an input. disconnected In the asynchronous mode (SYN=0). This input is 5 V tolerant. or GPIO Port C 5—When the ESAI is configured as GPIO. Enhanced Serial Audio Interface 2. for external DACs) or as an additional system clock.. PC1 Input. this disconnected signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. This input is 5 V tolerant. In the synchronous mode (SYN=1).g. This input is 5 V tolerant. or internally disconnected..1 Freescale Semiconductor 2-9 . When programmed as an output. or internally disconnected. For asynchronous mode. this signal is individually disconnected disconnected programmable as input. DSP56364 Technical Data.

SDO4 Output GPIO Serial Data Output 4—When programmed as a transmitter. its direction is determined by the RCKD bit in the RCCR register. or as serial flag 0 pin in the synchronous mode (SYN=1). this signal is individually disconnected disconnected programmable as input. Rev.1 2-10 Freescale Semiconductor . output. the data value at the pin will be stored in the IF0 bit in the SAISR register. or by all enabled transmitters in asynchronous mode. output. 4. PC6 Input. SDI0 Input GPIO Serial Data Input 0—When programmed as a receiver. SDO5 Output GPIO Serial Data Output 5—When programmed as a transmitter. this signal is individually disconnected disconnected programmable as input. DSP56364 Technical Data. SDO4 is used to disconnected transmit data from the TX4 serial transmit shift register. output. this signal is individually disconnected disconnected programmable as input. When configured as the output flag OF0. or GPIO Port C 0—When the ESAI is configured as GPIO. output. SDI0 is used to receive disconnected serial data into the RX0 serial receive shift register. or GPIO Port C 6—When the ESAI is configured as GPIO. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0). The default state after reset is GPIO disconnected. This input is 5 V tolerant. The default state after reset is GPIO disconnected. The default state after reset is GPIO disconnected. or GPIO Port C 3—When the ESAI is configured as GPIO. output. This input is 5 V tolerant. The default state after reset is GPIO disconnected. output. SCKT Input or output GPIO Transmitter Serial Clock—This signal provides the serial bit rate clock for the disconnected ESAI. or internally disconnected. or internally disconnected. and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. output. or GPIO Port C 4—When the ESAI is configured as GPIO. output. this signal is individually disconnected disconnected programmable as input. this pin will reflect the value of the OF0 bit in the SAICR register. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode. PC0 Input. synchronized by the frame sync in normal mode or the slot in network mode. This input is 5 V tolerant. This input is 5 V tolerant. When this pin is configured as serial flag pin. SDO5 is used to disconnected transmit data from the TX5 serial transmit shift register. or internally disconnected.Enhanced Serial Audio Interface Table 2-10 Enhanced Serial Audio Interface Signals (continued) Signal State During Signal Type Signal Description Name Reset PC4 Input. When configured as the input flag IF0. PC3 Input. or internally disconnected. SCKR Input or output GPIO Receiver Serial Clock—SCKR provides the receiver serial bit clock for the disconnected ESAI.

output. Rev. SDO3 Output GPIO Serial Data Output 3—When programmed as a transmitter. The default state after reset is GPIO disconnected. The default state after reset is GPIO disconnected. output. PC10 Input. The default state after reset is GPIO disconnected. output. output. Enhanced Serial Audio Interface Table 2-10 Enhanced Serial Audio Interface Signals (continued) Signal State During Signal Type Signal Description Name Reset SDI1 Input GPIO Serial Data Input 1—When programmed as a receiver. this signal is individually disconnected disconnected programmable as input. This input is 5 V tolerant. or GPIO Port C 10—When the ESAI is configured as GPIO. 4. SDO3 is used to disconnected transmit data from the TX3 serial transmit shift register. or GPIO Port C 9—When the ESAI is configured as GPIO. DSP56364 Technical Data. output.1 Freescale Semiconductor 2-11 . or internally disconnected. This input is 5 V tolerant. or internally disconnected. this signal is individually disconnected disconnected programmable as input. PC8 Input. or internally disconnected. The default state after reset is GPIO disconnected. output. This input is 5 V tolerant. This input is 5 V tolerant. PC7 Input. this signal is individually disconnected disconnected programmable as input. or GPIO Port C 7—When the ESAI is configured as GPIO. output. PC11 Input. this signal is individually disconnected disconnected programmable as input. output. SDI2 is used to receive disconnected serial data into the RX2 serial receive shift register. This input is 5 V tolerant. or internally disconnected. SDI2 Input GPIO Serial Data Input 2—When programmed as a receiver. SDO1 Output GPIO Serial Data Output 1—SDO1 is used to transmit data from the TX1 serial disconnected transmit shift register. SDO0 Output GPIO Serial Data Output 0—SDO0 is used to transmit data from the TX0 serial disconnected transmit shift register. or GPIO Port C 11—When the ESAI is configured as GPIO. SDI1 is used to receive disconnected serial data into the RX1 serial receive shift register. The default state after reset is GPIO disconnected. SDI3 is used to receive disconnected serial data into the RX3 serial receive shift register. SDO2 is used to disconnected transmit data from the TX2 serial transmit shift register SDI3 Input GPIO Serial Data Input 3—When programmed as a receiver. SDO2 Output GPIO Serial Data Output 2—When programmed as a transmitter. PC9 Input. or internally disconnected. this signal is individually disconnected disconnected programmable as input. output. or GPIO Port C 8—When the ESAI is configured as GPIO. output.

Table 2-12 GPIO Signals Signal State During Signal Type Signal Description Name Reset GPIO0– Input. Each Port B GPIO pin may be individually programmed as an input. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TMS Input Input Test Mode Select—TMS is an input signal used to sequence the test controller’s state machine. This input is 5 V tolerant. TDI Input Input Test Data Input—TDI is a test data serial input signal used for test instructions and data. output or disconnected DSP56364 Technical Data. This input is 5 V tolerant. TDO Output Tri-stated Test Data Output—TDO is a test data serial output signal used for test instructions and data.9 JTAG/OnCE Interface Table 2-11 JTAG/OnCE Interface Signal Signal State During Signal Description Name Type Reset TCK Input Input Test Clock—TCK is a test clock input signal used to synchronize the JTAG test logic. TDO changes on the falling edge of TCK. output or Disconnected GPIO0–3—The General Purpose I/O pins are used for control and GPIO3 disconnected handshake functions between the DSP and external circuitry.1 2-12 Freescale Semiconductor . TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant. Rev.JTAG/OnCE Interface 2. It has an internal pull-up resistor. 4. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor.

Finalized specifications will be published after full characterization and device qualifications are complete. NOTE In the calculation of timing requirements. 4.1 Introduction The DSP56364 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs and outputs. The DSP56364 specifications are preliminary and are from design simulations.1 Freescale Semiconductor 3-1 . DSP56364 Technical Data. 3. a “maximum” value for a specification will never occur in the same device that has a “minimum” value for another specification. A maximum specification is calculated using a worst case variation of process parameter values in one direction. adding a maximum to a minimum represents a condition that can never exist. and may not be fully tested or guaranteed. either GND or VCC). Therefore.g. However. normal precautions should be taken to avoid exceeding maximum voltage ratings..3 Specifications 3. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. The suggested value for a pull-up or pull-down resistor is 10 kΩ. Rev. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e. adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum.2 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields.

805 East Middlefield Rd. In any case.16 V. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3.26 °C/W Thermal characterization parameter ΨJT 2. 4.3 to +4. (415) 964-5111.1 3-2 Freescale Semiconductor .87 °C/W Junction-to-case thermal resistance2 RθJC or θJC 9.95 V greater than the supply voltage. “5 V Tolerant” inputs are inputs that tolerate 5 V. TJ = –0°C to +105°C. 2 Unit Supply Voltage VCC −0. (SEMI is Semiconductor Equipment and Materials International.3 to VCC + 0. VCC = 3. 3 CAUTION: All “5 V Tolerant” input voltages must not be more than 3. the input voltages cannot be more than 5. Rev. CL = 50 pF 2 Absolute maximum ratings are stress ratings only.) Measurements were done with parts mounted on thermal test boards conforming to specification EIA/JESD51-3. with the exception that the cold plate temperature is used for the case temperature.95 V Current drain per pin excluding VCC and GND I 10 mA Operating temperature range TJ -40 to +105 °C Storage temperature TSTG −55 to +125 °C 1 GND = 0 V.. as well as during normal operation. and functional operation at the maximum is not guaranteed. CA 94043. Mountain View. DSP56364 Technical Data.3 Thermal Characteristics Table 3-2 Thermal Characteristics Characteristic Symbol TQFP Value Unit Junction-to-ambient thermal resistance1 RθJA or θJA 49.3 to VCC + 3.0 °C/W 1 Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per SEMI G38-87 in natural convection. 2 Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88.3 V All “5 V tolerant” input voltages3 VIN5 GND − 0.75 V. this restriction applies to “power on”.0 V All input voltages excluding “5 V tolerant” inputs3 VIN GND -0.3 V ± 0.Thermal Characteristics Table 3-1 Maximum Ratings Rating1 Symbol Value1.

5 — VCC + 3.1 × VCC.16 V. 4 Periodically sampled and not 100% tested DSP56364 Technical Data. PINIT/NMI and all VIHP 2.01 — — V Output low voltage VOL V • TTL (IOL = 3.3 — 0.46 V Input high voltage V • D(0:7).5 mA Input capacitance4 CIN — — 10 pF 1 VCC = 3.4 — — V • CMOS (IOH = –10 μA)4 VCC – 0. RESET.0 mA. open-drain pins IOL = 6.4 DC Electrical Characteristics Table 3-3 DC Electrical Characteristics1 Characteristics Symbol Min Typ Max Unit Supply voltage VCC 3.3 V ± .3 — 0.01 Internal supply current6 at internal clock of 100 MHz • In Normal mode ICCI — 127 181 mA • In Wait mode7 ICCW — 7. CL = 50 pF 2 Refers to MODA/IRQA.5 2.1 Freescale Semiconductor 3-3 . To minimize power consumption.3 3. DC Electrical Characteristics 3.9 × VCC and the maximum VILX should be no higher than 0.8 • JTAG/ESAI/GPIO/SHI (SPI mode)pins VILP –0.4 • CMOS (IOL = 10 μA)4 — — 0.4 mA)4.3 — 0.3x VCC • EXTAL3 VILX –0.8 • SHI (I2C mode) pins VILP -0.4 V / 0. 5 11 mA • In Stop mode8 ICCS — 100 150 μA PLL supply current — 1 2. RESET.4 V) ITSI –10 — 10 μA Output high voltage VOH • TTL (IOH = –0.95 JTAG/ESAI/GPIO/SHI (SPI mode) pins • SHI (I2C mode) pins VIHP 1.7 mA)4. MODB/IRQB.0 — VCC • MOD2/IRQ2.8 × VCC — VCC Input low voltage V • D(0:7).0 — VCC + 3.95 • EXTAL3 VIHX 0. and MODD/IRQD pins 3 Driving EXTAL to the low VIHX or the high VILX value may cause additional power consumption (DC current). TA. the minimum VIHX should be no lower than 0. TA VIH 2. Rev. PINIT VIL –0. 4.14 3.5 — — 0.3 — 0. TJ = 0°C to +105°C.2 × VCC Input leakage current IIN –10 — 10 μA High impedance (off-state) input current (@ 2. MOD2/IRQ2.

AC timing specifications. the device AC test conditions are 15 MHz and rated speed. 2 Characteristics Symbol Min Typ Max Internal operation frequency with PLL enabled f — (Ef × MF)/ — (PDF × DF) Internal operation frequency with PLL disabled f — Ef/2 — Internal clock high period TH • With PLL disabled — ETC — • With PLL enabled and MF ≤ 4 0.. not allowed to float).4 V for all pins except EXTAL. NOTE Although the minimum value for the frequency of EXTAL is 0 MHz.3 V at TJ = 105°C. Maximum internal supply current is measured with VCC = 3..47 × ETC × — 0.6 Internal Clocks Table 3-4 Internal Clocks Expression1. 8 In order to obtain these results.3 V and a VIH minimum of 2. must be terminated (i.4 V and 2.AC Electrical Characteristics 5 This characteristic does not apply to PCAP. 3. This reflects typical DSP applications. "Design Considerations" provides a formula to compute the estimated current requirements in Normal mode. 4. DSP56364 output levels are measured with the production test machine VOL and VOH reference levels set at 0.1 3-4 Freescale Semiconductor . Rev. The power consumption numbers in this specification are 90% of the measured results of this benchmark. respectively.46 V at TJ = 105°C. are measured in production with respect to the 50% point of the respective input signal’s transition. not allowed to float). In order to obtain these results. which are referenced to a device input signal. all inputs.e. which is tested using the input levels shown in Note 8 of the previous table. all inputs must be terminated (i. PLL signal is disabled during Stop state.e..e. 3. which are not disconnected at Stop mode. 6 Section 5. Typical internal supply current is measured with VCC = 3. not allowed to float). 7 In order to obtain these results.53 × ETC × PDF × DF/MF PDF × DF/MF DSP56364 Technical Data.4 V.49 × ETC × — 0. all inputs must be terminated (i.51 × ETC × PDF × DF/MF PDF × DF/MF • With PLL enabled and MF > 4 0.5 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0. Measurements are based on synthetic intensive DSP benchmarks.

4. 3.49 × ETC × — 0. 2 Characteristics Symbol Min Typ Max Internal clock low period TL • With PLL disabled — ETC — • With PLL enabled and MF ≤ 4 0.7 External Clock Operation The DSP56364 system clock is an externally supplied square wave voltage source connected to EXTAL (See Figure 3-1).51 × ETC × PDF × DF/MF PDF × DF/MF • With PLL enabled and MF > 4 0.53 × ETC × PDF × DF/MF PDF × DF/MF Internal clock cycle time with PLL enabled TC — ETC × PDF × — DF/MF Internal clock cycle time with PLL disabled TC — 2 × ETC — Instruction cycle time ICYC — TC — 1 DF = Division Factor Ef = External frequency ETC = External clock cycle MF = Multiplication Factor PDF = Predivision Factor TC = internal clock cycle 2 See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL. Rev. VIHC Midpoint EXTAL VILC ETH ETL 2 3 4 ETC Note: The midpoint is 0. External Clock Operation Table 3-4 Internal Clocks (continued) Expression1.47 × ETC × — 0.1 Freescale Semiconductor 3-5 . Figure 3-1 External Clock Timing DSP56364 Technical Data.5 (VIHC + VILC).

2 The maximum value for PLL enabled is given for minimum VCO and maximum MF.5% duty cycle6) 4.00 ns 273.0 μs 3 EXTAL input low1.1 μs 1 Measured at 50% of the input transition. 2 • With PLL disabled (46.67 ns ∞ • With PLL enabled (42.3% duty cycle6) ETL 4.25 ns 157. 2 • With PLL disabled (46.7%–53.25 ns 157.5%–57.0 μs 4 EXTAL cycle time2 • With PLL disabled ETC 10.00 ns ∞ • With PLL enabled 10. The recommended value in pF for CPCAP can be computed from one of the following equations: (MF x 680)-120.5%–57.7%–53.3% duty cycle6) ETH 4. 4. for MF > 4. DSP56364 Technical Data. or MF x 1100.8 Phase Lock Loop (PLL) Characteristics Table 3-6 PLL Characteristics Characteristics Min Max Unit VCO frequency when PLL enabled (MF × Ef × 2/PDF) 30 200 MHz PLL external capacitor (PCAP pin to VCCP) (CPCAP1) pF • @ MF ≤ 4 (MF × 580) − 100 (MF × 780) − 140 • @ MF > 4 MF × 830 MF × 1470 1 CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). Rev.0 The rise and fall time of this external clock should be 3 ns maximum.Phase Lock Loop (PLL) Characteristics Table 3-5 Clock Operation No. 3. Characteristics Symbol Min Max 1 Frequency of EXTAL (EXTAL Pin Frequency) Ef 0 100.5% duty cycle6) 4. 2 EXTAL input high1. for MF ≤ 4.67 ns ∞ • With PLL enabled (42.1 3-6 Freescale Semiconductor .

Reset, Stop, Mode Select, and Interrupt Timing

3.9 Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1

No. Characteristics Expression2 Min Max Unit

8 Delay from RESET assertion to all pins at reset value3 — — 26.0 ns

9 Required RESET duration4
• Power on, external clock generator, PLL disabled 50 × ETC 500.0 — ns

• Power on, external clock generator, PLL enabled 1000 × ETC 10.0 — ns

• Power on, internal oscillator 75000 × ETC 0.75 — μs

• During STOP, XTAL disabled (PCTL Bit 16 = 0) 75000 × ETC 0.75 — ms

• During STOP, XTAL enabled (PCTL Bit 16 = 1) 2.5 × TC 25.0 — ms

• During normal operation 2.5 × TC 25.0 — ns

10 Delay from asynchronous RESET deassertion to first
external address output (internal reset deassertion)5
• Minimum 3.25 × TC + 2.0 34.5 — ns

• Maximum 20.25 TC + 7.50 — 211.5 ns

13 Mode select setup time 30.0 — ns

14 Mode select hold time 0.0 — ns

15 Minimum edge-triggered interrupt request assertion width 6.6 — ns

16 Minimum edge-triggered interrupt request deassertion width 6.6 — ns

17 Delay from IRQA, IRQB, IRQD, NMI assertion to external
memory access address out valid
• Caused by first interrupt instruction fetch 4.25 × TC + 2.0 44.5 — ns

• Caused by first interrupt instruction execution 7.25 × TC + 2.0 74.5 — ns

18 Delay from IRQA, IRQB, IRQD, NMI assertion to 10 × TC + 5.0 105.0 — ns
general-purpose transfer output valid caused by first
interrupt instruction execution

19 Delay from address output valid caused by first interrupt 3.75 × TC + WS × TC – 10.94 — — ns
instruction execute to interrupt request deassertion for level
sensitive fast interrupts 6, 7

20 Delay from RD assertion to interrupt request deassertion 3.25 × TC + WS × TC – 10.94 — — ns
for level sensitive fast interrupts6, 7

DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor 3-7

Reset, Stop, Mode Select, and Interrupt Timing

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 (continued)

No. Characteristics Expression2 Min Max Unit

21 Delay from WR assertion to interrupt request deassertion ns
for level sensitive fast interrupts6, 7

• DRAM for all WS (WS + 3.5) × TC – 10.94 — —

• SRAM WS = 1 (WS + 3.5) × TC – 10.94 — —

• SRAM WS = 2, 3 (WS + 3) × TC – 10.94 — —

• SRAM WS ≥ 4 (WS + 2.5) × TC – 10.94 — —

24 Duration for IRQA assertion to recover from Stop state 5.9 —

25 Delay from IRQA assertion to fetch of first instruction (when
exiting Stop)3, 8
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop PLC × ETC × PDF + 1.3 13.6 ms
delay is enabled (OMR Bit 6 = 0) (128 K − PLC/2) × TC

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop PLC × ETC × PDF + 232.5 12.3
delay is not enabled (OMR Bit 6 = 1) (23.75 ± 0.5) × TC ns ms

• PLL is active during Stop (PCTL Bit 17 = 1) (Implies No (8.25 ± 0.5) × TC 77.5 87.5 ns
Stop Delay)

26 Duration of level sensitive IRQA assertion to ensure
interrupt service (when exiting Stop)3, 8
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop PLC × ETC × PDF + 13.6 — ms
delay is enabled (OMR Bit 6 = 0) (128 K − PLC/2) × TC

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop PLC × ETC × PDF + 12.3 — ms
delay is not enabled (OMR Bit 6 = 1) (20.5 ± 0.5) × TC

• PLL is active during Stop (PCTL Bit 17 = 1) (implies no 5.5 × TC 55.0 — ns
Stop delay)

27 Interrupt Requests Rate
• ESAI, SCI 12TC — 120.0 ns

• DMA 8TC — 80.0 ns

• IRQ, NMI (edge trigger) 8TC — 80.0 ns

• IRQ, NMI (level trigger) 12TC — 120.0 ns

28 DMA Requests Rate
• Data read from ESAI, SCI 6TC — 60.0 ns

• Data write to ESAI, SCI 7TC — 70.0 ns

• IRQ, NMI (edge trigger) 3TC — 30.0 ns

DSP56364 Technical Data, Rev. 4.1
3-8 Freescale Semiconductor

Reset, Stop, Mode Select, and Interrupt Timing

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 (continued)

No. Characteristics Expression2 Min Max Unit

29 Delay from IRQA, IRQB, IRQD, NMI assertion to external 4.25 × TC + 2.0 44.0 — ns
memory (DMA source) access address out valid
1 VCC = 3.3 V ± 0.16 V; TJ = 0°C to + 105°C, CL = 50 pF
2
Use expression to compute maximum value.
3
Periodically sampled and not 100% tested
4
For an external clock generator, RESET duration is measured during the time in which RESET is asserted, VCC is valid, and
the EXTAL input is active and valid.
For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified
timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the
crystal and other components connected to the oscillator and reflects worst case conditions.
When the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should
minimize this state to the shortest possible duration.
5 For an external clock generator, RESET duration is measured during the time in which RESET is asserted, V
CC is valid, and
the EXTAL input is active and valid.
For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified
timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the
crystal and other components connected to the oscillator and reflects worst case conditions.
When the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should
minimize this state to the shortest possible duration.
6 When using fast interrupts and IRQA, IRQB, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent

multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using
fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
7 WS = number of wait states (measured in clock cycles, number of T )
C
8 This timing depends on several settings:

For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL
Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before executing programs. In that case, resetting
the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended
and these specifications do not guarantee timings for that case.
For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization
delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored).
For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by
the PCTL Bit 17 and OMR Bit 6 settings.
For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked.
The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in
parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay
counter completes count or PLL lock procedure completion.
PLC value for PLL disable is 0.
The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 100 MHz it is 4096/100
MHz = 40 μs). During the stabilization period, TC, TH, and TL will not be constant, and their width may vary, so timing may vary
as well.
9. If PLL does not lose lock.

DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor 3-9

1 3-10 Freescale Semiconductor . IRQB. IRQB. Rev. IRQD. and Interrupt Timing VIH RESET 9 10 8 All Pins Reset Value A0–A17 First Fetch AA0460 Figure 3-2 Reset Timing First Interrupt Instruction A0–A17 Execution/Fetch RD 20 WR 21 IRQA. Stop. 17 19 IRQD. 4.Reset. Mode Select. NMI b) General Purpose I/O AA0462 Figure 3-3 External Fast Interrupt Timing DSP56364 Technical Data. NMI a) First Interrupt Instruction Execution General Purpose I/O 18 IRQA.

MODA.MODD. IRQB. NMI PINIT AA0465 Figure 3-5 Operating Mode Select Timing 24 IRQA 25 A0–A17 First Instruction Fetch AA0466 Figure 3-6 Recovery from Stop State Using IRQA DSP56364 Technical Data.1 Freescale Semiconductor 3-11 . IRQD. and Interrupt Timing IRQA. 4. IRQD. Reset. Mode Select. IRQB. Stop. MODB. IRQB. Rev. NMI 15 IRQA. NMI 16 AA0463 Figure 3-4 External Interrupt Timing (Negative Edge-Triggered) VIH RESET 13 14 VIH VIH IRQA. VIL VIL IRQD.

External Memory Expansion Port (Port A) 26 IRQA 25 A0–A17 First IRQA Interrupt Instruction Fetch AA0467 Figure 3-7 Recovery from Stop State Using IRQA Interrupt Service A0–A17 DMA Source Address RD WR IRQA. tWC (WS + 1) × TC − 4.0 56. 4. IRQB. Rev. Characteristics Symbol Expression2 Min Max Unit 100 Address valid and AA assertion pulse width tRC.1 3-12 Freescale Semiconductor . First Interrupt Instruction Execution NMI AA1104 Figure 3-8 External Memory Access (DMA Source) Timing 3.0 — ns [4 ≤ WS ≤ 7] (WS + 3) × TC − 4.10.0 — ns [WS ≥ 8] DSP56364 Technical Data.0 16.0 106.1 SRAM Timing Table 3-8 SRAM Read and Write Accesses1 No.10 External Memory Expansion Port (Port A) 3. 29 IRQD.0 — ns [1 ≤ WS ≤ 3] (WS + 2) × TC − 4.

5 — ns [WS ≥ 1] DSP56364 Technical Data.25 × TC − 2.75) × TC − 7.0 20.5 — ns [WS ≥ 8] All frequencies: 8.5 × TC − 4.0 [4 ≤ WS ≤ 7] 2.5 — ns 1.25 × TC − 4.5 — ns [WS = 1] 0.0 — 5.25 × TC − 2. Rev.25 × TC − 4.25 × TC − 2.5 ns [WS ≥ 1] 105 RD assertion to input data valid tOE (WS + 0.5 — ns [WS ≥ 4] 102 WR assertion pulse width tWP 1.5 — ns [2 ≤ WS ≤ 3] 1.0 31.0 13.5 — ns [WS ≥ 8] 104 Address and AA valid to input data valid tAA.0 10.0 0.75 × TC − 2.5 — ns [4 ≤ WS ≤ 7] 2.0 — ns 107 Address valid to WR deassertion3 tAW (WS + 0.0 — ns [WS = 1] All frequencies: 16.1 Freescale Semiconductor 3-13 .0 10.0 11.25) × TC − 7.0 — 10.5 ns [WS ≥ 1] 106 RD deassertion to data not valid (data hold time) tOHZ 0.5 — ns [1 ≤ WS ≤ 3] 1.0 — ns [WS ≥ 4] 103 WR deassertion to address not valid tWR 0.25 × TC − 2.0 5. tAC (WS + 0.0 — ns WS × TC − 4. Characteristics Symbol Expression2 Min Max Unit 101 Address and AA valid to WR assertion tAS 0. External Memory Expansion Port (Port A) Table 3-8 SRAM Read and Write Accesses1 (continued) No.0 18. 4.25 × TC − 2.0 0.75) × TC − 4.5) × TC − 4.0 [2 ≤ WS ≤ 3] (WS − 0.

1 3-14 Freescale Semiconductor .0 3.0 — ns [WS = 1] TC − 2.0 — ns [WS ≥ 8] 115 Address valid to RD assertion 0.0 13.25 × TC − 2.0 0.5 — ns [WS ≥ 8] 114 WR deassertion time 0.0 31.25 × TC − 2.0 — ns 116 RD assertion pulse width (WS + 0.5 — ns [4 ≤ WS ≤ 7] 2.0 20.0 20.5 × TC − 4.25) × TC − 3.25 × TC − 2.25 × TC − 2.0 4.75 × TC − 4.5 — ns [1 ≤ WS ≤ 3] 1.25) × TC −4.5 — ns [WS ≥ 1] 109 Data hold time from WR deassertion tDH 0.75 × TC − 4.5 × TC − 4.5 — ns [4 ≤ WS ≤ 7] 2.25 × TC − 2.5 — ns [1 ≤ WS ≤ 3] 1.5 — ns [4 ≤ WS ≤ 7] 2.0 21.External Memory Expansion Port (Port A) Table 3-8 SRAM Read and Write Accesses1 (continued) No.25 × TC − 2.5 — ns [WS ≥ 8] DSP56364 Technical Data.0 23.5 × TC − 4.0 10.5 — ns 117 RD deassertion to address not valid 0.5 × TC − 4.0 1. Rev.0 — ns [2 ≤ WS ≤ 3] 2.5 — ns [1 ≤ WS ≤ 3] 1.75 × TC − 4.0 — ns [4 ≤ WS ≤ 7] 3.0 1.5 — ns [WS ≥ 8] 113 RD deassertion time 0.0 8.0 6.0 0.0 10. Characteristics Symbol Expression2 Min Max Unit 108 Data valid to WR deassertion (data setup time) tDS (tDW) (WS − 0. 4.

107 are guaranteed by design. External Memory Expansion Port (Port A) Table 3-8 SRAM Read and Write Accesses1 (continued) No. 4 In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active.5 · Vcc to . 3 Timings 100.5 — ns 119 TA hold after RD or WR deassertion 0 — ns 1 All timings for 100 MHz are measured from 0.05 · Vcc 2 WS is the number of wait states specified in the BCR. not tested. 100 A0–A17 AA0–AA1 113 116 117 RD 115 105 106 WR 104 119 118 TA Data D0–D7 In AA0468 Figure 3-9 SRAM Read Access DSP56364 Technical Data.0 4. Rev. Characteristics Symbol Expression2 Min Max Unit 118 TA setup before RD or WR deassertion4 0. 4.1 Freescale Semiconductor 3-15 .25 × TC + 2.

95 MHz). the selection guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode DRAM. Rev.2 DRAM Timing The selection guides provided in Figure 3-11 and Figure 3-14 should be used for primary selection only. running the chip at a slightly lower frequency (e.g. a designer may choose to evaluate whether fewer wait states might be used by determining which timing prevents operation at 100 MHz.10. using faster DRAM (if it becomes available).1 3-16 Freescale Semiconductor . However.External Memory Expansion Port (Port A) 100 A0–A17 AA0–AA3 107 101 102 103 WR 114 RD 119 118 TA 108 111 110 109 112 D0–D23 Data Out AA0469 Figure 3-10 SRAM Write Access 3. and control factors such as capacitive and resistive load to improve overall system performance. As an example. Final selection should be based on the timing provided in the following tables. 4. by using the information in the appropriate table.. DSP56364 Technical Data.

8 ns 133 Column address valid to data valid tAA 1. 3 20 MHz4 30 MHz4 No. For (tRAC ns) exact and detailed timings see the following tables.5 ns (read) DSP56364 Technical Data.5 — 41.7 — ns consecutive accesses of the same direction Page mode cycle time for mixed (read 1.7 — and write) accesses 132 CAS assertion to data valid (read) tCAC TC − 7. 100 80 70 60 Chip Frequency 50 40 66 80 100 120 (MHz) 1 Wait States 3 Wait States 2 Wait States 4 Wait States AA0472 Figure 3-11 DRAM Page Mode Wait States Selection Guide Table 3-9 DRAM Page Mode Timings. Characteristics Symbol Expression Unit Min Max Min Max 131 Page mode cycle time for two tPC 2 × TC 100. 2. 4.5 × TC − 7.5 — 67.0 — 66.1 Freescale Semiconductor 3-17 .5 — 25.25 × TC 62.5 — 42. Rev. One Wait State (Low-Power Applications)1. External Memory Expansion Port (Port A) DRAM Type Note: This figure should be use for primary selection.5 — 42.

0 — 12.8 — 4.External Memory Expansion Port (Port A) Table 3-9 DRAM Page Mode Timings.7 — 29.5 135.6 — ns 145 CAS assertion to WR deassertion tWCH 0.5 × TC − 4.0 96.0 — ns 151 WR assertion to CAS assertion tWCS TC − 4.25 × TC − 6.5 — 21.3 — ns deassertion5 BRW[1:0] = 00 • BRW[1:0] = 01 3.0 33.1 3-18 Freescale Semiconductor .5 × TC − 4.0 81.7 8.2 — 54.5 — ns • BRW[1:0] = 11 6.0 — 12.0 206.0 — ns 138 Last CAS deassertion to RAS tCRP 1.7 — ns deassertion 137 CAS assertion pulse width tCAS 0.3 45.5 — 52.3 83.2 20.0 33.0 8.0 — ns valid 142 Last column address valid to RAS tRAL 2 × TC − 4.0 — 62.5 — ns 146 WR assertion pulse width tWP 1. 3 (continued) 20 MHz4 30 MHz4 No.8 — 12.0 — ns 149 Data valid to CAS assertion (Write) tDS 0.5 — 21.75 × TC − 4.7 — ns 140 Column address valid to CAS tASC 0.5 102.7 — ns assertion 141 CAS assertion to column address not tCAH 0.0 — 0.75 × TC − 4.1 — ns 139 CAS deassertion pulse width tCP 0.75 × TC − 4.75 × TC − 4.0 — ns deassertion 136 Previous CAS deassertion to RAS tRHCP 2 × TC − 4. Rev.75 × TC − 3.3 83.25 × TC − 6.5 — 45.5 × TC − 4.2 — ns • BRW[1:0] = 10 4.25 × TC − 4.5 — 21.0 — ns DSP56364 Technical Data.75 × TC − 4.3 — ns 150 CAS assertion to data not valid (write) tDH 0.0 156.5 70.5 — 202.0 21.0 306.0 33.0 — ns 148 WR assertion to CAS deassertion tCWL 1.7 — 21.25 × TC − 3.2 — ns 144 CAS deassertion to WR assertion tRCH 0.0 21.5 × TC − 4.5 — ns 147 Last WR assertion to RAS deassertion tRWL 1.5 — 4. 4.0 96. 2.0 — 62.75 × TC − 6.8 33.7 — ns deassertion 143 WR deassertion to CAS assertion tRCS 0.5 — 21.25 × TC – 6.0 33.2 — 54.0 — ns (read hold time) 135 Last CAS assertion to RAS tRSH 0.75 × TC − 4. Characteristics Symbol Expression Unit Min Max Min Max 134 CAS deassertion to data not valid tOFF 0. One Wait State (Low-Power Applications)1.

Characteristics Symbol Expression Unit Min Max Min Max 152 Last RD assertion to RAS deassertion tROH 1.0 — ns 153 RD assertion to data valid tGA TC − 7. therefore.3 37. Some of the timings are better for specific cases (e.0 71. 6 RD deassertion will always occur after CAS deassertion. 4. External Memory Expansion Port (Port A) Table 3-9 DRAM Page Mode Timings. DSP56364 Technical Data.7 — ns 156 WR deassertion to data high 0.0 — 46. 3 (continued) 20 MHz4 30 MHz4 No.5 — 25.0 — 0. 2 The refresh period is specified in the DCR.8 ns 154 RD deassertion to data not valid 6 tGZ 0.5 — 8.).3 ns impedance 1 The number of wait states for Page mode access is specified in the DCR. 4 Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See Figure 3-14.5 — 42. the restricted timing is tOFF and not tGZ. One Wait State (Low-Power Applications)1.2 — 24.g. 3 All the timings are calculated for the worst case.75 × TC − 0. Rev.0 — ns 155 WR assertion to data active 0. 5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. 2..5 × TC − 4. tPC equals 2 × TC for read-after-read or write-after-write sequences).1 Freescale Semiconductor 3-19 .25 × TC — 12.

2 — — ns 1.0 × TC − 6.0 45.1 3-20 Freescale Semiconductor . 3.6 — ns 146 WR assertion pulse width tWP 2.5 × TC − 3.7 3.0 11.0 18.External Memory Expansion Port (Port A) Table 3-10 DRAM Page Mode Timings.9 — 2.5 × TC − 4.9 — ns 142 Last column address valid to RAS tRAL 3 × TC − 4.5 — 33.0 — 0.4 — — ns 2.5 — ns 141 CAS assertion to column address not valid tCAH 1.5 — 14.6 — ns deassertion 137 CAS assertion pulse width tCAS 1.0 22. Characteristics Symbol Expression5 Unit Min Max Min Max 131 Page mode cycle time for two consecutive tPC 2 × TC 45.5 × TC − 6.2 — 36.8 15.9 — 11.8 — ns 144 CAS deassertion to WR assertion tRCH 0.5 × TC − 4.0 — ns • BRW[1:0] = 01 3.75 × TC − 4.5 — 17.5 — ns accesses of the same direction Page mode cycle time for mixed (read and 1.5 — — — 12.25 × TC − 3.0 41. 4.9 — ns 136 Previous CAS deassertion to RAS tRHCP 3.0 62.0 — ns time) 135 Last CAS assertion to RAS deassertion tRSH 1.2 18.5 × TC − 7.25 × TC − 4.1 — 34.5 × TC − 6.5 — ns deassertion 143 WR deassertion to CAS assertion tRCS 1.3 — ns 139 CAS deassertion pulse width tCP 1. Rev.5 — 17.5 33.5 — 30.5 — — — 24.8 ns 134 CAS deassertion to data not valid (read hold tOFF 0.75 × TC − 4.6 — ns 140 Column address valid to CAS assertion tASC TC − 4.6 — ns 145 CAS assertion to WR deassertion tWCH 1.0 24.5 × TC − 4.5 — 26.5 × TC − 7. 2.4 — ns write) accesses 132 CAS assertion to data valid (read) tCAC 1.0 14.5 × TC − 6.3 ns 133 Column address valid to data valid (read) tAA 2.2 — 8.5 — 15.4 — 37.25 × TC − 4.8 — ns • BRW[1:0] = 10 4.5 × TC − 6.5 × TC − 6.3 — ns • BRW[1:0] = 11 6.0 47.4 — 50. 4 66 MHz 80 MHz No.8 — ns DSP56364 Technical Data.4 — 19.25 × TC 41.0 92.2 — 37.0 22.8 — 75.8 — ns 138 Last CAS deassertion to RAS deassertion6 • BRW[1:0] = 00 tCRP 2.7 — 14. Two Wait States1.1 — 11.

4 ns 154 RD deassertion to data not valid7 tGZ 0. 3 The asynchronous delays specified in the expressions are valid for DSP56364.25 × TC − 3.3 33.25 × TC — 3. Rev.1 — ns 150 CAS assertion to data not valid (write) tDH 1.3 33.0 — ns 149 Data valid to CAS assertion (write) tDS 0. 5 All the timings are calculated for the worst case. External Memory Expansion Port (Port A) Table 3-10 DRAM Page Mode Timings. 4 There are no DRAMs fast enough to fit to two wait states Page mode @ 100 MHz (See Figure 3-11).75 × TC − 0. therefore. 4. Characteristics Symbol Expression5 Unit Min Max Min Max 147 Last WR assertion to RAS deassertion tRWL 2.6 — 27.1 — 9. 7 RD deassertion will always occur after CAS deassertion.0 — — ns 1.1 — — — ns 0. Some of the timings are better for specific cases (e.8 — ns 148 WR assertion to CAS deassertion tCWL 2.75 × TC − 6.3 11.75 × TC − 4.8 — 3.9 — ns 151 WR assertion to CAS assertion tWCS TC − 4.g.0 — — 0.9 — 8. the restricted timing is tOFF and not tGZ. 3.3 10.2 — ns 152 Last RD assertion to RAS deassertion tROH 2.5 × TC − 4. DSP56364 Technical Data.7 0.5 × TC − 4. Two Wait States1..25 × TC − 3.4 — 26.75 × TC − 7. tPC equals 3 × TC for read-after-read or write-after-write sequences).5 — 19.9 — 27. 4 (continued) 66 MHz 80 MHz No.5 — — — 15.3 — ns 153 RD assertion to data valid tGA 1.0 22.1 — ns 156 WR deassertion to data high impedance 0.0 33.1 ns 1 The number of wait states for Page mode access is specified in the DCR. 2 The refresh period is specified in the DCR.1 Freescale Semiconductor 3-21 . 2.5 — 17. 6 BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access.0 — ns 155 WR assertion to data active 0.75 × TC − 4.0 — 0.

0 3.0 — ns 136 Previous CAS deassertion to RAS deassertion tRHCP 4.5 — ns 139 CAS deassertion pulse width tCP 1.0 — 13.0 11.0 ns 134 CAS deassertion to data not valid (read hold time) tOFF 0.2 18. 3 No.0 61.1 3-22 Freescale Semiconductor .3 — ns 146 WR assertion pulse width tWP 3.0 6.0 — — ns • BRW[1:0] = 10 4.0 — 23.0 16.0 — ns 150 CAS assertion to data not valid (write) tDH 2.0 — ns 140 Column address valid to CAS assertion tASC TC − 4.25 × TC − 4. Characteristics Symbol Expression4 Min Max Unit 131 Page mode cycle time for two consecutive accesses of the tPC 2 × TC 40.2 — ns DSP56364 Technical Data.0 — ns 141 CAS assertion to column address not valid tCAH 2.5 × TC − 4.75 × TC − 4.5 × TC − 4.25 × TC − 6.2 — ns 149 Data valid to CAS assertion (write) tDS 0.0 — ns 137 CAS assertion pulse width tCAS 2 × TC − 4.25 × TC 35.0 ns 133 Column address valid to data valid (read) tAA 3 × TC − 7.0 — ns 143 WR deassertion to CAS assertion tRCS 1.25 × TC − 4.3 28.75 × TC − 6.5 — ns 144 CAS deassertion to WR assertion tRCH 0.0 41. 4.0 — ns 142 Last column address valid to RAS deassertion tRAL 4 × TC − 4.0 — ns 135 Last CAS assertion to RAS deassertion tRSH 2.0 41.5 × TC − 4.0 — ns same direction Page mode cycle time for mixed (read and write) accesses 1.0 — ns 138 Last CAS deassertion to RAS assertion5 • BRW[1:0] = 00 tCRP 2.0 8.0 21.5 — ns • BRW[1:0] = 11 6.5 × TC − 4.5 × TC − 4.25 × TC − 4.75 × TC − 4.0 — ns 151 WR assertion to CAS assertion tWCS 1.5 — ns 147 Last WR assertion to RAS deassertion tRWL 3.0 21. 2. Rev.External Memory Expansion Port (Port A) Table 3-11 DRAM Page Mode Timings.25 × TC − 4.5 × TC − 4.0 21.2 — ns 148 WR assertion to CAS deassertion tCWL 3.3 33.5 30.0 — 132 CAS assertion to data valid (read) tCAC 2 × TC − 7.0 36.3 8.5 × TC − 4.0 1.75 × TC − 6.75 × TC − 6.5 — ns 145 CAS assertion to WR deassertion tWCH 2.0 — — ns • BRW[1:0] = 01 3. Three Wait States1.

Three Wait States1.0 ns 154 RD deassertion to data not valid6 tGZ 0.0 — — ns • BRW[1:0] = 01 4. 2. 4. Some of the timings are better for specific cases (e. Four Wait States1. 1.0 16.25 × TC 45. 6 RD deassertion will always occur after CAS deassertion. 3 No. Characteristics Symbol Expression4 Min Max Unit 152 Last RD assertion to RAS deassertion tROH 3. External Memory Expansion Port (Port A) Table 3-11 DRAM Page Mode Timings.0 — ns 132 CAS assertion to data valid (read) tCAC 2.0 — 30.0 56.5 × TC − 4.0 46.g.3 7.0 — ns 155 WR assertion to data active 0. 3 The asynchronous delays specified in the expressions are valid for DSP56364. Rev.0 — ns 138 Last CAS deassertion to RAS assertion5 • BRW[1:0] = 00 tCRP 2.0 66. 2.0 21.0 — ns 136 Previous CAS deassertion to RAS deassertion tRHCP 6 × TC − 4.5 × TC − 4.2 — ns 156 WR deassertion to data high impedance 0.0 31. Page mode cycle time for mixed (read and write) accesses.1 Freescale Semiconductor 3-23 . the restricted timing is tOFF and not tGZ. 2 The refresh period is specified in the DCR.0 — ns DSP56364 Technical Data.0 31.25 × TC − 6.0 — ns 153 RD assertion to data valid tGA 2. therefore. Characteristics Symbol Expression4 Min Max Unit 131 Page mode cycle time for two consecutive accesses of the tPC 2 × TC 50.0 — ns same direction. tPC equals 4 ¥ TC for read-after-read or write-after-write sequences).75 × TC − 6.5 ns 134 CAS deassertion to data not valid (read hold time) tOFF 0.0 — ns 135 Last CAS assertion to RAS deassertion tRSH 3.5 — ns 139 CAS deassertion pulse width tCP 2 × TC − 4.75 × TC − 0.5 ns 1 The number of wait states for Page mode access is specified in the DCR.75 × TC − 7.0 — 20.5 ns 133 Column address valid to data valid (read) tAA 3.25 × TC — 2.5 — ns • BRW[1:0] = 11 7.0 — ns 137 CAS assertion pulse width tCAS 2. 4 All the timings are calculated for the worst case.5 × TC − 4.0 — 18.75 × TC − 7. Table 3-12 DRAM Page Mode Timings. 3 (continued) No. 5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access.5 × TC − 7..0 — — ns • BRW[1:0] = 10 5.25 × TC − 6.25 × TC − 6.

2 The refresh period is specified in the DCR.0 — ns 153 RD assertion to data valid tGA 3. DSP56364 Technical Data.0 6. Characteristics Symbol Expression4 Min Max Unit 140 Column address valid to CAS assertion tASC TC − 4.0 — ns 141 CAS assertion to column address not valid tCAH 3.2 — ns 152 Last RD assertion to RAS deassertion tROH 4.0 — ns 151 WR assertion to CAS assertion tWCS 1. therefore.0 8.2 — ns 156 WR deassertion to data high impedance 0.0 8.5 × TC − 4.75 × TC − 4. 2.g. Four Wait States1.5 × TC − 4.25 × TC — 2.75 × TC − 0.5 × TC − 4. tPC equals 3 × TC for read-after-read or write-after-write sequences).3 8.External Memory Expansion Port (Port A) Table 3-12 DRAM Page Mode Timings.5 — ns 144 CAS deassertion to WR assertion tRCH 1. Some of the timings are better for specific cases (e. the restricted timing is tOFF and not tGZ. 5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access.0 1.25 × TC − 4.0 41.5 ns 154 RD deassertion to data not valid6 tGZ 0.0 — 25. Rev.5 × TC − 4.0 31.3 7. 3 (continued) No.3 43.0 — ns 155 WR assertion to data active 0.5 × TC − 4.75 × TC − 4.5 — ns 145 CAS assertion to WR deassertion tWCH 3.0 — ns 150 CAS assertion to data not valid (write) tDH 3..3 33.5 ns 1 The number of wait states for Page mode access is specified in the DCR.2 — ns 149 Data valid to CAS assertion (write) tDS 0. 6 RD deassertion will always occur after CAS deassertion. 4.0 — ns 143 WR deassertion to CAS assertion tRCS 1.2 28.25 × TC − 4.25 × TC − 4. 4 All the timings are calculated for the worst case.5 — ns 147 Last WR assertion to RAS deassertion tRWL 4.0 46.0 31.3 — ns 146 WR assertion pulse width tWP 4.2 — ns 148 WR assertion to CAS deassertion tCWL 3.5 40. 3 The asynchronous delays specified in the expressions are valid for DSP56364.1 3-24 Freescale Semiconductor .0 — ns 142 Last column address valid to RAS deassertion tRAL 5 × TC − 4.25 × TC − 4.25 × TC − 7.

1 Freescale Semiconductor 3-25 . External Memory Expansion Port (Port A) RAS 136 131 135 CAS 137 139 138 140 141 142 Row Column Column Last Column A0–A17 Add Address Address Address 151 144 143 145 147 WR 146 148 RD 155 156 150 149 D0–D7 Data Out Data Out Data Out AA0473 Figure 3-12 DRAM Page Mode Write Accesses DSP56364 Technical Data. 4. Rev.

Rev.External Memory Expansion Port (Port A) RAS 136 131 135 CAS 137 139 138 140 141 142 Row Column Column Last Column A0–A17 Add Address Address Address 143 WR 132 133 152 153 RD 134 154 D0–D7 Data In Data In Data In AA0474 Figure 3-13 DRAM Page Mode Read Accesses DSP56364 Technical Data.1 3-26 Freescale Semiconductor . 4.

0 158. External Memory Expansion Port (Port A) DRAM Type (tRAC ns) Note: This figure should be use for primary selection. 4. Characteristics3 Symbol Expression Unit Min Max Min Max 157 Random read or write cycle time tRC 5 × TC 250.5 — 42.25 × TC − 4. Rev.3 — ns 164 CAS assertion to RAS deassertion tRSH 1.75 × TC − 4.0 83.2 ns 159 CAS assertion to data valid (read) tCAC 1.0 — 166.3 — ns 163 RAS assertion pulse width tRAS 3.0 83.5 — 104.75 × TC − 7.5 — 55.0 — ns (read hold time) 162 RAS deassertion to RAS assertion tRP 1.5 × TC − 7.25 × TC − 7.1 Freescale Semiconductor 3-27 .5 — 54.0 — 84.2 ns 160 Column address valid to data valid tAA 1.3 — ns DSP56364 Technical Data. 2 20 MHz4 30 MHz4 No.75 × TC − 4. 100 80 70 60 Chip Frequency 50 120 (MHz) 40 66 80 100 4 Wait States 11 Wait States 8 Wait States 15 Wait States AA0475 Figure 3-14 DRAM Out-of-Page Wait States Selection Guide Table 3-13 DRAM Out-of-Page and Refresh Timings.5 — 67.5 ns (read) 161 CAS deassertion to data not valid tOFF 0.5 — 130. For exact and detailed timings see the following tables.7 — ns 158 RAS assertion to data valid (read) tRAC 2.5 — 54.0 — 34. Four Wait States1.0 — 0.

0 — 62.0 83.0 77.5 — 71.25 × TC − 4.25 × TC − 4.3 208.25 × TC − 4.5 — 54.0 — ns 170 CAS deassertion pulse width tCP 1.8 — ns 182 WR assertion pulse width tWP 4.0 108.3 — ns 172 RAS assertion to row address not valid tRAH 1. Four Wait States1.2 — 46.0 158.25 × TC − 4.0 58.0 158.3 — ns 187 RAS assertion to data not valid (write) tDHR 3.8 — ns 181 RAS assertion to WR deassertion tWCR 3 × TC − 4.5 — ns 183 WR assertion to RAS deassertion tRWL 4.25 × TC − 4.7 8.0 108.5 — 54.3 233.1 3-28 Freescale Semiconductor .3 — ns valid 176 Column address valid to RAS tRAL 2 × TC − 4.3 — ns 171 Row address valid to RAS assertion tASR 1.25 × TC ± 2 60.5 × TC − 4.5 — 54.8 — 45.2 — 154.25 × TC − 4.0 52.5 64.75 × TC − 3.5 — 87.5 × TC ± 2 73.7 — ns 167 RAS assertion to CAS assertion tRCD 1.0 133.7 — ns 173 Column address valid to CAS tASC 0.3 — ns assertion 174 CAS assertion to column address not tCAH 1.8 — 4.5 — 4.6 — ns 180 CAS assertion to WR deassertion tWCH 1.0 83.75 × TC − 4.0 83.5 × TC − 4.25 × TC − 4.5 — 104. 4.75 × TC − 4.75 × TC − 4.7 43.3 — ns DSP56364 Technical Data. 2 (continued) 20 MHz4 30 MHz4 3 No.7 — ns deassertion 177 WR deassertion to CAS assertion tRCS 1.0 58.0 8.5 — 37.0 83.5 — 104.75 × TC − 4.2 — ns 178 CAS deassertion to WR assertion tRCH 0.75 × TC − 4.5 220.0 ns 168 RAS assertion to column address valid tRAD 1.5 — 145.75 × TC − 4.0 48.8 — 21.5 — 71.2 — 137.5 39.7 33.4 — ns 185 Data valid to CAS assertion (write) tDS 2. Rev.3 — ns valid 175 RAS assertion to column address not tAR 3.0 — ns 186 CAS assertion to data not valid (write) tDH 1.5 × TC − 3.5 — 54.External Memory Expansion Port (Port A) Table 3-13 DRAM Out-of-Page and Refresh Timings.8 — 95.7 ns 169 CAS deassertion to RAS assertion tCRP 2.2 145.25 × TC − 3.3 — ns 179 RAS deassertion to WR assertion tRRH 0. Characteristics Symbol Expression Unit Min Max Min Max 165 RAS assertion to CAS deassertion tCSH 2.0 — ns 184 WR assertion to CAS deassertion tCWL 4.2 70.5 — 37.0 96.8 71.7 — ns 166 CAS assertion pulse width tCAS 1.25 × TC − 4.

6 — — ns 2.9 ns 159 CAS assertion to data valid (read) tCAC 2. 2 66 MHz 80 MHz No.4 — 112.25 × TC − 6.5 — 26.7 — ns (refresh) 191 RD assertion to RAS deassertion tROH 4.75 × TC − 6. therefore.5 — 8.0 — 12.5 — 40.0 — 0.7 — ns 189 CAS assertion to RAS assertion tCSR 0.5 — 64. 4 Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (See Figure 3-17).0 221.25 × TC − 4.25 × TC — 12.0 83.5 — — — 31.0 — 146.7 — 95.7 — ns (refresh) 190 RAS deassertion to CAS assertion tRPC 1.0 — ns 192 RD assertion to data valid tGA 4 × TC − 7. 2 (continued) 20 MHz4 30 MHz4 3 No.25 × TC − 7.3 ns impedance 1 The number of wait states for out of page access is specified in the DCR. Four Wait States1.5 — 37.6 ns 160 Column address valid to data valid tAA 3 × TC − 7.0 45.25 × TC − 4. Rev.0 58.3 145.5 — ns 158 RAS assertion to data valid (read) tRAC 4.0 — — ns (read) 3 × TC − 6.5 × TC − 4.7 — ns 195 WR deassertion to data high 0.0 — 0.0 ns 161 CAS deassertion to data not valid tOFF 0.0 — ns 194 WR assertion to data active 0. Characteristics3 Symbol Expression4 Unit Min Max Min Max 157 Random read or write cycle time tRC 9 × TC 136.2 — 24. Characteristics Symbol Expression Unit Min Max Min Max 188 WR assertion to CAS assertion tWCS 3 × TC − 4.0 21.3 37.2 — 36. Table 3-14 DRAM Out-of-Page and Refresh Timings.8 ns 193 RD deassertion to data not valid3 tGZ 0. Eight Wait States1.5 × TC − 4.5 — 192.5 — — — 21.75 × TC − 7. External Memory Expansion Port (Port A) Table 3-13 DRAM Out-of-Page and Refresh Timings.5 — — ns 4.9 — ns DSP56364 Technical Data.1 Freescale Semiconductor 3-29 .75 × TC − 0. 4. 3 RD deassertion will always occur after CAS deassertion.75 × TC − 4.6 — ns 163 RAS assertion pulse width tRAS 5. 2 The refresh period is specified in the DCR.5 — 125. the restricted timing is t OFF and not tGZ.1 — 67.0 — ns (read hold time) 162 RAS deassertion to RAS assertion tRP 3.5 — — — 52.

9 ns 169 CAS deassertion to RAS assertion tCRP 4.0 7. 2 (continued) 66 MHz 80 MHz No.3 — ns 181 RAS assertion to WR deassertion tWCR 5.8 — ns 183 WR assertion to RAS deassertion tRWL 8. Characteristics3 Symbol Expression4 Unit Min Max Min Max 164 CAS assertion to RAS deassertion tRSH 3.75 × TC − 4.25 × TC − 4.1 — 64.1 — 92.9 23.0 45.0 — 55.75 × TC ± 2 24. 4.4 — ns DSP56364 Technical Data.5 — 21.5 124.75 × TC − 4.6 — ns 185 Data valid to CAS assertion (write) tDS 4.5 × TC ± 2 35. Eight Wait States1.4 — ns assertion 174 CAS assertion to column address not tCAH 3.2 — 36.75 × TC − 4.7 15.2 41.1 3-30 Freescale Semiconductor .8 26.25 × TC − 4.6 — ns valid 175 RAS assertion to column address not tAR 5.3 — 101.7 — 30.3 113.1 — ns 184 WR assertion to CAS deassertion tCWL 7.0 45.3 ns 168 RAS assertion to column address valid tRAD 1.0 68.75 × TC − 4.75 × TC − 4.9 — ns 173 Column address valid to CAS tASC 0.0 83.3 33.9 39.0 59.1 — ns 180 CAS assertion to WR deassertion tWCH 3 × TC − 4.3 — 105.6 — ns 172 RAS assertion to row address not valid tRAH 1.0 — ns deassertion 177 WR deassertion to CAS assertion tRCS 2 × TC − 3.75 × TC − 4.1 — — — ns 0.5 × TC − 4.3 — 33.0 68.75 × TC − 4.0 — — 0.2 — 36.25 × TC − 3.4 — ns 171 Row address valid to RAS assertion tASR 3.External Memory Expansion Port (Port A) Table 3-14 DRAM Out-of-Page and Refresh Timings.2 — ns 178 CAS deassertion to WR5 assertion tRCH 1.1 — ns 170 CAS deassertion pulse width tCP 2.9 — ns 179 RAS deassertion to WR5 assertion tRRH 0.5 — 17.1 — ns 167 RAS assertion to CAS assertion tRCD 2.1 — 67.2 79. Rev.4 — 5.2 — 11.8 — 49.5 28.25 × TC − 3.5 × TC − 4.2 — 36.6 — ns 182 WR assertion pulse width tWP 8.75 × TC − 4.7 0.0 37.5 19.25 × TC − 4.9 — ns valid 176 Column address valid to RAS tRAL 4 × TC − 4.0 22.0 — 55.6 — ns 165 RAS assertion to CAS deassertion tCSH 4.9 29.0 30.0 45.0 56.25 × TC − 4.25 × TC − 3.5 — ns 166 CAS assertion pulse width tCAS 2.1 — 24.6 — 46.25 × TC − 4.3 128.

5 — 17. 3 RD deassertion will always occur after CAS deassertion.0 22.8 — 102.5 × TC − 7. Characteristics3 Symbol Expression4 Unit Min Max Min Max 186 CAS assertion to data not valid (write) tDH 3.5 ns 160 Column address valid to data valid (read) tAA 4.5 × TC − 6.0 124.0 — 30. 2 No. the restricted timing is t OFF and not tGZ.25 × TC − 4. therefore. 2 (continued) 66 MHz 80 MHz No.8 — ns (refresh) 190 RAS deassertion to CAS assertion tRPC 1.0 — 0. Eight Wait States1.75 × TC − 0.75 × TC − 4.3 79.1 — 67.0 0.3 ns 193 RD deassertion to data not valid3 tGZ 0.75 × TC − 4.0 — 38.25 × TC − 4.3 11.5 × TC − 4.1 — 9.5 × TC − 7.0 — 64.25 × TC − 7.0 18. 4 The asynchronous delays specified in the expressions are valid for DSP56364.0 — ns 158 RAS assertion to data valid (read) tRAC 6.0 83. Table 3-15 DRAM Out-of-Page and Refresh Timings.0 — ns 194 WR assertion to data active 0.5 — — — 87.5 ns 159 CAS assertion to data valid (read) tCAC 3.1 Freescale Semiconductor 3-31 .1 — ns 195 WR deassertion to data high 0.0 45.5 — 106.3 — ns 192 RD assertion to data valid tGA 7.1 ns impedance 1 The number of wait states for out-of-page access is specified in the DCR.8 — 3.6 — ns 187 RAS assertion to data not valid (write) tDHR 5. Eleven Wait States1.9 — ns 188 WR assertion to CAS assertion tWCS 5.5 — ns 163 RAS assertion pulse width tRAS 7.75 × TC − 4. 5 Either t RCH or tRRH must be satisfied for read cycles.1 — — ns 7.5 × TC − 4. Rev.5 × TC − 4.0 73.0 — ns 162 RAS deassertion to RAS assertion tRP 4.75 × TC − 7. 2 The refresh period is specified in the DCR.7 — 14.0 38.2 — 36.0 ns 161 CAS deassertion to data not valid (read hold time) tOFF 0. Characteristics3 Symbol Expression4 Min Max Unit 157 Random read or write cycle time tRC 12 × TC 120.5 — ns DSP56364 Technical Data.5 — ns 189 CAS assertion to RAS assertion tCSR 1.0 — 55.25 × TC — 3. 4.9 — ns (refresh) 191 RD assertion to RAS deassertion tROH 8. External Memory Expansion Port (Port A) Table 3-14 DRAM Out-of-Page and Refresh Timings.

5 × TC ± 4.5 — ns 167 RAS assertion to CAS assertion tRCD 2.75 × TC − 4.5 × TC − 4.75 × TC − 4.5 — ns 173 Column address valid to CAS assertion tASC 0.5 × TC − 4.5 — ns DSP56364 Technical Data.0 38.5 × TC − 4.5 — ns 172 RAS assertion to row address not valid tRAH 1.0 48.25 × TC − 4.5 — ns 175 RAS assertion to column address not valid tAR 7.2 45.8 — ns 182 WR assertion pulse width tWP 11.0 23.5 — ns 165 RAS assertion to CAS deassertion tCSH 6.0 38.5 × TC − 4.0 29.5 110.1 3-32 Freescale Semiconductor .2 70.5 — ns 183 WR assertion to RAS deassertion tRWL 11.0 11.0 73.5 — ns 171 Row address valid to RAS assertion tASR 4.75 × TC − 4.0 33.3 103.0 48.0 56.2 — ns 185 Data valid to CAS assertion (write) tDS 5.75 × TC − 4.8 — ns 181 RAS assertion to WR deassertion tWCR 7.0 48.0 × TC − 4.0 13.5 — ns 180 CAS assertion to WR deassertion tWCH 5 × TC − 4.25 × TC − 4.2 — ns 184 WR assertion to CAS deassertion tCWL 10.75 × TC − 4.25 × TC − 4.25 × TC − 4.0 3.75 × TC − 4.0 26.0 58.5 — ns 176 Column address valid to RAS deassertion tRAL 6 × TC − 4.3 113.5 — ns 179 RAS deassertion to WR5 assertion tRRH 0.5 — ns 186 CAS assertion to data not valid (write) tDH 5.25 × TC − 4.0 ns 168 RAS assertion to column address valid tRAD 1.5 — ns 170 CAS deassertion pulse width tCP 4.0 53.75 × TC − 4.25 × TC − 4. Eleven Wait States1. Characteristics3 Symbol Expression4 Min Max Unit 164 CAS assertion to RAS deassertion tRSH 5.0 21.5 — ns 174 CAS assertion to column address not valid tCAH 5.25 × TC − 2.5 21.3 60.0 0. Rev.75 × TC ± 4.7 — ns 189 CAS assertion to RAS assertion (refresh) tCSR 1. 4.0 13.0 — ns 190 RAS deassertion to CAS assertion (refresh) tRPC 2.0 73.0 — ns 177 WR deassertion to CAS assertion tRCS 3.5 — ns 166 CAS assertion pulse width tCAS 3.75 × TC − 4.75 × TC − 4.0 53.0 — ns 178 CAS deassertion to WR5 assertion tRCH 1. 2 (continued) No.25 × TC − 4.0 13.5 — ns 187 RAS assertion to data not valid (write) tDHR 7.5 ns 169 CAS deassertion to RAS assertion tCRP 5.External Memory Expansion Port (Port A) Table 3-15 DRAM Out-of-Page and Refresh Timings.75 × TC − 4.5 — ns 188 WR assertion to CAS assertion tWCS 6.

0 37.1 Freescale Semiconductor 3-33 .75 × TC ± 2 25. Characteristics3 Symbol Expression4 Min Max Unit 191 RD assertion to RAS deassertion tROH 11.75 × TC − 5.5 × TC ± 2 33.3 ns 161 CAS deassertion to data not valid (read hold time) tOFF 0.0 — ns 158 RAS assertion to data valid (read) tRAC 8.25 × TC − 5.75 × TC − 4.5 — ns 166 CAS assertion pulse width tCAS 4.0 73. Fifteen Wait States1.75 × TC − 4.75 × TC − 4.0 93. the restricted timing is tOFF and not tGZ.0 78.5 — ns 163 RAS assertion pulse width tRAS 9.8 ns 160 Column address valid to data valid (read) tAA 5.25 × TC — 2.5 — ns DSP56364 Technical Data.5 ns 169 CAS deassertion to RAS assertion tCRP 7.7 — 41.0 — ns 162 RAS deassertion to RAS assertion tRP 6.25 × TC − 4. 5 Either tRCH or tRRH must be satisfied for read cycles. Rev.0 43.5 — ns 164 CAS assertion to RAS deassertion tRSH 6.5 × TC − 4.5 — ns 171 Row address valid to RAS assertion tASR 6. External Memory Expansion Port (Port A) Table 3-15 DRAM Out-of-Page and Refresh Timings.0 111.0 ns 193 RD deassertion to data not valid3 tGZ 0.0 58. therefore.0 23. Table 3-16 DRAM Out-of-Page and Refresh Timings.0 — 93.25 × TC − 4. 3 RD deassertion will always occur after CAS deassertion.0 — ns 194 WR assertion to data active 0.5 — ns 172 RAS assertion to row address not valid tRAH 2.0 ns 168 RAS assertion to column address valid tRAD 2. 2 No. 4 The asynchronous delays specified in the expressions are valid for DSP56364.2 — ns 195 WR deassertion to data high impedance 0.5 — ns 167 RAS assertion to CAS assertion tRCD 3. 4.0 0.0 58.8 ns 159 CAS assertion to data valid (read) tCAC 4.3 7.75 × TC − 4. 2 The refresh period is specified in the DCR. Eleven Wait States1. 2 (continued) No.25 × TC − 4.0 58. Characteristics3 Symbol Expression Min Max Unit 157 Random read or write cycle time tRC 16 × TC 160.25 × TC − 4.5 ns 1 The number of wait states for out-of-page access is specified in the DCR.7 — 76.5 — ns 170 CAS deassertion pulse width tCP 6.5 — ns 165 RAS assertion to CAS deassertion tCSH 8.0 — ns 192 RD assertion to data valid tGA 10 × TC − 7.5 × TC − 5.0 58.5 29.75 × TC − 0.7 — 49.25 × TC − 4.

2 — ns 185 Data valid to CAS assertion (write) tDS 8.0 66.0 93.5 ns 1 The number of wait states for out-of-page access is specified in the DCR.5 — ns 188 WR assertion to CAS assertion tWCS 9.75 × TC − 4.75 × TC − 4.7 13.75 × TC − 4.5 × TC − 4.8 — ns 182 WR assertion pulse width tWP 15.75 × TC − 4. 4.5 × TC − 4.0 — ns 190 RAS deassertion to CAS assertion (refresh) tRPC 4.7 — 134.2 55.0 — ns 177 WR deassertion to CAS assertion tRCS 5 × TC − 3.2 — ns 178 CAS deassertion to WR4 assertion tRCH 1.75 × TC − 3.1 3-34 Freescale Semiconductor . Fifteen Wait States1. Characteristics3 Symbol Expression Min Max Unit 173 Column address valid to CAS assertion tASC 0.3 ns 193 RD deassertion to data not valid3 tGZ 0. Rev.5 — ns 176 Column address valid to RAS deassertion tRAL 7 × TC − 4.75 × TC − 4.5 × TC − 4.25 × TC − 2.75 × TC − 4.5 — ns 174 CAS assertion to column address not valid tCAH 6. 3 RD deassertion will always occur after CAS deassertion. 2 The refresh period is specified in the DCR.8 46.5 — ns 183 WR assertion to RAS deassertion tRWL 15.3 7.75 × TC − 0.5 × TC − 4.25 × TC − 4.0 0. 4 Either t RCH or tRRH must be satisfied for read cycles.External Memory Expansion Port (Port A) Table 3-16 DRAM Out-of-Page and Refresh Timings.5 — ns 191 RD assertion to RAS deassertion tROH 15.0 83.0 151.5 150.8 — ns 179 RAS deassertion to WR4 assertion tRRH 0.8 — ns 181 RAS assertion to WR deassertion tWCR 9.2 — ns 195 WR deassertion to data high impedance 0.5 — ns 180 CAS assertion to WR deassertion tWCH 6 × TC − 4.0 3.7 — ns 189 CAS assertion to RAS assertion (refresh) tCSR 1. therefore.3 138.0 93.5 — ns 186 CAS assertion to data not valid (write) tDH 6.2 90.0 11.0 43.5 — ns 175 RAS assertion to column address not valid tAR 9.3 153.3 90.2 — ns 184 WR assertion to CAS deassertion tCWL 14.5 — ns 187 RAS assertion to data not valid (write) tDHR 9. DSP56364 Technical Data.25 × TC − 4.0 — ns 192 RD assertion to data valid tGA 14 × TC − 5.5 × TC − 4.0 — ns 194 WR assertion to data active 0.25 × TC — 2. the restricted timing is tOFF and not tGZ.0 58. 2 (continued) No.25 × TC − 4.0 58.

Rev. External Memory Expansion Port (Port A) 157 162 163 162 165 RAS 167 164 169 168 170 166 CAS 171 173 174 175 A0–A17 Row Address Column Address 172 176 177 179 191 WR 160 168 159 RD 158 193 192 161 Data D0–D7 In AA0476 Figure 3-15 DRAM Out-of-Page Read Access DSP56364 Technical Data. 4.1 Freescale Semiconductor 3-35 .

External Memory Expansion Port (Port A) 157 162 163 162 165 RAS 167 164 169 168 170 166 CAS 171 173 172 174 176 A0–A17 Row Address Column Address 181 175 188 180 182 WR 184 183 RD 187 186 185 195 194 D0–D7 Data Out AA0477 Figure 3-16 DRAM Out-of-Page Write Access DSP56364 Technical Data.1 3-36 Freescale Semiconductor . 4. Rev.

5×TC+189 214 — ns DSP56364 Technical Data.5×TC+102 127 — ns Wide 2. Characteristics Mode Expression Min Max Unit Mode 140 Tolerable spike width on clock or data in — Bypassed — — 0 ns Narrow — — 50 ns Wide — — 100 ns 141 Minimum serial clock cycle = tSPICC(min) Master Bypassed 6×TC+46 106 — ns Narrow 6×TC+152 212 — ns Wide 6×TC+223 283 — ns 142 Serial clock high period Master Bypassed 0.11 Serial Host Interface SPI Protocol Timing Table 3-17 Serial Host Interface SPI Protocol Timing Filter No. Rev.1 Freescale Semiconductor 3-37 . Serial Host Interface SPI Protocol Timing 157 162 163 162 RAS 190 170 165 CAS 189 177 WR AA0478 Figure 3-17 DRAM Refresh Access 3.5×tSPICC –10 131 — ns Slave Bypassed 2. 4.5×tSPICC –10 43 — ns Narrow 0.5×tSPICC –10 96 — ns Wide 0.5×TC+12 37 — ns Narrow 2.

5×TC+12 37 — ns Narrow 2. 0} 30 — ns 149 SCK last sampling edge to data input not valid Master/ Bypassed 2. 4. 0} 10 — ns Wide MAX{(40-TC). Characteristics Mode Expression Min Max Unit Mode 143 Serial clock low period Master Bypassed 0.5×TC+10 35 — ns Slave Narrow 2.5×TC+15 50 — ns CPHA = 0 Narrow 0 0 — ns Wide 0 0 — ns CPHA = 1 Slave Bypassed 10 10 — ns Narrow 0 0 — ns Wide 0 0 — ns 147 Last SCK edge to SS not asserted Slave Bypassed 12 12 — ns Narrow 102 102 — ns Wide 189 189 — ns 148 Data input valid to SCK edge (data input set-up Master/ Bypassed 0 0 — ns time) Slave Narrow MAX{(20-TC).Serial Host Interface SPI Protocol Timing Table 3-17 Serial Host Interface SPI Protocol Timing (continued) Filter No.5×tSPICC –10 96 — ns Wide 0.1 3-38 Freescale Semiconductor .5×TC+102 127 — ns Wide 2.5×tSPICC –10 131 — ns Slave Bypassed 2.5×TC+189 214 — ns 144 Serial clock rise/fall time Master — — — 10 ns Slave — — — 2000 ns 146 SS assertion to first SCK edge Slave Bypassed 3.5×tSPICC –10 43 — ns Narrow 0. Rev.5×TC+50 75 — ns 150 SS assertion to data out active Slave — 2 2 — ns 151 SS deassertion to data high impedance Slave — 9 — 9 ns DSP56364 Technical Data.5×TC+30 55 — ns Wide 2.

4.5 ×tSPICC + 209 — ns 2.5×TC+120 — 145 ns Wide 2.5 ×tSPICC + 174 — ns 2. not 100% tested DSP56364 Technical Data.5×TC+30 55 — ns deasserted (CPHA = 1) Narrow 2.5×TC+136 161 — ns 159 SS deassertion to HREQ output not deasserted Slave — 2.5×TC+43 Wide 0.5×TC+43 162 HREQ in deassertion to last SCK sampling Master — 0 0 — ns edge (HREQ in set-up time) (CPHA = 1) 163 First SCK edge to HREQ in not asserted Master — 0 0 — ns (HREQ in hold time) Note: Periodically sampled.1 Freescale Semiconductor 3-39 . Characteristics Mode Expression Min Max Unit Mode 152 SCK edge to data out valid Master/ Bypassed 2×TC+33 — 53 ns (data out delay time) Slave Narrow 2×TC+123 — 143 ns Wide 2×TC+210 — 230 ns 153 SCK edge to data out not valid Master/ Bypassed TC+5 15 — ns (data out hold time) Slave Narrow TC+55 65 — ns Wide TC+106 116 — ns 154 SS assertion to data out valid Slave — TC+33 — 43 ns (CPHA = 0) 157 First SCK sampling edge to HREQ output Slave Bypassed 2.5×TC+30 — 55 ns deassertion Narrow 2.5×TC+30 55 — ns (CPHA = 0) 160 SS deassertion pulse width (CPHA = 0) Slave — TC+6 16 — ns 161 HREQ in assertion to first SCK edge Master Bypassed 0. Rev.5×TC+217 — 242 ns 158 Last SCK sampling edge to HREQ output not Slave Bypassed 2.5×TC+80 105 — ns Wide 2.5×TC+43 Narrow 0.5 × tSPICC + 121 — ns 2. Serial Host Interface SPI Protocol Timing Table 3-17 Serial Host Interface SPI Protocol Timing (continued) Filter No.

4.1 3-40 Freescale Semiconductor . Rev.Serial Host Interface SPI Protocol Timing SS (Input) 143 141 142 144 144 SCK (CPOL = 0) (Output) 142 141 144 143 144 SCK (CPOL = 1) (Output) 148 149 149 148 MISO MSB LSB (Input) Valid Valid 152 153 MOSI MSB LSB (Output) 161 163 HREQ (Input) AA0271 Figure 3-18 SPI Master Timing (CPHA = 0) DSP56364 Technical Data.

1 Freescale Semiconductor 3-41 . Serial Host Interface SPI Protocol Timing SS (Input) 143 141 142 144 144 SCK (CPOL = 0) (Output) 142 141 143 144 144 SCK (CPOL = 1) (Output) 148 148 149 149 MISO MSB LSB (Input) Valid Valid 152 153 MOSI MSB LSB (Output) 161 162 163 HREQ (Input) AA0272 Figure 3-19 SPI Master Timing (CPHA = 1) DSP56364 Technical Data. 4. Rev.

Serial Host Interface SPI Protocol Timing SS (Input) 143 141 147 142 144 144 160 SCK (CPOL = 0) (Input) 146 142 141 144 143 144 SCK (CPOL = 1) (Input) 154 152 153 153 151 150 MISO (Output) MSB LSB 148 148 149 149 MOSI MSB LSB (Input) Valid Valid 157 159 HREQ (Output) AA0273 Figure 3-20 SPI Slave Timing (CPHA = 0) DSP56364 Technical Data.1 3-42 Freescale Semiconductor . Rev. 4.

4. Serial Host Interface SPI Protocol Timing SS (Input) 143 141 147 142 144 144 SCK (CPOL = 0) (Input) 146 142 144 143 144 SCK (CPOL = 1) (Input) 152 152 153 151 150 MISO (Output) MSB LSB 148 148 149 149 MOSI MSB LSB (Input) Valid Valid 157 158 HREQ (Output) AA0274 Figure 3-21 SPI Slave Timing (CPHA = 1) DSP56364 Technical Data.1 Freescale Semiconductor 3-43 . Rev.

3 — μs 173 Start condition set-up time TSU.9 μs 181 Stop condition set-up time TSU.DAT 0.3 — μs 177 SCL and SDA rise time TR — 1000 20 + 0.5 — MHz • Narrow filters enabled 11.0 — 0.Serial Host Interface (SHI) I2C Protocol Timing 3.7 — MHz • Wide filters enabled 13.0 — MHz 184 HREQ in deassertion to last SCL edge tSU.12 Serial Host Interface (SHI) I2C Protocol Timing Table 3-18 SHI I2C Protocol Timing Standard I2C1 Standard-Mode Fast-Mode Unit Symbol/ No.1 3-44 Freescale Semiconductor . Characteristics Expression Min Max Min Max Tolerable spike width on SCL or SDA — • Filters bypassed — 0 — 0 ns • Narrow filters enabled — 50 — 50 ns • Wide filters enabled — 100 — 100 ns 171 SCL clock frequency FSCL — 100 — 400 kHz 172 Bus free time TBUF 4.STO 4.6 — μs 175 SCL low period TLOW 4.1 × Cb 300 ns 178 SCL and SDA fall time TF — 300 20 + 0.7 — 1. 4.STA 4.3 — μs 176 SCL high period THIGH 4.0 — 0.6 — 28.0 — 0.7 — 0. Rev.6 — μs 174 Start condition hold time THD.RQI 0.7 — 1.STA 4.DAT 250 — 100 — ns 180 Data hold time THD.0 — 1.0 — 0.0 0.1 — 61.8 — 39.0 — ns (HREQ in set-up time) DSP56364 Technical Data.1 × Cb 300 ns 179 Data set-up time TSU.6 — μs 182 Capacitive load for each line Cb — 400 — 400 pF 183 DSP clock frequency FDSP • Filters bypassed 10.

T I CCP.5 × TI2CCP - 0. A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected.RQI ns 0.12.5 × TC . When HRS is cleared.RQO ns deassertion • Filters bypassed 2 × TC + 30 — 50 — 50 ns • Narrow filters enabled 2 × TC + 120 — 140 — 140 ns • Wide filters enabled 2 × TC + 208 — 228 — 228 ns 187 Last SCL edge to HREQ output not TAS. DSP56364 Technical Data.RQO ns deasserted • Filters bypassed 2 × TC + 30 50 — 50 — ns • Narrow filters enabled 2 × TC + 80 100 — 100 — ns • Wide filters enabled 2 × TC + 135 155 — 155 — ns 188 HREQ in assertion to first SCL edge TAS. HDM[7:0] are the divider modulus select bits.1 Freescale Semiconductor 3-45 . The expression for T I CCP is 2 T 2 = [ T C × 2 × ( HDM [ 7 :0 ] + 1 ) × ( 7 × ( 1 – HRS ) + 1 ) ] I CCP where HRS is the prescaler rate select bit. the fixed divide-by-eight prescaler is operational. is specified by the value of the HDM[5:0] and HRS bits of the 2 HCKR (SHI clock control register). the prescaler is bypassed.5 k¾ 3.21 • Filters bypassed 4327 — 927 — ns • Narrow filters enabled 4282 — 882 — ns • Wide filters enabled 4238 — 838 — ns 1 RP (min) = 1. Serial Host Interface (SHI) I2C Protocol Timing Table 3-18 SHI I2C Protocol Timing (continued) Standard I2C1 Standard-Mode Fast-Mode Unit Symbol/ No. Characteristics Expression Min Max Min Max 186 First SCL sampling edge to HREQ output TNG.1 Programming the Serial Clock The programmed serial clock cycle. When HRS is set. Rev. 4.

TR = 1000ns). SCL rise time (TR). 4. and the filters selected should be chosen 2 in order to achieve the desired SCL frequency. the user may select a value for the programmed serial clock cycle from 6 × T C ( if HDMS [ 5 :0 ] = $02 and HRS = 1 ) to 4096 × T C ( if HDMS [ 7 :0 ] = $FF and HRS = 0 ) The programmed serial clock cycle (TI CCP ). as shown in Table 3-19. TC = 10ns).5 × TC + 45ns + TR Narrow filters enabled TI2CCP + 2.Serial Host Interface (SHI) I2C Protocol Timing In I2C mode. TSCL = 10μs).5 × TC + 135ns + TR Wide filters enabled TI2CCP + 2. Rev.8 Thus the HDM[7:0] value should be programmed to $38 (=56). operating in a standard-mode I2C environment (FSCL = 100 KHz (i.e. 171 173 176 175 SCL 177 178 180 172 179 SDA Stop Start MSB LSB ACK Stop 174 186 182 183 189 184 188 187 HREQ AA0275 Figure 3-22 I2C Timing DSP56364 Technical Data.1 3-46 Freescale Semiconductor .5 × TC + 223ns + TR EXAMPLE: For DSP clock frequency of 100 MHz (i. Table 3-19 SCL Serial Clock Cycle Generated as Master Filters bypassed TI2CCP + 2.5 × 10ns – 45ns – 1000ns = 893ns I CCP Choosing HRS = 0 gives HDM [ 7 :0 ] = ( 8930ns ) ⁄ ( 2 × 10ns × 8 ) – 1 = 55.e. with filters bypassed T 2 = 10μs – 2.

2.5 × TC 15.0 10.0 — x ck ns synchronous mode) falling edge 19.0 x ck ns — 24.0 — • For external clock 1.0 i ck a 437 RXC rising edge to FSR out (wl) high — — — 36.0 i ck a 434 RXC rising edge to FSR out (bl) low — — — 37.0 — x ck ns 23.0 x ck ns — 24.0 i ck a 438 RXC rising edge to FSR out (wl) low — — — 37.0 — i ck 440 Data in hold time after RXC falling edge — — 5.0 — • For external clock 1.0 10.0 x ck ns — 21.1 Freescale Semiconductor 3-47 .0 — x ck ns edge6 1. Rev.0 — x ck TXC:max[3*tc.0 — 433 RXC rising edge to FSR out (bl) high — — — 37.13 Enhanced Serial Audio Interface Timing Table 3-20 Enhanced Serial Audio Interface Timing No.0 i ck a 436 RXC rising edge to FSR out (wr) low6 — — — 39.0 — i ck ns 3 × TC 30.0 — i ck 441 FSR input (bl.5 × TC 15.0 i ck a 439 Data in setup time before RXC (SCK in — — 0. Characteristics1. 4.0 x ck ns — 22.0 — i ck a DSP56364 Technical Data. 3 Symbol Expression Min Max Condition4 Unit 430 Clock cycle5 tSSICC 4 × TC 40.0 x ck ns — 22.0 — x ck 431 Clock high period ns • For internal clock — 2 × TC − 10.0 — x ck ns 3. Enhanced Serial Audio Interface Timing 3.0 — i ck a 442 FSR input (wl) high before RXC falling edge — — 1.0 x ck ns — 22.0 — 432 Clock low period ns • For internal clock — 2 × TC − 10. wr) high before RXC falling — — 23. t454] 40.0 i ck a 435 RXC rising edge to FSR out (wr) high6 — — — 39.

Rev.Enhanced Serial Audio Interface Timing Table 3-20 Enhanced Serial Audio Interface Timing (continued) No.0 x ck ns assertion — 20.0 x ck ns 21.0 — i ck s 445 Flags input hold time after RXC falling edge — — 6.0 i ck 448 TXC rising edge to FST out (wr) high6 — — — 31.0 — x ck ns 19.0 x ck ns — 19.0 x ck ns impedance — 17.0 — i ck a 444 Flags input setup before RXC falling edge — — 0.0 x ck ns — 15.0 x ck ns — 16.0 — x ck ns 0.0 — x ck ns 0.5 × TC — 28.0 i ck 447 TXC rising edge to FST out (bl) low — — — 31.0 — i ck 458 FST input (wl) to data out enable from high — — — 27.1 3-48 Freescale Semiconductor .0 i ck 452 TXC rising edge to data out enable from high — — — 31. 2.0 i ck 456 TXC rising edge to transmitter #0 drive enable — — — 34. 3 Symbol Expression Min Max Condition4 Unit 443 FSR input hold time after RXC falling edge — — 3.0 i ck 455 TXC rising edge to data out high impedance7 — — — 31.0 i ck 453 TXC rising edge to transmitter #0 drive enable — — — 34.0 i ck 449 TXC rising edge to FST out (wr) low6 — — — 33.0 — 21. wr) setup time before TXC — — 2.0 x ck ns — 17.0 x ck ns — 16.0 i ck 451 TXC rising edge to FST out (wl) low — — — 31.0 i ck 457 FST input (bl. Characteristics1.0 i ck 454 TXC rising edge to data out valid — 23 + 0.0 — i ck s 446 TXC rising edge to FST out (bl) high — — — 29. 4.0 x ck ns deassertion7 — 20.0 — x ck ns falling edge6 21.0 i ck 450 TXC rising edge to FST out (wl) high — — — 30.0 x ck ns — 17.0 — ns impedance DSP56364 Technical Data.0 x ck ns — 17.

6 The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform. asynchronous mode (asynchronous implies that TXC and RXC are two different clocks) i ck s = internal clock.0 x ck ns — 18.1 Freescale Semiconductor 3-49 . 4.0 i ck 463 HCKR/HCKT clock cycle — — 40. Characteristics1.0 — i ck 462 Flag output valid after TXC rising edge — — — 32.16 V ± 0.0 — ns 464 HCKT input rising edge to TXC output — — — 27. TJ = 0°C to +105°C.5 ns 465 HCKR input rising edge to RXC output — — — 27. 7 Periodically sampled and not 100% tested DSP56364 Technical Data. but spreads from one serial clock before first bit clock (same as bit length frame sync signal).16 V.0 — i ck 461 FST input hold time after TXC falling edge — — 4. Enhanced Serial Audio Interface Timing Table 3-20 Enhanced Serial Audio Interface Timing (continued) No.0 — x ck ns edge 21. 3 Symbol Expression Min Max Condition4 Unit 459 FST input (wl) to transmitter #0 drive enable — — — 31.0 — x ck ns 0.0 — ns assertion 460 FST input (wl) setup time before TXC falling — — 2. 2. synchronous mode (synchronous implies that TXC and RXC are the same clock) 3 bl = bit length wl = word length wr = word length relative 4 TXC (SCKT pin) = transmit clock RXC (SCKR pin) = receive clock FST (FST pin) = transmit frame sync FSR (FSR pin) = receive frame sync HCKT (HCKT pin) = transmit high speed clock HCKR (HCKR pin) = receive high speed clock 5 For the internal clock.5 ns 1 VCC = 3. until the one before last bit clock of the first word in frame. 2 i ck = internal clock x ck = external clock i ck a = internal clock. the external clock cycle is defined by Icyc and the ESAI control register. Rev. CL = 50 pF.

Enhanced Serial Audio Interface Timing 430 431 432 TXC (Input/Output) 446 447 FST (Bit) Out 450 451 FST (Word) Out 454 454 452 455 Data Out First Bit Last Bit Transmitter 459 #0 Drive Enable 457 453 456 FST (Bit) In 461 458 460 461 FST (Word) In 462 See Note Flags Out Note: In network mode. 4. In normal mode. AA0490 Figure 3-23 ESAI Transmitter Timing DSP56364 Technical Data. Rev. output flag transitions can occur at the start of each time slot within the frame.1 3-50 Freescale Semiconductor . the output flag state is asserted for the entire frame period.

1 Freescale Semiconductor 3-51 . Rev. Enhanced Serial Audio Interface Timing 430 431 RXC 432 (Input/Output) 433 434 FSR (Bit) Out 437 438 FSR (Word) Out 440 439 Data In First Bit Last Bit 441 443 FSR (Bit) In 442 443 FSR (Word) In 444 445 Flags In AA0491 Figure 3-24 ESAI Receiver Timing HCKT 463 SCKT (output) 464 Figure 3-25 ESAI HCKT Timing DSP56364 Technical Data. 4.

2 — ns 493 EXTAL edge to GPIO in not valid (GPIO in hold time) 1. CL = 50 pF 2 Valid only when PLL enabled with multiplication factor equal to one.GPIO Timing HCKR 463 SCKR (output) 465 Figure 3-26 ESAI HCKR Timing 3. 4.7 — ns 495 GPIO out rise time — — 13 ns 496 GPIO out fall time — — 13 ns 1 VCC = 3.16 V.8 ns 491 EXTAL edge to GPIO out not valid (GPIO out hold time) 4.1 3-52 Freescale Semiconductor . Rev. TJ = 0°C to +105°C.14 GPIO Timing Table 3-21 GPIO Timing No.8 — ns 492 GPIO In valid to EXTAL edge (GPIO in set-up time) 10.3 V ± 0.8 65. DSP56364 Technical Data.75 × TC-1.8 — ns 4942 Fetch to EXTAL edge before GPIO change 6. Characteristics1 Expression Min Max Unit 4902 EXTAL edge to GPIO out valid (GPIO out delay time) — 32.

0 ns 508 TMS.0 — ns DSP56364 Technical Data. Rev.0 MHz 501 TCK cycle time in Crystal mode 45.X:(R0).0 — ns 506 TCK low to output data valid 0.0 40. maximum 22 MHz) 0.0 40.0 ns 507 TCK low to output high impedance 0. GPIO (Output) 495 496 Figure 3-27 GPIO Timing 3.0 — ns 505 Boundary scan input data hold time 24. 4. JTAG Timing EXTAL (Input) 490 491 GPIO (Output) 492 493 GPIO Valid (Input) A0–A17 494 Fetch the instruction MOVE X0.0 22.0 — ns 503 TCK rise and fall times 0.1 Freescale Semiconductor 3-53 .0 — ns 502 TCK clock pulse width measured at 1. Characteristics Unit Min Max 500 TCK frequency of operation (1/(TC × 3). X0 contains the new value of GPIO and R0 contains the address of GPIO data register. TDI data setup time 5.15 JTAG Timing Table 3-22 JTAG Timing1.0 ns 504 Boundary scan input data setup time 5.0 3. 2 All Frequencies No.5 V 20.

2 (continued) All Frequencies No.0 — ns 510 TCK low to TDO data valid 0. 501 502 502 VIH VM VM TCK (Input) VIL 503 503 AA0496 Figure 3-28 Test Clock Input Timing Diagram TCK VIH (Input) VIL 504 505 Data Inputs Input Data Valid 506 Data Output Data Valid Outputs 507 Data Outputs 506 Data Outputs Output Data Valid AA0497 Figure 3-29 Boundary Scan (JTAG) Timing Diagram DSP56364 Technical Data.3 V ± 0. Rev. TDI data hold time 25. TJ = 0°C to +105°C.1 3-54 Freescale Semiconductor .0 44. CL = 50 pF 2 All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.JTAG Timing Table 3-22 JTAG Timing1. Characteristics Unit Min Max 509 TMS.0 44. 4.0 ns 511 TCK low to TDO high impedance 0.0 ns 1 VCC = 3.16 V.

Rev. JTAG Timing TCK VIH (Input) VIL 508 509 TDI TMS Input Data Valid (Input) 510 TDO (Output) Output Data Valid 511 TDO (Output) 510 TDO Output Data Valid (Output) AA0498 Figure 3-30 Test Access Port Timing Diagram DSP56364 Technical Data.1 Freescale Semiconductor 3-55 . 4.

Rev.1 3-56 Freescale Semiconductor .JTAG Timing NOTES DSP56364 Technical Data. 4.

4 Packaging 4. 4. DSP56364 Technical Data.1 TQFP Package Description Top view of the 100-pin TQFP package is shown in Figure 4-1 with its pin-outs.1 Freescale Semiconductor 4-1 .1. The 100-pin TQFP package mechanical drawing is shown in Figure 4-2. Rev. including diagrams of the package pinouts and tables describing how the signals described in Section 2. 4. Table 4-1 and Table 4-2show the pin/name assignments for the packages. The DSP56364 is available in a 100-pin TQFP package.1 Pin-Out and Package Information This section provides information about the available package for this product. "Signal/Connection Descriptions" are allocated for the package.

Rev. 4.Pin-Out and Package Information TDI GPIO3 GPIO2 GPIO1 GPIO0 NC NC NC D7 D6 D5 D4 GNDD VCCD D3 D2 D1 TMS TCK TDO GNDS VCCS VCCHQ GNDQ VCCLQ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 MODD 1 75 D0 MODB 2 74 A17 MODA 3 73 A16 FST 4 72 GNDA FSR 5 71 VCCA SCKT 6 70 A15 SCKR 7 69 A14 VCCS 8 68 A13 GNDS 9 67 A12 HCKT 10 66 VCCLQ VCCLQ 11 65 GNDQ GNDQ 12 DSP56364 64 GNDA HCKR 13 100-Pin TQPF 63 VCCA SDO0 14 62 A11 VCCHQ 15 61 VCCHQ SDO1 16 60 A10 SDO2/SDI3 17 59 A9 SDO3/SDI2 18 58 A8 SDO4/SDI1 19 57 A7 SDO5/SDI0 20 56 GNDA VCCS 21 55 VCCA GNDS 22 54 A6 SS/HA2 23 53 A5 MOSI/HA0 24 52 A4 MISO/SDA 25 51 A3 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RESET SCK/SCL PINIT/NMI NC EXTAL WR RD VCCC GNDC AA1 AA0 A0 A1 A2 HREQ VCCP PCAP GNDP TA CAS VCCA VCCHQ GNDA GNDQ VCCLQ Figure 4-1 DSP56364 100-Pin Thin Quad Flat Pack (TQFP). Top View DSP56364 Technical Data.1 4-2 Freescale Semiconductor .

4. Most pins supply a single signal.1 Freescale Semiconductor 4-3 . such as the MODx/IRQx pins that select an operating mode after RESET is deasserted. Pin-Out and Package Information Table 4-1 DSP56364 100-Pin TQFP Signal Identification by Pin Number Pin Pin Pin Pin Signal Name Signal Name Signal Name Signal Name No. but act as interrupt lines during operation. 1 MODD/IRQD 26 SCK/SCL 51 A3 76 D1 2 MODB/IRQB 27 HREQ 52 A4 77 D2 3 MODA/IRQA 28 PINIT/NMI 53 A5 78 D3 4 FST 29 RESET 54 A6 79 VCCD 5 FSR 30 No Connect 55 VCCA 80 GNDD 6 SCKT 31 VCCP 56 GNDA 81 D4 7 SCKR 32 PCAP 57 A7 82 D5 8 VCCS 33 GNDP 58 A8 83 D6 9 GNDS 34 EXTAL 59 A9 84 D7 10 HCKT 35 VCCHQ 60 A10 85 No Connect 11 VCCLQ 36 GNDQ 61 VCCHQ 86 No Connect 12 GNDQ 37 VCCLQ 62 A11 87 VCCLQ 13 HCKR 38 TA 63 VCCA 88 GNDQ 14 SDO0 39 CAS 64 GNDA 89 VCCHQ 15 VCCHQ 40 WR 65 GNDQ 90 No Connect 16 SDO1 41 RD 66 VCCLQ 91 GPIO0 17 SDO2/SDI3 42 VCCC 67 A12 92 VCCS 18 SDO3/SDI2 43 GNDC 68 A13 93 GNDS 19 SDO4/SDI1 44 AA1/RAS1 69 A14 94 GPIO1 20 SDO5/SDI0 45 AA0/RAS0 70 A15 95 GPIO2 21 VCCS 46 A0 71 VCCA 96 GPIO3 22 GNDS 47 A1 72 GNDA 97 TDO 23 SS/HA2 48 VCCA 73 A16 98 TDI 24 MOSI/HA0 49 GNDA 74 A17 99 TCK 25 MISO/SDA 50 A2 75 D0 100 TMS Note: Signal names are based on configured functionality. DSP56364 Technical Data. Rev. No. Some pins provide a signal with dual functionality. No. No.

1 4-4 Freescale Semiconductor . No. 4.Pin-Out and Package Information Table 4-2 DSP56364 100-Pin TQFP Signal Identification by Name Pin Pin Pin Pin Signal Name Signal Name Signal Name Signal Name No. No. Rev. No. A0 46 D4 81 HCKR 13 SDO4/SDI1 19 A1 47 D5 82 HCKT 10 TA 38 A10 60 D6 83 HREQ 27 TCK 99 A11 62 D7 84 MISO/SDA 25 TDI 98 A12 67 EXTAL 34 MODA/IRQA 3 TD0 97 A13 68 FSR 5 MODB/IRQB 2 TMS 100 A14 69 FST 4 MODD/IRQD 1 VCCA 48 A15 70 GNDA 49 MOSI/HA0 24 VCCA 55 A16 73 GNDA 56 No Connect 30 VCCA 63 A17 74 GNDA 64 No Connect 85 VCCA 71 A2 50 GNDA 72 No Connect 86 VCCC 42 A3 51 GNDC 43 No Connect 90 VCCD 79 A4 52 GNDD 80 PCAP 32 VCCHQ 15 A5 53 GNDP 33 PINIT/NMI 28 VCCHQ 35 A6 54 GNDQ 12 RD 41 VCCHQ 61 A7 57 GNDQ 36 RESET 29 VCCHQ 89 A8 58 GNDQ 65 SCK/SCL 26 VCCLQ 11 A9 59 GNDQ 88 SCKR 7 VCCLQ 37 AA0 45 GNDS 9 SCKT 6 VCCLQ 66 AA1 44 GNDS 22 SDO0 14 VCCLQ 87 CAS 39 GNDS 93 SDO1 16 VCCP 31 D0 75 GPIO0 91 SDO5/SDI0 20 VCCS 8 D1 76 GPIO1 94 SS/HA2 23 VCCS 21 D2 77 GPIO2 95 SDO2/SDI3 17 VCCS 92 D3 78 GPIO3 96 SDO3/SDI2 18 WR 40 DSP56364 Technical Data.

1.2 TQFP Package Mechanical Drawing Figure 4-2 DSP56364 100-pin TQFP Package DSP56364 Technical Data. Rev.1 Freescale Semiconductor 4-5 . 4. Pin-Out and Package Information 4.

1 4-6 Freescale Semiconductor . Rev. 4.Pin-Out and Package Information DSP56364 Technical Data.

For example. or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. TJ. add a heat sink. The user controls the thermal environment to change the case-to-ambient thermal resistance. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. For ceramic packages. analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. in °C can be obtained from the following equation: T J = T A + ( P D × R θJA ) Where: TA = ambient temperature °C RqJA = package junction-to-ambient thermal resistance °C/W PD = power dissipation in package W Historically. • To minimize temperature variation across the surface. Again. 4. Rev. if the estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate. thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance.1 Thermal Design Considerations An estimation of the chip junction temperature. R θJA = R θJC + R θCA Where: RθJA = package junction-to-ambient thermal resistance °C/W RθJC = package junction-to-case thermal resistance °C/W RθCA = package case-to-ambient thermal resistance °C/W RθJC is device-related and cannot be influenced by the user.5 Design Considerations 5. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages. This model is most useful for ceramic packages with heat sinks. change the mounting arrangement on the printed circuit board (PCB). the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. the user can change the air flow around the device. DSP56364 Technical Data.1 Freescale Semiconductor 5-1 . in situations where the heat flow is split between a path to the case and an alternate path through the PCB. RθCA. some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. a system level model may be appropriate.

Rev. the new thermal metric. • If the temperature of the package case (TT) is determined by a thermocouple. • Use at least six 0.1 μF bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. • Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 1.01–0.2 cm (0. has been defined to be (TJ – TT)/PD. • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. and TA pins. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. normal precautions should be taken to avoid exceeding maximum voltage ratings. From a practical standpoint. DSP56364 Technical Data. • Use at least a four-layer PCB with two inner layers for VCC and GND. the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. However. • Because the DSP output signals have fast rise and fall times.5 inch) per capacitor lead. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. IRQB. In natural convection. using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature.1 5-2 Freescale Semiconductor .. 5. the thermal resistance is measured from the junction to where the leads are attached to the case. PCB trace lengths should be minimal. IRQD. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. Maximum PCB trace lengths on the order of 15 cm (6 inches) are recommended. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor.g. Use the following list of recommendations to assure correct DSP operation: • Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. Hence. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e. The suggested value for a pull-up or pull-down resistor is 10 k ohm.Electrical Design Considerations • To define a value approximately equal to a junction-to-board thermal resistance. the thermal resistance is computed using the value obtained by the equation: ( TJ – TT ) ⁄ PD As noted above. 4. either GND or VCC).2 Electrical Design Considerations CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. thermal characterization parameter or ΨJT. that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. This recommendation particularly applies to the address and data buses as well as the IRQA.

The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. Current consumption is described by the following formula: I = C×V×f where C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle Example 1. • Connect the unused inputs to pull-up or pull-down resistors. to compensate for measured board current not caused by the DSP). which is charging and discharging the capacitances of the pins and internal nodes. • RESET must be asserted when the chip is powered up. One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i. Current Consumption For a Port A address pin loaded with 50 pF capacitance. • Disable unused peripherals. • At power-up. • Minimize external memory accesses and use internal memory accesses.95 V. toggling at its maximum possible rate (50 MHz). A stable EXTAL signal must be supplied before deassertion of RESET.1 Freescale Semiconductor 5-3 .3 Power Consumption Considerations Power dissipation is a key issue in portable DSP applications. • Minimize the number of pins that are switching. • Minimize the capacitive load on the pins.. operating at 3. 5. 4.3 V. do the following: • Set the EBD bit when not accessing external memory. Rev. Power Consumption Considerations • All inputs must be terminated (i. not allowed to float) using CMOS levels. and with a 100 MHz clock. except for the three pins with internal pull-up resistors (TMS.3 × 50 × 10 = 8. which is not necessarily a real application case. Some of the factors which affect current consumption are described in this section. TCK).e. check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. Most of the current consumed by CMOS devices is alternating current (ac).e. ensure that the voltage difference between the 5 V tolerant pins and the chip VCC never exceeds 3.. • If multiple DSP56364 devices are on the same board. the current consumption is – 12 6 I = 50 × 10 × 3. TDI.25mA The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions. • Take special care to minimize noise levels on the VCCP and GNDP pins. For applications that require very low current consumption. DSP56364 Technical Data.

F2 could be 66 MHz and F1 could be 33 MHz.PLL Performance Issues A benchmark power consumption test algorithm is listed in Appendix A.e. 5. it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e. and the following equation to derive the current per MIPS value. The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. 5. There is no testing that verifies these exact numbers.4.. For example. If the rate of change of the frequency of EXTAL is slow (i.. 4. specific test current measurements.5%.1 5-4 Freescale Semiconductor .1 Input (EXTAL) Jitter Requirements The allowed jitter on the frequency of EXTAL is 0. Use the test algorithm. Rev. These observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges.4 PLL Performance Issues The following explanations should be considered as general observations on expected PLL behavior. "IBIS Model". The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application. DSP56364 Technical Data. I ⁄ MIPS = I ⁄ MHz = ( I typF2 – I typF1 ) ⁄ ( F2 – F1 ) where: ItypF2 = current at F2 ItypF1 = current at F1 F2 = high frequency (any specified operating frequency) F1 = low frequency (any specified operating frequency lower than F2) NOTE F1 should be significantly less than F2. then the allowed jitter can be 2%. it does not stay at an extreme value for a long time).

6 Ordering Information Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and to place an order. DSP56364 Technical Data. DTS.3 V Thin quad flat pack (TQFP) 100 100 XCB56364FU100 Quad flat pack (QFP) 112 100 XCB56364PV100 1 The DSP56364 can include factory-programmed ROM.1 Freescale Semiconductor 6-1 .freescale. Variations will be supported for Dolby digital (AC-3). or to request customer-specific ROM-based support. Table 6-1 Ordering Information1. Rev. call your local Freescale Semiconductor sales office or authorized distributor. 2 Supply Pin Frequency Part Package Type Order Number Voltage Count (MHz) DSP56364 3.com/dsp for current availability. Please consult the web site at www. For additional information on future part development. These products are only available to authorized licensees of those technologies. and other features. 2 Future products in the DSP56364 family may include other ROM-based options. 4. MPEG2. The listed ‘B’ ROM code is a generic unused ROM available to any customer.

NOTES DSP56364 Technical Data. 4.1 6-2 Freescale Semiconductor . Rev.

2pF 1. 2002 [Component] 56364 [Manufacturer] Freescale SEMI CONDUCTOR Ltd.1nH 4.ibs [File Rev] e [Date] Feb 13.3pF 1.4pF [Pin] signal_name model_name R_pin L_pin C_pin 1 irqd_ ipad5v_io 2 irqb_ ipad5v_io 3 irqa_ ipad5v_io 4 fst ipad5v_io 5 fsr ipad5v_io 6 sckt ipad5v_io 7 sckr ipad5v_io 8 vccs power 9 gnds gnd 10 hckt ipad5v_io 11 vcclq power 12 gndq gnd 13 hckr ipad5v_io 14 sdo0 ipad5v_io 15 vcchq power 16 sdo1 ipad5v_io 17 sdo2/sdi3 ipad5v_io 18 sdo3/sdi2 ipad5v_io 19 sdo4/sdi1 ipad5v_io 20 sdo5/sdi0 ipad5v_io 21 vccs power 22 gnds gnd 23 ss_/ha2 ipad5v_io 24 mosi/ha0 ipad5v_io 25 miso/sda ipad5i_io 26 sck/scl ipad5i_io 27 hreq_ ipad5i_io 28 pinit/nmi_ ipad5v_io 29 reset_ ipad5v_io 31 vccp power 32 pcap power 33 gndp gnd 34 extal ipadex_i 35 vcchq power DSP56364 Technical Data.Appendix A IBIS Model IBIS Model [IBIS Ver] 3.1 Freescale Semiconductor A-1 .3nH C_pkg 1.0m L_pkg 2. Rev. [Package] | variable typ min max R_pkg 45.5nH 1.0m 75.0m 22. 4.2 [File name] 56364_e.

1 A-2 Freescale Semiconductor . Rev. 4. 36 gndq gnd 37 vcclq power 38 ta_ ipadn_io 39 cas_ ipadm_3st 40 wr_ ipadn_io 41 rd_ ipadn_io 42 vccc power 43 gndc gnd 44 aa1/ras1_ ipado_3st 45 aa0/ras0_ ipado_3st 46 a0 ipada_3st 47 a1 ipada_3st 48 vcca power 49 gnda gnd 50 a2 ipada_3st 51 a3 ipada_3st 52 a4 ipada_3st 53 a5 ipada_3st 54 a6 ipada_3st 55 vcca power 56 gnda gnd 57 a7 ipada_3st 58 a8 ipada_3st 59 a9 ipada_3st 60 a10 ipada_3st 61 vcchq power 62 a11 ipada_3st 63 vcca power 64 gnda gnd 65 gndq gnd 66 vcclq power 67 a12 power 68 a13 ipada_3st 69 a14 ipada_3st 70 a15 ipada_3st 71 vcca power 72 gnda gnd 73 a16 ipada_3st 74 a17 ipada_3st 75 d0 ipadd_io 76 d1 ipadd_io 77 d2 ipadd_io 78 d3 ipadd_io 79 vccd power 80 gndd gnd 81 d4 ipadd_io 82 d5 ipadd_io 83 d6 ipadd_io 84 d7 ipadd_io 87 vcclq power 88 gndq gnd 89 vcchq power 91 gpio0 ipad5v_io 92 vccs power 93 gnds gnd DSP56364 Technical Data.

94 gpio1 ipad5v_io
95 gpio2 ipad5v_io
96 gpio3 ipad5v_io
97 tdo ipad5f_io
98 tdi ipad5f_io
99 tck ipad5f_io
100 tms ipad5f_io

[Model] ipad5f_io | ""
Model_type I/O
Vinl = 0.8
Vinh = 2
| variable typ min max
C_comp 1.96p 1.87p 2.06p
| variable typ min max
[Temperature Range] 40.0 0.0 120.0
| variable typ min max
[Voltage Range] 3.30V 3.00V 3.60V
|
[Pulldown]
| pulldown in the table = pulldown subtract gnd_clamp
|Voltage I(typ) I(min) I(max)
|
-3.30V -142.303u -76.239u -215.182u
-3.20V -149.700u -80.226u -226.432u
-3.10V -157.861u -84.616u -238.866u
-3.00V -166.908u -89.472u -252.678u
-2.90V -176.992u -94.869u -268.107u
-2.80V -188.295u -100.900u -285.446u
-2.70V -201.049u -107.679u -305.068u
-2.60V -215.545u -115.349u -327.446u
-2.50V -232.155u -124.094u -353.191u
-2.40V -251.367u -134.145u -383.107u
-2.30V -273.825u -145.808u -418.273u
-2.20V -300.403u -159.488u -460.167u
-2.10V -332.314u -175.737u -510.874u
-2.00V -371.286u -195.318u -573.418u
-1.90V -419.868u -219.325u -652.360u
-1.80V -481.968u -249.369u -754.892u
-1.70V -563.882u -287.925u -893.013u
-1.60V -676.382u -338.973u -1.088m
-1.50V -839.410u -409.300u -1.383m
-1.40V -1.094m -511.367u -1.873m
-1.30V -1.537m -670.350u -2.819m
-1.20V -2.451m -943.845u -5.162m
-1.10V -4.857m -1.486m -12.214m
-1.00V -10.606m -2.746m -20.764m
-0.90V -14.267m -5.259m -21.749m
-0.80V -13.851m -7.108m -20.142m
-0.70V -12.481m -7.168m -18.211m
-0.60V -10.883m -6.348m -15.981m
-0.50V -9.156m -5.339m -13.503m
-0.40V -7.378m -4.288m -10.922m
-0.30V -5.572m -3.224m -8.282m
-0.20V -3.741m -2.154m -5.584m

DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor A-3

-0.10V -1.885m -1.080m -2.825m
0.00V 1.898p 1.419p 1.871p
0.10V 1.857m 1.057m 2.800m
0.20V 3.630m 2.064m 5.482m
0.30V 5.323m 3.023m 8.052m
0.40V 6.936m 3.935m 10.508m
0.50V 8.467m 4.798m 12.849m
0.60V 9.915m 5.611m 15.073m
0.70V 11.275m 6.371m 17.176m
0.80V 12.546m 7.078m 19.155m
0.90V 13.723m 7.726m 21.011m
1.00V 36.925m 20.745m 56.704m
1.10V 39.391m 22.074m 60.708m
1.20V 41.612m 23.244m 64.383m
1.30V 43.585m 24.247m 67.726m
1.40V 45.305m 25.079m 70.735m
1.50V 46.773m 25.741m 73.414m
1.60V 47.997m 26.251m 75.766m
1.70V 48.985m 26.633m 77.783m
1.80V 49.733m 26.905m 79.441m
1.90V 50.257m 27.092m 80.724m
2.00V 50.612m 27.223m 81.651m
2.10V 50.858m 27.321m 82.294m
2.20V 51.040m 27.399m 82.744m
2.30V 51.182m 27.465m 83.074m
2.40V 51.302m 27.522m 83.332m
2.50V 51.405m 27.572m 83.543m
2.60V 51.497m 27.618m 83.724m
2.70V 51.581m 27.657m 83.884m
2.80V 51.658m 27.674m 84.030m
2.90V 51.727m 27.587m 84.165m
3.00V 51.757m 27.577m 84.290m
3.10V 51.229m 28.700m 84.409m
3.20V 49.190m 30.042m 84.515m
3.30V 49.441m 31.171m 84.491m
3.40V 51.034m 32.199m 81.077m
3.50V 54.363m 33.153m 79.736m
3.60V 57.165m 34.039m 80.276m
3.70V 58.834m 34.872m 82.430m
3.80V 60.328m 35.686m 85.482m
3.90V 61.725m 36.495m 91.743m
4.00V 63.035m 37.291m 94.219m
4.10V 64.319m 38.051m 96.276m
4.20V 65.598m 38.755m 98.249m
4.30V 66.836m 39.394m 100.059m
4.40V 67.999m 39.962m 101.849m
4.50V 69.069m 40.453m 103.628m
4.60V 70.046m 40.840m 105.345m
4.70V 70.938m 41.065m 106.956m
4.80V 71.751m 40.952m 108.448m
4.90V 72.476m 40.067m 109.826m
5.00V 73.089m 39.395m 111.106m
5.10V 73.531m 39.313m 112.297m
5.20V 73.651m 39.358m 113.400m
5.30V 72.901m 39.410m 114.401m

DSP56364 Technical Data, Rev. 4.1
A-4 Freescale Semiconductor

5.40V 71.005m 39.460m 115.267m
5.50V 70.389m 39.508m 115.917m
5.60V 70.321m 39.552m 116.139m
5.70V 70.361m 39.595m 114.582m
5.80V 70.422m 39.634m 111.344m
5.90V 70.489m 39.672m 110.612m
6.00V 70.557m 39.708m 110.449m
6.10V 70.624m 39.743m 110.455m
6.20V 70.690m 39.777m 110.515m
6.30V 70.753m 39.812m 110.595m
6.40V 70.817m 39.848m 110.686m
6.50V 70.881m 39.886m 110.783m
6.60V 70.949m 39.929m 110.885m
|
[Pullup]
| pullup in the table = pullup subtract power_clamp
|Voltage I(typ) I(min) I(max)
|
-3.30V 75.797u 7.914u 161.477u
-3.20V 90.464u 17.699u 181.779u
-3.10V 105.160u 27.445u 202.314u
-3.00V 119.836u 37.119u 223.007u
-2.90V 134.451u 46.694u 243.785u
-2.80V 148.966u 56.144u 264.581u
-2.70V 163.342u 65.447u 285.332u
-2.60V 177.543u 74.582u 305.982u
-2.50V 191.536u 83.527u 326.474u
-2.40V 205.285u 92.262u 346.757u
-2.30V 218.754u 100.766u 366.776u
-2.20V 231.907u 109.016u 386.478u
-2.10V 244.706u 116.988u 405.807u
-2.00V 257.106u 124.659u 424.699u
-1.90V 269.061u 131.998u 443.089u
-1.80V 280.519u 138.978u 460.899u
-1.70V 291.423u 145.565u 478.046u
-1.60V 301.710u 151.723u 494.457u
-1.50V 311.348u 157.417u 521.406u
-1.40V 729.899u 162.626u 1.612m
-1.30V 10.510m 445.517u 14.832m
-1.20V 9.629m 6.444m 13.576m
-1.10V 8.670m 5.833m 12.231m
-1.00V 7.693m 5.190m 10.854m
-0.90V 6.732m 4.551m 9.483m
-0.80V 5.825m 3.942m 8.169m
-0.70V 5.004m 3.382m 6.971m
-0.60V 4.261m 2.869m 5.921m
-0.50V 3.549m 2.381m 4.953m
-0.40V 2.841m 1.902m 3.978m
-0.30V 2.135m 1.426m 2.987m
-0.20V 1.437m 951.489u 2.003m
-0.10V 722.340u 478.341u 1.005m
-0.00V 22.329p 3.311p 24.081p
0.10V -708.556u -465.927u -990.647u
0.20V -1.377m -903.637u -1.943m
0.30V -2.007m -1.319m -2.832m

DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor A-5

933m -22.70V -38.265m 1.131m -47.90V -5.614m -1.608m -20.50V -39.20V -37.188m -52.80V -4.917m 2.40V -37.392m 1.60V -39.322m 2.537m 0.444m -24.600m -3.50V -30.00V -39.683m 3.70V -4.762m -8.631m -17.736m -3.202m -22.737m 1.916m 3.50V -41.489m -21.949m -22.241m -56.10V -5.715m -54.791m -21.590m -22.305m -7.80V -33.067m -59.217m -66.055m -19.960m -20.632m -19.785m 5.571m 2.741m -58.714m -22.570m -65.948m -9.50V -37.135m -20.032m -64.253m -62.1 A-6 Freescale Semiconductor .556m -54.689m -23.997m -62.70V -39.302m -20.586m -21.738m -2.631m 3.157m -21.90V -33.742m -6.80V -39.352m -57.802m 1.336m 0.00V -38.693m -23.370m -24.730m -18.730m -50.90V -36.361m 4.334m 3.423m -5.60V -36.983m 1.10V -34.997m -56.798m -61.240m 2.50V -35.973m -51.623m 4.932m 2.505m 5.709m -9.892m -62.457m -57.40V -41.40V -2.861m -55.749m -18. Rev.595m -63.547m -8.884m -20.20V -34.780m 4.819m 4.00V -34.037m -6.142m 3.086m 1.980m -3.453m 5.978m -21.40V -29.702m 0.80V -36.024m 4.886m -24.561m -61.710m -3.490m -60.60V -31.630m -19. 0.211m -22.370m -21.330m 5.788m -21.384m -23.381m -53.70V -32.121m -23.828m -22.324m -3.411m -63. 4.505m 2.357m -22.279m -10.019m 3.123m -56.90V -39.463m 2.874m 5.643m -21.70V -36.253m -2.499m 1.893m -23.10V -37.30V -37.076m -22.30V -38.60V -3.043m -24.986m 4.393m -19.194m 4.983m DSP56364 Technical Data.60V -41.860m 5.510m 2.713m -61.551m 2.137m -21.80V -42.288m -64.327m -21.070m -22.420m -60.575m -20.40V -35.185m -3.20V -38.00V -5.880m -66.460m -22.801m -63.60V -37.284m -60.30V -6.20V -40.899m -25.650m -58.909m -59.216m -60.40V -38.70V -42.254m 4.620m 1.50V -3.143m -59.00V -36.30V -40.454m -49.079m -4.116m -62.292m 1.035m 2.332m -22.10V -40.556m -58.989m -59.096m 0.913m 3.214m 5.516m -22.681m 3.20V -6.10V -38.573m 4.90V -38.827m -58.30V -35.406m 4.747m -45.80V -38.139m 1.181m 3.192m -2.817m 0.436m 3.352m -60.506m 5.635m -61.098m 5.

80V -655.685p -210.839m -95.628p 1.164m -723.130p 0.127m -1. 5.327m -262.197 -2.059 -625.40V -432.721m 6.60V -5.342m -629.793 -1.971p 0.222m -1.80V -1.384p DSP56364 Technical Data.231m -0.385 -804.848m 6.735m -581.50V -8.074 -2.129p 81.637u -9.110p 0.618m -352.50V -1.30V -18.70V -476.675 -2.983m -68.335p 2.931m -1.319m -2.60V -85.210p 0.576u -310.00V -33.177m -817.634m -1.979p 114.564p -30.291p 0.773m -536.292 -2.815m 6.256m -1.071m -1.370m -0.849p -13.295m -1.095m -25.80V 2.533m -1.390m -71.30V -1.303 -759.90V -1.029 -2.30V -20.017p 340.059 -3.499p -9.30V -1.760m -316.10V -116.833p 147.771 -2.050p 0.30V -46.221 -714.374m 6.839m -230.50V -9.70V -1.304n -3.930u -0.466p 1.748m | [GND_clamp] | |Voltage I(typ) I(min) I(max) | -3.587m -1.883m -845.482m -443.610p 0.70V -1.877p 308.354u -147.649p -0.102 -2.593n -0. Rev.90V 6.999u -0.678m 6.612m -0.10V -44.929m -73.10V -27.007 -1.287m -27. 4.60V -495.874n -340.029m -6.356p -20.20V -187.878m -273.171m -404.466 -849.048m -1.446m -448.748p 0.875 -1.40V -338.579 -2.895n -258.10V -1.1 Freescale Semiconductor A-7 .20V -977.777m -1.30V -262.080m -75.585m -67.242m -360.548 -893.303p 48.50V -416.409m -1.665p -30.140m -27.596p 244.90V -43.944n -8.910p 0.415m -69.487m -74.065m 6.10V -896.924p -5.10V 14.454p 212.20V -964.20V 19.50V -48.754p 13.70V -575.10V -72.335p 14.140 -670.049m -28.473m -25.395m -146.20V -45.90V -735.00V -44.975n -0.188p -1.498m -26.015u -2.769m -26.884m -70.90V -16.20V -22.546p -25.689p 179.384m -1.388 -2.990m -29.40V -47.730m -1.60V -1.155 -3.711m 6.024m -37.642m -1.756m -106.20V -1.548m -1.583p -2.60V -48.877u -295.765m -1.067m -188.254m -14.963 -2.869p -16.483 -2.906p 0.80V -2.711 -983.489m -1.560n -43.388p 10.891m -175.40V -1.40V -14.508p -34.181u -0.033u -33.758m -536.628p -29.

370m 4.065p 2.883m -43.90V -1.102 5.265n 86.30V -1.910p 30.30V 23.221 -849.715p 499.197 6.760m -448.70V 80.400p 2.254m -106.108p 1.561p 692.706p 723.106p 57.773m -670.20V 60.839m -360.771 6.777m -817.70V -338.748p 3.875 -1.164m -175.794p 3.758m -33.610p 3.119 -1.395m -273.722p 37.40V -116.110p 3.70V -1.50V -964.869p 780.793 -1.174m 5.675p 41.10V -655.074p 808.533m 4.90V 47.930u 4.685p -340.157p 372.354u -34.891m -147.302p 1.327m -845.90V -495.297p 404.304n -2.60V 35.20V -16.264p 69.30V -55.391p 80.029 -1.156p 2.579 6.409m 5.40V -896.446m -581.164 -1.10V -1.761p 49.384m 5.418p 659.910p 3.50V -977.30V 103.70V 39.80V -8.10V 89.80V 43.80V -416.548 -1.906p 3.999u 4.637u -29.482p 2.029m -8.209 -1.874n -295.10V -2.436p 436.277p 627.250p 18.649p 3.583p -3.499p 835.20V 89.319p 2.295m 5.139p 1.143p 22.513p 77.40V 68.995p 563.303 -893.931m -1. Rev.973p 65.074 -1.735m -714.181u 4.593n 4.195p 3.319m -258.576p 467.048m -536.199m 4.810p 2.765m -1.573p 1.576u -25.60V -1.587m 5.933p 53.974p 1.711 -1.10V 56.50V 31.60V -1.171m -536.847p 751.612m 4.646p 2.805p 33.342m -95.1 A-8 Freescale Semiconductor .20V -1.30V -33.071m -1.878m -404.466 -983.007 5.482m -6.483 6.140 -804.478p | [POWER_clamp] | |Voltage I(typ) I(min) I(max) | 3.892p 1.442p 73. 1.20V -735.033u -14.50V -1.018p 1.944n -20.564p 2.057p 1.40V 27. 4.618m -2.564p -33.90V 84.636m -188.489m -912.127m -723.877u -37.059 -759.60V -20.837p 860.256m -1.675 6.90V -85.40V -72.221p 1.027p 26.231m 4.50V -187.630 -1.756m -230.593n 90.60V -262.305n 88.024m -146.855p 531.80V -1.30V -815.634m 5.80V 82.30V 64.730m 5.388 6.177m -262.839m -9.067m -316.867 DSP56364 Technical Data.60V 76.642m -443.237p 2.40V -1.344p 3.70V -432.548m -629.50V 72.997m -625.142p 61.

845u -5.23/85.004p 1.05/194.737u -510.882u -287.211m -0.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.350u -2.868u -219.369u -754.10V -157.068u -2.90V -419.00V -10.70V -12.606m -2.874u -2.300u -1.314u -175.107u -2.30V -273.873m -1.318u -573.908u -89.545u -115.486m -12.764m -0.825u -145.56p | variable typ min max [Temperature Range] 40.616u -238.869u -268.418u -1.155u -124.383m -1.892u -1.86/343.883m -6.472u -252.451m -943.339m -13.40V -1.60V -215.30V 3.861u -84.162m -1.367u -134.286u -195.00V -166.191u -2.226u -226. | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 2. Rev.819m -1.259m -21.808u -418.094u -353.537m -670.504p | dV/dt_r 2.145u -383.749m -0.700u -80.678u -2.013u -1.20V -300.805p 2.403u -159.80V -13.30V -1.04/136.10V -332.44p 3.503m DSP56364 Technical Data.239u -215.900u -285.107u -2.90V -176.0 | variable typ min max [Voltage Range] 3.23/118.094m -511.488u -460.80V -481.168m -18.349u -327.108m -20.303u -76.744p 1.382u -338.50V -232.30V -142.20V -2.142m -0.50V -839.088m -1.295u -100.410u -409.156m -5.542p 2.00V -371.481m -7.432u -3.925u -893.367u -1.0 0.60V -10.049u -107.80V -188.90V -14.866u -3.325u -652.0 120.851m -7.1 Freescale Semiconductor A-9 .20V -149.360u -1.857m -1.00V 3.40V -251.679u -305.8 Vinh = 2 | variable typ min max C_comp 4.167u -2.70V -563.89p 4.10V -4.86/237.60V -676.968u -249.214m -1.981m -0.70V -201.182u -3.267m -5.446u -2.446u -2.50V -9. 4.746m -20.850p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipad5i_io | "" Model_type I/O Vinl = 0.273u -2.992u -94.348m -15.973u -1.

60V 57.174m 84.30V 5.00V 1.30V 51.409m 100.618m 83.951m 4.228m 34.572m -3.884m 2.288m -10.687m 87.581m 27.155m 0.90V 50.424m 3.658m 27.857m 1.10V 1.30V 50.781m 27.683m 84.871p 0.290m 3.078m 19.825m 0.658m 83.985m 26. Rev.922m -0.224m -8.294m 2.574m 3.321m 38.60V 51.467m 4.074m 2.257m 27.399m 82.158m 3.90V 13.724m 2.602m 38.773m 25.50V 51.612m 27.522m 83.244m 64.059m 96.498m 91.633m 77.50V 8.853m 4.276m 4.640m 28.275m 6.996m 108.60V 9.936m 3.858m 27.321m 82.332m 2.296m 94.733m 26.414m 1.302m 27.10V 39.10V 64. -0.585m 24.724m 2.20V 3.20V -3.726m 21.383m 1.982m 101.30V 66.405m 27.365m 3.20V 65.508m 0.948m 3.20V 50.030m 2.735m 1.726m 1.478m 103.612m 23.282m 30.080m -2.441m 1.073m 0.228m 4.90V 72.088m 40.638m 4.168m DSP56364 Technical Data.741m 73.023m 8.630m 2.10V 50.064m 5.453m 111.20V 41.060m 4.729m 27.092m 80.783m 1.154m -5.072m 40.872m 83.40V 51.50V 69.1 A-10 Freescale Semiconductor .798m 12.361m 4.50V 46. 4.20V 51.725m 36.323m 3.70V 58.767m 98.90V 61.00V 63.423m 3.973m 41.766m 1.844m 39.905m 79.40V 68.118m 109.584m -0.152m 39.40V 6.251m 75.00V 51.074m 60.70V 11.744m 2.704m 84.176m 0.328m 35.10V -1.065m 84.482m 0.484m 4.519m 3.40V 51.915m 5.409m 3.273m 31.011m 1.10V 51.794m 40.223m 81.497m 27.153m 80.80V 49.165m 3.529m 40.885m -1.391m 22.80V 60.40V -7.378m -4.419p 1.80V 51.80V 71.875m 5.60V 70.935m 10.052m 0.00V 36.102m 106.00V 50.70V 70.200m 83.800m 0.249m 4.546m 7.039m 81.40V 45.035m 37.121m 33.30V 43.057m 2.282m -0.247m 67.70V 51.305m 25.00V 73.60V 47.371m 17.793m 84.838m 34.643m 84.079m 70.925m 20.70V 48.50V 55.90V 51.997m 26.741m -2.704m 1.543m 2.849m 0.611m 15.898p 1.871m 105.745m 56.465m 83.871m 32.572m 83.982m 4.040m 27.708m 1.651m 2.012m 39.182m 27.30V -5.80V 12.723m 7.

60V 355.605m 39. Rev.00V 7.648m 6.392m 5.595u 182.897m 6.381u -3.40V 355.383m 6.641u 183.762u -1.765u 588.920u 589.492m 5.964u -2.163u 183.382m 4.70V 70.902m 3.511m 39.457m 39.559u 182.20V 9.00V 23.829u -1.40V 71.617u -2.30V 355.944m 8.737m 39.667m 39.40V 764.934u -1.20V 73.127m 6.30V 2.831m 39.805p 24.692u -1.193u 183.551m 115.788u 586.30V 72.701m 5.20V 1.90V 355.896u -2.287u -3.242u 183.512m 39.118u -2.257m -1.880m -1.134m 1.188u -3.815u 14.230m 40.50V 3.002m -0.891p DSP56364 Technical Data.734u 182.405u 587.40V 71.749m 39.262m 2.061m 5.799u 182.841m 1.50V 70.622u 184.90V 6.944m 110.870m 5.661m 116.612m -1.173m -0.779u -2.645u 588.1 Freescale Semiconductor A-11 .70V 354.10V 73.004m 3.978u 183.621u -1.921m -0.432m 113.737m 4.492m 114.288u 587.860u 183.763m 5.90V 70.899m 110.00V 354.40V 2.827m 3.953m -0.60V 354.374m 5.70V 355.875u 183.536m 460.90V 354.972m -0.249u 2.946u 1.650u 1.121u 590.608m 116.870m -0.20V 356.349u -2.10V 354.472u 587.00V 70.796m 6.711u 597.10V 721.911m 39.554m 9.833m 6.809m 110.060u 586.10V 356.978m -0.426m 2.148m 40.083m 111.434m 951.855m 110.468u 183.195m 10.198u 182.528u -2.20V 354.301m 5. 5.50V 354.233u 587.862u 586.920u 183.034m 111. 4.009m 6.80V 354.545m 5.666u 182.190u 184.097u 183.716m 6.50V 355.989m 39.340u 183.30V 357.20V 70.10V 8.379m 112.036u 183.550u 587.381u 591.549m 2.510m 5.762m 111.492m -0.60V 70.30V 70.036u -2.119u 586.985m -0.882u 477.30V 10.999m 39.068m 40.50V 71.455m 13.10V 70.841m 12.80V 355.80V 5.574u -1.80V 70.988m 110.997u 586.931u 586.136m 111.218u -2.674m -1.005m -0.129u -2.60V 71.70V 5.177u 586.250m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.115m 39.683m 5.345u 587.586m 39.094p 36.713m 114.00V 355.689m 6.60V 4.

659u -990.608m -20.90V -38.40V -41.30V -37.143m -59.334m 3.454m -49.067m -59.10V -40.948m -9.192m -2.30V -40.10V -5.561m -61.60V -36.457m -57.420m -60.406m 4.253m -62.50V -3.802m 1.573m 4.327m -21.973m -51.893m -23.10V -38.079m -4.30V -38.460m -22.116m -62.253m -2.983m 1.040u -465.832m 0.240m 2.392m 1.90V -33.181m 3.096m 0.352m -57.510m 2.978m -21.241m -56.40V -35.1 A-12 Freescale Semiconductor .623m 4.715m -54.139m 1.60V -37.892m -62.713m -61.336m 0.505m 2.393m -19.123m -56.620m 1.037m -6.319m -2.738m -2.265m 1.188m -52.986m 4.40V -2.00V -39.40V -29.90V -36.90V -5.411m -63.70V -32.817m 0.330m 5.785m 5.142m 3.10V -34.884m -20.20V -37.40V -37.60V -3.571m 2.590m -22.702m 0.932m 2.595m -63.60V -31.516m -22.284m -60.292m 1.423m -5.50V -41.960m -20.547m -8.086m 1.575m -20.035m 2.941m 0.20V -1. Rev.730m -50.997m -62.279m -10.490m -60.80V -39.737m 1.683m 3.819m 4.055m -19.131m -47.549u -1.861m -55.357m -22.90V -39.076m -22.10V -708.693m -23.980m -3.070m -22.537m 0.933m -22.50V -35.860m 5.374m -903.631m -17.917m 2.384m -23.989m -59.556m -54.370m -21.791m -21.614m -1.305m -7.007m -1.463m 2. 0.747m -45.736m -3.798m -61.710m -3.098m 5.949m -22.40V -38.444m -24.322m 2.551m 2. 4.202m -22.302m -20.828m -22.30V -2.381m -53.586m -21.80V -33.00V -36.600m -3.30V -35.635m -61.352m -60.788m -21.913m 3.632m -19.216m -60.556m -58.324m -3.650m -58.749m -18.024m 4.00V -5.70V -39.453m 5.801m -63.630m -19.185m -3.20V -38.00V -38.019m 3.254m 4.80V -4.20V -40.332m -22.361m 4.742m -6.032m -64.489m -21.157m -21.436m 3.709m -9.00V -34.997m -56.20V -34.137m -21.70V -36.043m -24.277u 0.827m -58.20V -6.10V -37.70V -38.631m 3.916m 3.60V -39.135m -20.714m -22.70V -4.121m -23.874m DSP56364 Technical Data.50V -30.506m 5.643m -21.211m -22.681m 3.909m -59.741m -58.80V -38.50V -37.499m 1.730m -18.689m -23.780m 4.288m -64.50V -39.762m -8.30V -6.80V -36.194m 4.

30V -20.537m -1.597n -0.60V -85.466 -849.801p -20.645p -12.303 -759.080m -75.614m -0.370m -24.771 -2.878u -295.181p -24.579 -2.131m -1.345m -629.10V -116.30V -262.150p 0.50V -416.20V -187.009p -38.140m -27.711 -983.1 Freescale Semiconductor A-13 .60V -48.610p 0.70V -4.235m -0.10V -896.564n -47.027m -37.80V -655.50V -48.20V -1.537p 144.029 -2.091p DSP56364 Technical Data.505m 5.783p 111.415m -1.177p -8.007 -1.884m -845.971n -8.263p -28.259m -1.883m -273.214m 5.929m -73.934m -1.10V -30.031m -6.60V -8.068p -30.485m -443.249p 0.483 -2.065m 6.183u -0.740m -581.769m -26.300m -1.177m -404.30V -1.675 -2.033u -33.075m -1.80V -49.059 -625.40V -47.40V -338.110p 0.50V -1.678m 6.20V -25.330m -262.50V -12.70V -575.90V -43.452m -448.769m -1.30V -46.493m -1.899m -25.80V -42.60V -495.10V -44.40V -17.979n -0.287m -27.385 -804. 4. 5.70V -476.210p 0.80V -1.049u -2.900n -262.90V -16.415m -69.072m -188.888p -16.760m -106.102 -2.388m -1.963 -2.844m -230.399m -146.90V -735.858p 10.30V -1.221 -714.781m -1.842m -95.990p -214.206p 0.052m -1.987p -2.095m -25.227m -1.171p 0.307p 45.167m -723.90V -1.197 -2.983m -68.548p -4.551m -1.449p -0.766m -316.60V -41.646u -9.10V -1.473m -25.711m 6.498m -26.639m -1.180m -817.40V -432.930u -0.140 -670.20V -977.293p 177.30V -21.779m -536.593m -1. Rev.80V -2.155 -3.255m -14.049m -28.074 -2.548 -893.130p 0.00V -36.487m -74.983m 5.886m -24.621m -352.018p -33.70V -42.292 -2.00V -44.50V -8.880m -66.990m -29.20V -968.70V -1.10V -75.576u -310.390m -71.374m 6.570m -65.893m -175.875 -1.646m -1.501u -147.059 -3.735m -1.388 -2.815m 6.247m -360.999u -0.510p 0.20V -45.40V -1.869p -34.033p 78.585m -67.308n -3.635f 209.761m -536.848m 6.878n -340.60V -1.217m -66.721m 6.884m -70.748m | [GND_clamp] | |Voltage I(typ) I(min) I(max) | -3.370m -0.321m -2.793 -1.

025p 1.731p 72.259m -1.674p 306.614m 4.074p 626.622p 1.60V -31.493m -912.452m -581.10V -655.221 -849.052m -536.50V 29.80V -8.510p 3.971n -24.156p 36.50V 72.90V 46.154p 370.265p 2.110p 2.987p -3.80V 81.352p 530.30V -1.316p 658.70V -432.984p 1.370m 4.219p 2.799p 52.308n -2.735m 5.60V -262.519p 48.30V -36.30V 96.766m -448.167m -175.907f 1.60V 76.072m -316.20V 90.164p 2.779m -670.30V 21.146p 2.255m -106.20V 59.112p 498.303 -893.237p 2.633p 434.646u -33.129p 28.345m -95. 0.449p 3.056p 1.802p -71.579 DSP56364 Technical Data.621m -2.256p 2.30V -55.129p 64.40V -896.639m 5.769m -1.548 -1.178p 864.466 -983.217p 40.485m -6.70V 38.646m -443.147p 20.002p 1.443p 68.893m -147.60V -1.630 -1.965p 1.102 5.781m -817.249p 3.274n 89.760m -230.652p 3.50V -187.388m 5.074 -1.40V -75.183u 4.070p 7.537m 4.999u 4.003m -625.50V -968.092p 1.027m -146.203m 4.559p 691.50V -977.080p 56.70V -338.844m -360.610p 3.131m -723.593m 5.70V 79.70V -1.300m 5.838p 835.068p -33.551m -629.90V 4.179m 5.761m -33.30V 63.60V -20.129p 1. Rev.592p 562.124p 11.20V -1.534p 76.140 -804.10V 55.131p -33.210p 3.640m -188.597n 4.146p 16.80V -1.40V -116.080p 3.247n 87.192p 241.388 6.200p 2.415m 5.180m -262.733p 1.1 A-14 Freescale Semiconductor .990p -340.883m -404.90V -1.234n 85.770p 80.182p 2.501p 3.197 6.029 -1.40V 25.330m -845.501u -38.878u -37.399m -273.90V -85.740m -714.10V 88.793p | [POWER_clamp] | |Voltage I(typ) I(min) I(max) | 3.90V -495.90V 84.914p 338.40V 67.803p 722.10V -2.059 -759.038p 1.10V 12.031m -8.206p 3.930u 4.033u -14.007 5.177m -536.044p 751.878n -295.30V -816.80V 42.10V -1.20V -16.20V 16.576u -28.224p 60.138p 24.075m -1.788p 466.020p 1.235m 4.934m -1.20V -735.409p 807.321m -262.842m -9.80V -416. 4.884m -47.393p 402.162p 779.483 6.

155u -124.50V -839.321p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipad5v_io | "" Model_type I/O Vinl = 0.668p | dV/dt_r 2.1 Freescale Semiconductor A-15 .90V -419.737u -510.90V -176.764m -0.20/122.749m -0.30V -1.367u -1.20V -300.675 6.182u -3.259m -21.96p 1.0 0.094u -353.403u -159.30V 3.70V -563.678u -2.8 Vinh = 2 | variable typ min max C_comp 1.40V -1.02/200.900u -285.492p 1.318u -573.875 -1.20V -149.83/223.367u -134.711 -1.869u -268.314u -175.00V -10.107u -2.80V -188.107u -2.068u -2.239u -215.50V -1.80V -481.679u -305.30V -273.01/129.094m -511.488u -460.013u -1.825u -145.857m -1.162m -1.00V -166.093p 1.088m -1.594p 2.119 -1.0 | variable typ min max [Voltage Range] 3.472u -252.191u -2.360u -1.382u -338.20V -2.10V -157.325u -652.60V -215.873m -1.273u -2.303u -76.30V -142. 6.992u -94.446u -2.700u -80.70V -201.267m -5.808u -418.819m -1.0 120.06p | variable typ min max [Temperature Range] 40.300u -1.145u -383.87p 2.60V -1.746m -20.00V 3.349u -327.882u -287.164 -1.925u -893.537m -670.874u -2.50V -232.793 -1.851m -7.00V -371.90V -14.432u -3.60V -676.295u -100.616u -238.286u -195.20/79.10V -4.486m -12.451m -943.80V -13.369u -754.845u -5.892u -1.606m -2.866u -3.40V -1.867 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 2. 4.209 -1.142m DSP56364 Technical Data.446u -2.973u -1.214m -1.861u -84.868u -219.83/352.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.108m -20.10V -332.226u -226. Rev.968u -249.167u -2.383m -1.515p 2.418u -1.40V -251.545u -115.350u -2.410u -409.049u -107.908u -89.771 6.

064m 5.211m -0.849m 0.257m 27.040m 27.985m 26.00V 50.938m 41.394m 100.40V 45.482m 0.10V 50.023m 8.840m 105.345m 4.884m 2.598m 38.30V 51.378m -4.034m 32.543m 2.587m 84.305m 25.409m 3.572m 83.302m 27.080m -2.50V -9.727m 27.074m 2.90V 51.981m -0.612m 23.956m DSP56364 Technical Data.962m 101.726m 1.686m 85.249m 4.825m 0.079m 70.288m -10.1 A-16 Freescale Semiconductor .922m -0.584m -0.414m 1.611m 15.291m 94.383m 1.10V 51.276m 4.50V 69.165m 3.30V 49. Rev.224m -8.515m 3.80V 51.546m 7.70V -12.276m 3.674m 84.441m 31.633m 77.199m 81.282m -0.857m 1.465m 83.585m 24.800m 0.724m 2.70V 70.481m -7.011m 1.491m 3.00V 51.60V 9.467m 4.20V 41.30V 5.482m 3.872m 82.40V 51.999m 39.736m 3.40V 51.00V 36.20V 3.733m 26.10V -1.10V 39.849m 4.065m 106.60V 57.503m -0.00V 63.885m -1.723m 7.039m 80.726m 21.057m 2.651m 2.223m 81.871p 0.70V 58.156m -5.657m 83.70V 11.60V 51.219m 4.190m 30.294m 2.522m 83.430m 3.630m 2.745m 56.724m 2.323m 3.700m 84.046m 40.618m 83.441m 1.247m 67.50V 51.836m 39.40V -7.70V 48.153m 79.40V 6.290m 3.042m 84.798m 12.321m 82.704m 1.168m -18.20V 65.773m 25.70V 51.244m 64.743m 4.50V 8.577m 84.80V 12.60V 70.363m 33.40V 67.30V -5.905m 79.30V 43.90V 61.725m 36. -0.10V 1.059m 4.00V 1.30V 66.708m 1.332m 2.371m 17.391m 22.925m 20.154m -5.572m -3.741m 73.80V 49.20V -3.90V 13.155m 0.497m 27.069m 40.50V 54.783m 1.030m 2.997m 26.755m 98.339m -13.612m 27.741m -2.757m 27.399m 82.229m 28.165m 34.20V 49.092m 80.766m 1.90V 50.20V 51.80V 60.628m 4.735m 1.60V 47.883m -6.275m 6.073m 0.60V -10.182m 27.915m 5.935m 10.052m 0.035m 37.898p 1.328m 35.834m 34.077m 3.50V 46.348m -15.936m 3.171m 84.858m 27.658m 27.319m 38.078m 19.10V 64.051m 96.405m 27.508m 0.453m 103.581m 27.419p 1.074m 60.176m 0. 4.495m 91.251m 75.744m 2.

267m 5.836u 37.445u 202.476m 40.40V 70.444m 13.478u -2.982u -2.342u 65.007u -2. Rev.929m 110.581u -2.1 Freescale Semiconductor A-17 .624m 39.344m 5.582u 305.508m 115.457u -1.536u 83.812m 110.70V 163.169m -0.449m 6.899u -1.966u 56.00V 7.785u -2.313m 112.389m 39.50V 70.489m 39.361m 39.978u 460.826m 5.817m 39.797u 7.907u 109.901m 39.672m 110.448m 4.10V 73.743m 110.00V 119.451u 46.552m 116.807u -2.723u 494.595m 114.942m 8.046u -1.40V 205.119u 223.833m 12.699u -1.332u -2.00V 70.708m 110.005m 39.30V 218.80V 148.776u -2.423u 145.754u 100.710u 151.998u 443.50V 191.061u 131.10V 70.595m 6.90V 134.30V 72.20V 70.395m 111.477u -3.262u 346.231m -1.914u 161.348u 157.988u 405.953m DSP56364 Technical Data.693m 5.80V 280.753m 39.358m 113.50V 311.732m 4.70V 70.30V 75.460m 115.777m 110.886m 110.285u 92.382m 6.557m 39.410m 114.527u 326.089m 39.00V 257.690m 39.694u 243.474u -2.90V 6.10V 244.751m 40.50V 3.321m 39.626u 1.519u 138.261m 2.515m 6.90V 269.659u 424.40V 71.160u 27.464u 17.90V 72.297m 5.20V 9.20V 73.699u 181.686m 6.971m -0.881m 39.40V 729.510m 445.651m 39.00V 73.949m 39.089u -1.455m 6.447u 285.899u 162.004m 3.60V 70.139m 5.576m -1.80V 5. 4.70V 291.80V 71.20V 90.70V 5.60V 70.190m 10.016u 386.531m 39.766u 366.848m 110.670m 5.106u 124.551m 9.381m 4.144u 264.757u -2.30V 10.80V 70.106m 5.612m -1.10V 105.483m -0.825m 3.952m 108.20V 231.832m -1.417u 521.517u 14.314u -3.706u 116.10V 8.779u -3.917m 5.400m 5.612m 6.549m 2.565u 478.629m 6.885m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.90V 70.634m 111.30V 70.422m 39.543u 74.60V 177.60V 4. 4.406u -1.50V 70.869m 5.854m -0.582m 5.783m 6.401m 5.067m 109.921m -0.60V 301.

608m -20.50V -37.20V -38.185m -3.600m -3.253m -62.60V -3.40V -2.575m -20.620m 1.393m -19.590m -22.927u -990.702m 0.614m -1.916m 3.917m 2.50V -30.10V 722.762m -8.241m -56.00V -38.817m 0.420m -60.292m 1.632m -19.20V -37.40V -38.489m -21.079m -4.832m 0.332m -22.932m 2.319m -2.791m -21.60V -36.997m -62.024m 4.324m -3.284m -60.635m -61.20V 1.240m 2.737m 1.90V -5.561m -61.798m -61.457m -57.192m -2.819m 4.70V -38.143m -59.60V -31.003m -0.340u 478.081p 0.997m -56.960m -20.352m -60.60V -37.647u 0.861m -55.780m 4.007m -1.279m -10.067m -59.741m -58.710m -3.341u 1.736m -3.70V -39.556u -465.1 A-18 Freescale Semiconductor .329p 36.827m -58.086m 1.893m -23.730m -50.131m -47.742m -6.714m -22.327m -21.556m -58.00V -5.551m 2.211m -22.978m -21.980m -3.70V -4. 4.70V -36.055m -19.936p 24.423m -5.40V 2.076m -22.90V -39.00V -36.631m 3.713m -61.10V -708.681m 3.749m -18.643m -21.943m 0.202m -22.510m 2.70V -32.253m -2.978m -0.828m -22.80V -38.80V -36.60V -39.302m -20.841m 1.973m -51.715m -54.10V -34.802m 1.454m -49.20V -1.00V -39.426m 2.377m -903.406m 4.30V -35.631m -17.50V -3.573m 4.20V -34.516m -22.738m -2. Rev.135m -20.90V -33. -0.987m -0.683m 3.80V -39.392m 1.556m -54.788m -21.035m 2.336m 0.547m -8.188m -52.460m -22.730m -18.334m 3.80V -33.070m -22.90V -36.884m -20.123m -56.913m 3.989m -59.30V -37.949m -22.181m 3.505m 2.194m 4.933m -22.30V -38.693m -23.10V -38.90V -38.537m 0.709m -9.00V -34.254m 4.489u 2.983m 1.506m 5.352m -57.20V -6.216m -60.137m -21.948m -9.10V -37.499m 1.139m 1.80V -4.909m -59.50V -39.40V -37.00V 22.157m -21.785m DSP56364 Technical Data.357m -22.361m 4.902m 3.135m 1.747m -45.30V -6.30V -2.463m 2.142m 3.50V -35.630m -19.571m 2.370m -21.265m 1.005m -0.305m -7.096m 0.381m -53.892m -62.019m 3.623m 4.10V -5.637u -1.650m -58.437m 951.40V -35.436m 3.586m -21.40V -29.037m -6.490m -60.30V 2.986m 4.322m 2.116m -62.

121m -23.30V -40.466 -849.20V -40.618m -352.330m 5.287m -27.579 -2.482m -443.944n -8.254m -14.30V -20.689m -23.140m -27.411m -63.217m -66.30V -1.029m -6.990m -29.895n -258.304n -3.10V -44.90V -1.140 -670.983m 5.384m -23.80V -655.877u -295.735m -581.222m -1.848m 6.70V -476.80V -42.40V -432.878m -273.40V -1.080m -75.30V -18.773m -536.30V -262.483 -2.595m -63.505m 5. 4.649p -0.473m -25.587m -1.678m 6.612m -0.90V -735.303 -759.675 -2.043m -24.095m -25.059 -3.155 -3.637u -9.931m -1.769m -26.10V -72.771 -2.370m -24.50V -48.975n -0.777m -1.886m -24.60V -85.20V -964.098m 5.60V -48.033u -33.395m -146.059 -625. Rev.164m -723.446m -448.748m | [GND_clamp] | |Voltage I(typ) I(min) I(max) | -3.342m -629.906p DSP56364 Technical Data.730m -1.292 -2.883m -845.665p -30.049m -28.711m 6.102 -2.983m -68.20V -977.765m -1.444m -24.10V -896.214m 5.891m -175.583p -2.390m -71.875 -1.30V -46.593n -0.065m 6.548m -1.685p -210.748p 0.548 -893.197 -2.815m 6.171m -404.327m -262.910p 0.70V -1.20V -45.074 -2.048m -1.231m -0.585m -67.409m -1. 5.370m -0.221 -714.70V -42.610p 0.029 -2.354u -147.453m 5.999u -0.560n -43.90V -16.634m -1.874n -340.40V -41.20V -22.839m -230.801m -63.50V -416.288m -64.024m -37.60V -1.242m -360.930u -0.10V -40.70V -575.10V -27.874m 5.415m -69.00V -44.20V -187.032m -64.385 -804.642m -1.40V -47.929m -73.756m -106.50V -1.50V -41.319m -2.570m -65.1 Freescale Semiconductor A-19 .498m -26.487m -74.30V -1.388 -2.793 -1.711 -983.127m -1.110p 0.880m -66.356p -20.60V -41.884m -70.10V -116.374m 6.071m -1.546p -25.628p -29.20V -1.508p -34.067m -188.90V -43.384m -1.80V -1.303p 48.564p -30.754p 13.40V -338.576u -310.721m 6.760m -316.295m -1.50V -8.256m -1.899m -25.963 -2.860m 5.533m -1.015u -2.758m -536.839m -95.00V -33.80V -2.177m -817.489m -1.60V -495.007 -1.10V -1.181u -0.

335p 14.593n 4.127m -723.910p 3.910p 30.454p 212.618m -2.30V -815.30V 64.924p -5.264p 69.20V 60.847p 751.60V 76.906p 3.637u -29.576u -25.60V -5.869p -16.20V -16.388p 10.971p 0.849p -13.90V 84.30V 23. Rev. 4.715p 499.370m 4.265n 86.250p 18.110p 3.773m -670.70V 39.80V -416.335p 2.839m -9.181u 4.777m -817.564p 2.587m 5.610p 3.706p 723. 0.40V -14.533m 4.139p 1.60V 35.130p 0.30V -55.573p 1.499p -9.140 -804.221p 1.70V -432.304n -2.735m -714.027p 26.017p 340.40V -896.057p 1.50V -964.722p 37.877u -37.436p 436.90V -85.30V -33.883m -43.805p 33.642m -443.188p -1.50V -9.999u 4.384p 1.033u -14.10V -2.10V 14.195p 3.10V -655.646p 2.933p 53.442p 73.499p 835.065p 2.758m -33.748p 3.30V 103.157p 372.256m -1.839m -360.319m -258.973p 65.106p 57.90V 47.564p -33.395m -273.979p 114.067m -316.689p 179.576p 467.018p 1.489m -912.482p 2.129p 81.877p 308.466p 1.344p 3.342m -95.20V -735.730m 5.418p 659.291p 0.974p 1.059 -759.513p 77.164m -175.70V -1.675p 41.478p | [POWER_clamp] | |Voltage I(typ) I(min) I(max) | 3.048m -536.70V 80.60V -262.354u -34.90V 6.833p 147.837p 860.384m 5.794p 3.80V 2.1 A-20 Freescale Semiconductor .760m -448.297p 404.634m 5.60V -20.20V 19.143p 22.70V -338.810p 2.612m 4.892p 1.50V -187.391p 80.10V 56.80V 82.400p 2.891m -147.50V 72.050p 0.174m 5.761p 49.70V -1.295m 5.40V -116.628p 1.90V -495.482m -6.40V -72.409m 5.756m -230.231m 4.60V -1.007 DSP56364 Technical Data.548m -629.50V 31.237p 2.636m -188.177m -262.40V 27.561p 692.80V -8.108p 1.210p 0.10V 89.944n -20.995p 563.199m 4.869p 780.327m -845.20V 89.878m -404.142p 61.029m -8.593n 90.40V 68.446m -581.649p 3.50V -977.685p -340.302p 1.583p -3.171m -536.319p 2.874n -295.930u 4.855p 531.997m -625.596p 244.305n 88.024m -146.254m -106.80V 43.074p 808.277p 627.156p 2.

240u -289.50V -252.00V -183.277u -352.30V 3.17p 2.976u -516.711 -1.40V -1.407u -496.793 -1.283u -169.346u -909.86/341.987m -1.134u -99.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3. Rev.146m -6.20V -2.20V -325.197 6.386u -256.00V 3.822m -12.32p 2.191m -619.822p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipada_3st | "" Model_type 3-state | variable typ min max C_comp 2.219u -2.0 120.80V -206.623u -1. 4.384u -218.011u -1.133m -1.217u -306.685u -3.00V -400.579 6.590u -464.20V -165.024u -1.699m -811.10V -1.479u -242.851u -660.60V -729.148u -121.265u -387.90V -452.30V -157.466 -983.901u -242.221 -849.162u -183.405p 2.037u -104.029 -1.117u -2.355u -2.102 5.045u -413.70V -607.217u -1.115m -1.286u -2.500u -2.630 -1.05/194.10V -359.412p 2.595u -2.071m -1.30V -1.000u -3.04/134.874p | dV/dt_r 2.875 -1.0 0.190u -146.50V -907.40V -273.002p 1.675 6.931m -1.483 6.176u -2.30V -1.427u -199.90V -194.189u -129.750u -270.1 Freescale Semiconductor A-21 .749u -109.765m -1.934u -2.974m DSP56364 Technical Data.256u -219.119 -1.10V -5.48p | variable typ min max [Temperature Range] 40.199u -357.80V -519.127u -230.30V -297.70V -219.689m -1.766u -137.074 -1. 5.856u -157.20V -1.431u -308.799m -1.434m -1.60V -1.388 6.936u -271.867 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 2.548 -1.079u -3.549u -765.681u -1.933u -2.50V -1.80V -1.86/235.236u -422.680u -331.400u -115.0 | variable typ min max [Voltage Range] 3.40V -1.303 -893.838p 1.771 6.60V -235.837u -2.23/118.90V -1.299u -579.270u -1.209 -1.811u -1.10V -173.23/85.250u -3.243m -1.164 -1.

70V 127.30V 126.527m 201.541e-18 -1.948m 72.10V 125.639m 1.411m 4.147m 72.113m 4.80V -11.70V 9.302m -17.208m 23.017m 2.776m 72.948m -0.928m 3.232m 70.652m -9.60V 119.643m 71.661m 0.992m 196.284m 0.708m 67.577m 71.612m 195.214m -1.416m -3.313m -0.000m 70.672m -6.286m -3.710m 192.10V -1. Rev.863m 3.20V -3.614m 72.10V 127.40V 130.966m 4.80V 128.775m 4.00V 129.40V -6.792m 12.335m 200.563m 17.90V 11.00V -10.30V 130.529m 5.338m -0.40V 128.80V 10.372m 8.990u -2.20V 13.316m 73.20V 3.821m 7.528m -6.203m DSP56364 Technical Data.296m 197.784m 0.50V 128.432m 14.503m 4.1 A-22 Freescale Semiconductor .479m -16.304m 72.146m -15.607f 0.80V 123.034m 2.447m 2.00V 124.622m 2.692m -0.784m 73.410m 0.190m -0.342m -5.151m 197.855m 0.138m 1.964m -0.858m 0.20V 129.930m 64.30V 14.30V 4.194m 3.449m -17.124m 1.876m 2.30V -4.50V 7.508m 6.20V 127.764m 202.562m 6.50V 117.458m 72.00V 32.60V 126.944m 1.417m 8.428m 198.667m 68.621m 2.957m 1.593m 0.263m 2.958m 3.774m 199.90V 127.874m 1.90V -12.817m 0.973m 199.305m 70.513m 184.638m 201.856m 1.814u 2.814m 196.023m 15.562m 22.152m -0.650m 70.621m 72.00V 12.387m -13.20V 125.60V -9.093m 202.275m 3.066m 200.367m 7.189m 21.40V 5.361m 72.575m 1.083m 194.551m 198.405m 3.055m 69.260m 71.10V 1.051m 18.90V 124.934m 73.498m 187.311m 203.871e-18 18.245m 200.846m -4.711m 70.818m 71.983m 2.10V 129.40V 14.156m 200. 4.70V -10.050m 71.604m 910.486m 19.999m -0.206m 190.472m 3.770m -4.428m 201.865m 20.50V 126.986m 71.90V 129.579m 204.80V 127.00V 127.667m 3.666m 198.020m 69.774m 4.928m 3.914m 202.576m 3.647m 1.60V 8.815m 2.740m -0.138m 7.50V -7.595m 6.391m 0.70V 121. -1.524m 4.535m -11.453m 2.094m 66.30V 128.566m 2.876m 199.766m -2.823m 71.817m 1.10V 13.374m 195.138m 3.204m -5.627m -928.457m 71.70V 128.306m 1.40V 126.60V 128.210m 4.140m 72.105m 10.754m -6.

421u 365. Rev.060m 74.659m 5.912m 74.10V 138. 4.787m 207.90V 337.1 Freescale Semiconductor A-23 .308m 78.494u 264.694m 225.90V 8.736u 160.110u -2.880u 850.836m 215.778u 120. 4.60V 210.148m -0.333m 105.80V 8.10V 145.237m 1.70V 179.149m 5.418u 306.056m 5.102u 238.559u 109.326u 150.029m -0.419m 5.029m 260.090m 2.723u -2.60V 132.013m 4.300u -2.70V 431.319m 6.700u 1.062m -0.00V 303.583m 10.368m 208.810m 6.000u -3.825u 186.60V 6.90V 135.50V 597.30V 142.706u 141.70V 7.009m 298.40V 194.395u 567.20V 138.941u -2.979u 100.358m 73.141u -2.004u 590.10V 276.50V 201.096m 287.300m 87.033u -1.80V 133.00V 4.597m 80.478m 89.80V 378.065m 6.993m 113.651u 126.128m 4.087m -1.80V 169.00V 169.648u 206.730u -1.032m 4.10V 174.939m 75.20V 180.00V 152.324m 77.30V 187.362u 333.344u 171.778m -0.605u 247.906m 205.640m 246.128m 8.712m -1.644m 1.113u 336.20V 1.393m 5.90V 164.981u 196.097m 92.012u 2.070m 6.852u 232.513u 199.748u 1.192m 83.194m 5.722u -1.513u -2.355m 229.497m -1.544m 5.060m 210.810u -1.465m 278.304m 206.670m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.316m 240.033m 4.20V 140.118m 117.166m 76.112m 269.984u 105.60V 190.80V 159.60V 151.276m 4.40V 217.789u 114.400m 109.30V 132.70V 132.90V 160.20V 253.10V 2.415u -2.70V 155.067u -1.50V 131.30V 960.115u 178.155u 404.340u 451.619m 76.443m DSP56364 Technical Data.692u 184.830u 217.045m 4.40V 737.781m 101.948m 218.562u 133.630m 5.208m 253.174u 283.806m 6.230m 221.217m 81.669m 5.602m 6.734m 98.906u 218.60V 501.177m 95.803u -2.224m 234.211m 309.641u 462.40V 145.240u 389.727m 11.705m 321.754m 9.50V 203.255m 6.348m -1.907m 12.763m 4.253u -2.910u -2.075u -3.361m 731.00V 136.794u 170.878m 212.601u 697.081u 512.317u 264.50V 148.118m 4.877u -1.351u 296.702u -3.277m 5.30V 234.545m 85.

988m 0.265m -228.013m -83.493m -226.410m -0.828m -1.625m -213.20V -129. 4.40V -138.539m -13.30V -138.022m -221.277m -222.70V -119.10V -127.269m -3.994m -3.346m 2.195m -72.010m -70.004m 3.877m -211.10V -987.370m 1.462m -81.954m -200.971m -215.297m -73.10V -137.50V -144.599m -194.80V -135.306m -4.70V -134.106u -655.408m -82.311m -197.581m 2.740m -226.057m -78.563m -13.647m 1.761m -220.40V -3.910m -186.943m -82.387m 1.137m 4.585m -83.804m -190.255m 2.866m -8.504e-18 0.859m -3.399m 2.756m -80.890m -4.40V -143.552m 3.109m 3.30V -9.20V -8.00V -141.611m -154.30V 3.10V 1.082m 2.052m -0.80V -6.081m 1.713m -176.60V -144.30V -143.424m -5.908m -80.861m -229.856u 1.928m -1.783m -71.417m 4.20V -137.339m -65.010m -224.381m 0.733m -75.561m 1.931m -6.586m 4.996m -227.709m 0.90V -145.441m 7.014m 678.658m -10.964m -81.20V 2.60V -5.893m -181.499m -2.687e-18 58.363m 2.098m 3.00V -7.937m 2.525m -223.60V -117.216m 0.516m 0.70V -140.00V -126.50V -139.80V -122.920m -218.650m 3.053m 4.449m -83.587m 0.880m 3.447m -81.656m DSP56364 Technical Data.139m -75.20V -142.301m -12.280m -9.392m 0.644m -0.70V -5.30V -130.90V -124.704m 2. Rev.210m -218.709m 4.323m 1.416m -7.159m -83.551m -228.40V 4.10V -8.746m 5.00V -136.056m 2.037m -208.575m -206.792m -79.300m -82.384m -76.50V -4.604u -1.504m -77.90V -7.733m -83.067m 3.90V -135.498m -77.483m -79. -0.345m -80.1 A-24 Freescale Semiconductor .50V -132.40V -131.077m -204.540m -202.683m 2.412m -5.250m -225.136m -79.344m 4.274m -2.00V 58.622e-18 117.999m -11.80V -140.993m 3.370m -84.423m -78.60V -133.438m 1.907m -5.233m -0.673m -4.006m 4.20V -1.131m -74.602m 0.468m 2.490m -219.30V -2.60V -139.732m 3.685m -2.079m 3.80V -145.899m -84.270m -78.798m 1.871m -84.617m -217.40V -110.821m -0.302m 1.033m 1.10V -142.814m 2.470m -209.50V -113.300m 4.864m 3.879m 4.302m -216.461m 1.70V -144.311m -170.769m -223.261m 2.261m -212.112m 4.858m 4.90V -141.807m -69.103m -67.50V 5.860m -82.

023m -259.351n -6.194m -90.662u -0.387 -2.00V -27.859m -1.132 -2.30V -163.273m -255.494m -142.544m -1.30V -2.311m -563.425 -1.20V -161.930m -241.339m -89.583m -317.163p 0.021 -1.652m -85.354m -257.054p -13.242 -2.00V -156.80V -2.637 -1. Rev.650m -0.598p -810.221m -363.70V -877.406 -1.963m -263.20V -19.20V -2.802p -890.425m 6.531m -102.909u -271.709p -1.059 -1.685m 6.044u -0.195m -86.464m -233.40V -1.20V -147.515 -2.149m -886.011m -94.212n -18.10V -153.481m 5.60V -1.904m -1.105 -2.50V -14.697 -2.833 -2.907m -92.115m -87.098n -15.379m -86.373m -0.592m 5.226m -4.921m -243.457m -45.001m -85.924m 5.10V -2.561 -2.30V -1.109m 6.519m -1.404m 5.70V -152.838u -397.138m -127.50V -575.20V -1.129m -491.30V -357.995m -234.750m -1.174 -1.10V -92.597m -235.70V -799.40V -465.336m 5.514 -3.771p -16.073m -1.124m 5.314m -198.668n -598.200m -230.10V -1.683p 0.160m -98.378 -2.086u -560.215m -0.288m -1.535m -16.297m -753.20V -1.40V -166. 5.106m -268.640u -3.514u -53.223m 6.60V -151.715m -377.377m -501.10V -22.516p DSP56364 Technical Data.063 -3.10V -147.926 -3.969 -2.071p -5.575m -231.280m -237.182m -99.195 -2. 4.521 -1.667m -1.80V -153.80V -3.103m -439.613m -0.004 -1.10V -158.90V -155.60V -687.038m -245.789 -2.155 -1.601u -18.70V -1.254 -751.259 -2.368 -814.437n -0.00V -146.90V -2.483 -877.598 -941.294m -248.157m -88.904m -621.839m -93.475m -1.395m -1.993m -232.293m | [GND_clamp] | |Voltage I(typ) I(min) I(max) | -3.332p -0.50V -1.847m -1.943 -1.30V -148.054m -239.368m 5.739n -411.357m -1.041m 6.939p 0.80V -912.701m -251.699n -55.90V -19.50V -150.595m 6.068 -2.20V -252.426m 5.614m -240.444m -96.678m -89.046m 5.451 -2.1 Freescale Semiconductor A-25 .713 -1.026 -625.828 -1.308n -0.410n -29.40V -149.40V -780.305m -11.897m -1.60V -156.50V -169.60V -172.411m -85.90V -1.30V -37.465m 6.

385p 448.939p 3.60V 54.929p 149.226m -411.581p 2.20V 68.634p 10.10V 65.311m -751.673p 619.709p -598.896f -442.668n -397. 0.954p 1.70V 26.90V -156.40V -92.254 -941.785p 49.467p 12.754p 30.136p -383.647p 733.80V -955.715m -563.483 -1.765p -10.712p 2. 4.296p 44.595p 0.404p -2.044u 4.535m -142.50V 51.631m -257.904m -11.483p 507.50V -1.414p 28.357m -240.762p 2.305m -15.50V -252.60V -357.30V -1.859m 5.650m 4.026 -814.852p 2.40V -13.906n 61.60V 23.018p 208.10V 8.868p 55.987p 23.90V 2.489p 2.674p 1.258p 57.291p 387.098n -10.579p -87.414p -318.40V -1.164p 26.20V -19.401p 2.614m -271.666p -28.90V -687.873p 39.353p -683.909u -18.50V 20.30V -69.801n 63.050p -502.247p -622.021 5.514u -16.699n -53.70V -465.80V 59.245p 18.583m -501.297m -43.494m -317.40V 17.315p -264.70V 57.215m 4.129m -4.799p -8.60V -7.862p 1.039p 1.667m 5.10V -3.585p 3.290 DSP56364 Technical Data.859p 5.437n 4.562m 4.613m 4.847m -363.70V -780.234p 0.10V 39.20V 42.133p 1.492p -146.004 -1.30V -16.156p 52.838u -45.147p -562.149m -127.897m 5.30V 45.956p 0.332p 3.073m -1.717p 807.236p | [POWER_clamp] | |Voltage I(typ) I(min) I(max) | 3.221m -1.103m -625.20V 11.874p 0.904m 5.468p -745.10V -912.662u 4.404p 1.198p 327.40V -153.351n -3.516p 3.30V 72.475m -621.1 A-26 Freescale Semiconductor .769p 31.040p 2. Rev.802p -5.30V -27.60V -1.163p 3.373m 4.928p 3.318p 0.217p 4.346p 15.40V 48.071p -6.80V 29.80V -575.125p 2.20V -1.288m -29.601p 620.50V -1.962f 0.601u -16.583p 563.768p 1.468p 676.086u -13.068 -1.395m 4.310p 2.498p 1.80V -14.675p 3.60V -37.404p -205.155 5.141p 20.683p 3.012p 41.227p 1.90V 61.138m -18.949p 36.90V 33.368 -1.50V -10.856p 47.841p 90.750m -886.544m -753.30V 14.354m -439.874p 3.457m -198.216p 2.70V -4.140 -877.003p 59.314m -377.266n 65.

85/212.20V -165.195 -1.179p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipadd_io | "" Model_type I/O Vinl = 0.60V -729.811u -1.132 -1.431u -308.256u -219.17/69.80V -519.127u -230.400u -115.299u -579.578 -2.561 5.598 -1.90V -194.406 -1.219u -2.80V -1.00V 3.40V -2.936u -271.024u -1.134u -99.427u -199.479u -242.10V -359.680u -331.521 -1.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.434m -1.60V -235.236u -422.148u -121.80V -206.52p | variable typ min max [Temperature Range] 40.117u -2.90V -452.010p 1.81/184.1 Freescale Semiconductor A-27 .115m -1.174 -1.037u -104.059 -1.217u -306.99/110.172p 1.0 120.652 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 1.70V -1.199u -357. Rev.277u -352.681u -1.217u -1.837u -2.706 -2.40V -273.20V -325.259 -1.515 6.126p 2.637 -1.240u -289.595u -2.10V -173.30V 3.283u -169.190u -146.242 6.933u -2.387 -1.70V -607.384u -218.10V -2.766u -137.21p 2.901u -242.011u -1. 5.750u -270.987m DSP56364 Technical Data.934u -2.20V -2.828 -1.105 6.856u -157.976u -516.0 0.00V -400.697 6.000u -3.286u -2.378 6.30V -2.50V -2.60V -2.623u -1.90V -1.265u -387.50V -252.642 -2.250u -3.176u -2.0 | variable typ min max [Voltage Range] 3. 4.355u -2.189u -129.40V -1.974p | dV/dt_r 2.50V -907.590u -464.30V -297.685u -3.514 -2.30V -157.749u -109.162u -183.045u -413.851u -660.70V -219.8 Vinh = 2 | variable typ min max C_comp 2.713 -1.451 -2.00V -183.500u -2.270u -1.463p 2.191m -619.34p 2.969 6.425 5.407u -496.386u -256.549u -765.346u -909.04/120.290 -1.21/73.

133m -1.90V -12.405m 3.822m -12.286m -3.050m 71.774m 4.428m 198.948m -0.416m -3.770m -4.621m 72.855m 0.146m -6.20V -2.00V -10.432m 14.990u -2.10V 1.214m -1.20V -3.821m 7.638m 201.30V 126.973m 199.562m 22.20V 127.50V -7.667m 3.593m 0.30V 128.776m 72.40V -6.508m 6.105m 10.10V -5.051m 18.374m 195.361m 72.367m 7.20V 13.576m 3.60V 119.60V 128.20V 125.815m 2.151m 197.479m -16.846m -4.453m 2.80V 127.50V 126.689m -1.874m 1.614m 72.498m 187. 4.60V 8.667m 68.284m 0.622m 2.566m 2.948m 72.80V -11. -1.964m -0.70V -10.70V 121.70V 127.30V 14.876m 2.551m 198.928m 3.871e-18 18.90V 127.974m -1.417m 8.814m 196.40V 14.865m 20.563m 17.017m 2.823m 71.999m -0.652m -9.60V 126.513m 184.138m 3.152m -0.338m -0.243m -1.650m 70.60V -9.194m 3.527m 201.957m 1.30V 4.00V 127.607f 0.10V 127.944m 1.40V 5.342m -5.079u -3.529m 5.066m 200.00V 129.296m 197.30V -1.503m DSP56364 Technical Data.928m 3.387m -13.930m 64.023m 15.540e-18 -1.410m 0.147m 72.799m -1.577m 71.775m 4.70V 9.034m 2.80V 128.621m 2.90V 124.863m 3.627m -928.094m 66.00V 124.50V 117.80V 123.784m 0.764m 202.992m 196.138m 1.449m -17.428m 201.206m 190.210m 4.817m 0.20V 3.958m 3.204m -5.335m 200.774m 199.711m 70.146m -15.260m 71.138m 7.113m 4.639m 1.699m -811.245m 200.156m 200.000m 70.30V -4.232m 70.302m -17.876m 199.00V 32.306m 1.020m 69.766m -2.612m 195.818m 71.643m 71.692m -0.817m 1.275m 3.740m -0.70V 128.457m 71.00V 12.10V 129.083m 194.263m 2.304m 72.190m -0.40V 126.562m 6.1 A-28 Freescale Semiconductor .914m 202.10V 125. Rev.528m -6.708m 67.055m 69.661m 0.140m 72.535m -11.10V -1.10V 13.90V 129.472m 3.666m 198.313m -0.595m 6.983m 2.575m 1.710m 192.447m 2.40V 128.814u 2.458m 72.80V 10.856m 1.604m 910.486m 19.124m 1.411m 4.792m 12.391m 0.372m 8.208m 23.50V 128.647m 1.858m 0.305m 70.189m 21.986m 71.754m -6.90V 11.672m -6.50V 7.

651u 126.50V 201.20V 253.981u 196.544m 5.344u 171.087m -1.497m -1.478m 89.494u 264.794u 170.317u 264.368m 208.097m 92.415u -2.30V 960.70V 155.102u 238. 4.583m 10.362u 333.166m 76.40V 145.113u 336.418u 306.90V 135.255m 6.60V 132.30V 187.093m 202.361m 731.10V 145.640m 246.045m 4.316m 240.80V 159.400m 109.910u -2.706u 141.90V 337.763m 4.700u 1.880u 850.830u 217.333m 105.605u 247.50V 131.351u 296.324m 77.115u 178.70V 179.789u 114.907m 12.148m -0.004u 590.40V 194.778u 120.112m 269.669m 5.80V 133.513u 199.50V 597.722u -1.60V 151.277m 5.10V 276.00V 4.253u -2.1 Freescale Semiconductor A-29 .734m 98.230m 221.348m -1.619m 76.692u 184.149m 5.966m 4.00V 169.240u 389.705m 321.203m 4.065m 6.00V 152.524m 4.694m 225.304m 206.979u 100. 4.276m 4.579m 204.10V 138.941u -2.730u -1.825u 186.784m 73.224m 234.421u 365.906m 205.939m 75.90V 164.00V 303.836m 215.217m 81.912m 74.781m 101.300m 87.311m 203.000u -3.513u -2.644m 1.20V 1.419m 5.465m 278.10V 2.141u -2.80V 169.810u -1.070m 6.602m 6.211m 309.20V 129.993m 113.00V 136.060m 210.081u 512.20V 140.075u -3.60V 210.20V 138.40V 217.60V 190.393m 5.601u 697.10V 174. Rev.012u 2.118m 117.192m 83.155u 404.641u 462.877u -1.30V 130.208m 253.194m 5.906u 218.300u -2.316m 73.029m 260.702u -3.50V 203.597m 80.948m 218.340u 451.984u 105.70V 132.545m 85.810m 6.670m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.80V 378.30V 132.358m 73.174u 283.013m 4.177m 95.562u 133.712m -1.067u -1.060m 74.033u -1.803u -2.009m 298.090m 2.062m DSP56364 Technical Data.60V 501.90V 160.355m 229.934m 73.056m 5.110u -2.30V 142.40V 130.40V 737.70V 431.326u 150.319m 6.736u 160.308m 78.30V 234.878m 212.630m 5.723u -2.852u 232.20V 180.806m 6.787m 207.659m 5.50V 148.395u 567.748u 1.90V 8.237m 1.033m 4.559u 109.648u 206.096m 287.

943m -82.423m -78.10V -8.90V -141.344m 4.575m -206.20V -1.709m 0.387m 1.778m -0.490m -219.136m -79.233m -0.10V -987.399m 2.109m 3.261m -212.067m 3.098m 3.877m -211.082m 2.804m -190.250m -225.727m 11.928m -1.80V -6.417m DSP56364 Technical Data. -0.70V -134.30V -2.70V 7.60V -117.70V -5.954m -200.449m -83.013m -83.010m -70.30V -138.029m -0.622e-18 117.30V -9.586m 4.581m 2.311m -170.658m -10.40V 4.732m 3.277m -222.50V -4.416m -7.128m 8.462m -81.821m -0.10V -127.792m -79.363m 2.006m 4.996m -227.468m 2.255m 2.057m -78.539m -13.412m -5.756m -80.685m -2.10V -137.880m 3.50V -113.687e-18 58.052m -0.647m 1.103m -67.370m 1.40V -110.004m 3.10V -142.210m -218.50V -139.50V -132.910m -186.80V -140.270m -78.424m -5.866m -8.00V -7.443m -0.493m -226.311m -197.60V 6.20V -8.683m 2.937m 2.993m 3.617m -217.80V 8.964m -81.561m 1.585m -83.920m -218.994m -3.081m 1.269m -3.754m 9.20V -129.112m 4.709m 4.345m -80.90V -124.650m 3.20V 2.587m 0.807m -69.70V -119.611m -154.540m -202.40V -143.483m -79.599m -194.30V 3.40V -3.858m 4.704m 2.00V 58.814m 2.80V -122.864m 3.00V -141.261m 2.301m -12.441m 7.461m 1.447m -81.159m -83.1 A-30 Freescale Semiconductor .297m -73.346m 2.302m -216.032m 4.037m -208.00V -136.498m -77.079m 3.056m 2.828m -1.988m 0.50V -144.856u 1.644m -0.733m -75.50V 5.525m -223.761m -220.893m -181.408m -82. Rev.90V -135.20V -142.798m 1.890m -4.971m -215.306m -4.010m -224.40V -131.746m 5.470m -209.20V -137.860m -82.10V 1.713m -176.384m -76.604u -1.30V -143.499m -2.60V -5.118m 4.30V -130.907m -5.392m 0.300m 4.563m -13.410m -0.769m -223.783m -71.60V -139.302m 1.673m -4.504e-18 0.602m 0.300m -82.139m -75.053m 4.931m -6.00V -126.740m -226.516m 0.90V -7.908m -80.438m 1.131m -74.733m -83.999m -11.60V -133. 4.60V -144.859m -3.106u -655.128m 4.323m 1.381m 0.625m -213.552m 3.274m -2.339m -65.014m 678.195m -72.077m -204.280m -9.70V -140.022m -221.504m -77.033m 1.40V -138.80V -135.216m 0.

839m -93.411m -85.739n -411.10V -147.068 -2.406 -1.595m 6.20V -161.993m -232.828 -1.098n -15.124m 5.1 Freescale Semiconductor A-31 .969 -2.023m -259.60V -172.598 -941.465m 6.715m -377.20V -2.444m -96.223m 6.044u -0.073m -1.70V -799.483 -877.215m -0.614m -240.60V -687.426m 5.273m -255.00V -146.871m -84.157m -88.311m -563.897m -1.106m -268.551m -228.30V -163.514u -53.30V -1.90V -1.221m -363.943 -1.697 -2.521 -1.60V -151.071p -5.354m -257.368 -814.200m -230.182m -99.011m -94.451 -2.004 -1.926 -3. 4.50V -14.561 -2.155 -1.105 -2.583m -317.650m -0.195m -86.899m -84.357m -1.332p -0.138m -127.115m -87.70V -877.30V -37.535m -16.519m -1.20V -147.293m | [GND_clamp] | |Voltage I(typ) I(min) I(max) | -3.410n -29.378 -2.046m 5.833 -2.226m -4.40V -1.10V -158.613m -0.750m -1. 4.001m -85.789 -2.195 -2.70V -152.575m -231.026 -625.50V -150.713 -1.10V -1.30V -357.30V -148.314m -198.021 -1.041m 6.109m 6.242 -2.909u -271.907m -92.80V -912.60V -156.063 -3.847m -1.265m -228.368m 5.30V -2.351n -6.70V -1.699n -55.685m 6.904m -621.129m -491.90V -2.464m -233.404m 5.640u -3.377m -501.80V -145.137m 4.861m -229.086u -560.494m -142.481m 5.297m -753.514 -3.457m -45.305m -11.597m -235.425 -1.838u -397.90V -155.90V -19.160m -98.60V -1.339m -89.174 -1.149m -886.544m -1.20V -252.662u -0.80V -153.336m 5.387 -2.90V -145.80V -3.40V -166.995m -234.652m -85.924m 5.280m -237.678m -89.963m -263.103m -439.70V -144.40V -465.668n -598.50V -169.904m -1.254 -751.370m -84.601u -18.259 -2.80V -2.50V -1.288m -1.40V -780.20V -1.859m -1.395m -1.656m 5.038m -245.930m -241.132 -2.425m 6.294m -248.308n -0.10V -153.475m -1.054m -239.194m -90.059 -1.683p DSP56364 Technical Data.10V -2.921m -243.592m 5.701m -251. Rev.531m -102.379m -86.40V -149.10V -92.437n -0.515 -2.00V -156.50V -575.373m -0.879m 4.637 -1.667m -1.20V -1.

332p 3.50V -252.709p -1.404p -205.50V -1.385p 448.60V -7.10V -22.133p 1.50V -10.70V 26.149m -127.70V -4.30V 45.40V 17.928p 3.140 -877.956p 0.873p 39.483p 507.80V -575.20V 11.939p 3.801n 63.20V -1.40V -153.040p 2.754p 30.221m -1.862p 1.598p -810.769p 31.353p -683.601p 620.245p 18.003p 59.234p 0.20V 68.216p 2.044u 4.962f 0.583p 563.217p 4.437n 4.856p 47.60V 23.954p 1.80V 29.296p 44.071p -6.164p 26.125p 2.631m -257.896f -442.129m -4.802p -890.305m -15. 4.354m -439.675p 3.30V -16.904m -11.198p 327.601u -16.90V 2.40V 48. 0.247p -622.404p 1.489p 2.987p 23.785p 49.10V 8.291p 387.771p -16.30V 72.80V 59.712p 2.457m -198.838u -45.662u 4.226m -411.841p 90.00V -27.874p 0.750m -886.581p 2.516p 0.086u -13.583m -501.315p -264.717p 807.163p 3.20V 42.909u -18.10V -912.30V -27.103m -625.906n 61.666p -28.673p 619.30V 14.516p 3.70V -780.929p 149.156p 52.404p -2.939p 0.1 A-32 Freescale Semiconductor .765p -10.30V -1.163p 0.395m 4.874p 3.868p 55.227p 1.351n -3.614m -271.266n 65.050p -502.138m -18.40V -92.401p 2.668n -397.20V -19.468p 676.90V 33.288m -29.683p 3.647p 733.141p 20.60V -357.494m -317.852p 2.414p 28.709p -598.318p 0.699n -53.10V 39.90V -687.467p 12.60V 54.10V -3.799p -8.897m 5.579p -87.373m 4. Rev.562m 4.054p -13.70V -465.498p 1.314m -377.674p 1.613m 4.595p 0.667m 5.762p 2.357m -240.136p -383.098n -10.715m -563.859p 5.70V 57.475m -621.847m -363.310p 2.802p -5.492p -146.50V 20.20V -19.414p -318.80V -14.10V 65.468p -745.650m 4.80V -955.535m -142.026 -814.904m DSP56364 Technical Data.039p 1.297m -43.514u -16.147p -562.90V 61.346p 15.544m -753.311m -751.634p 10.50V 51.012p 41.585p 3.30V -69.90V -156.236p | [POWER_clamp] | |Voltage I(typ) I(min) I(max) | 3.212n -18.258p 57.018p 208.215m 4.949p 36.60V -37.859m 5.768p 1.40V -13.

474m -202.174 -1.004 -1.30V -480.80V -655.602p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipadex_i | "" Model_type Input Vinl = 0.483 -1.18/69.368 -1.290 5.451m -829.692m -1.259 -1.92p 2.057m -302.406 -1.20V -796.60V -2.924p 2.60V -1.99/104.561 5.60V | [GND_clamp] | |Voltage I(typ) I(min) I(max) | -3.04/123.40V -1.90V -340.78p 2.90V -1.027m -283.713 -1.515 6.126m -245.70V -620.528m -869.30V -2.299m -711.132 -1.021 5.290 -1.642 -2.335m -750.826m -189.652 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 1.062p 2.8 Vinh = 2 | variable typ min max C_comp 2.047m -264.534m -3.706 -2.242 6.657m DSP56364 Technical Data.569m -378.40V -2.85/215.496m -474.273m -170.895m -2.811m -2.657m -1.0 0.969 6.521 -1.10V -2.391m -359.501m -207.503m -1.697 6.789m -2.131m -321.20V -2.259m -318.402m -514.195 -1.819m -473.1 Freescale Semiconductor A-33 .30V 3. 5.665m -133.624m -435.810p 1.068 -1.279m -671.50V -550.150m -3.998m -357.637 -1.50V -2.828 -1.773m -397.80V -305.244m -340.528m -454.80V -1.286m -2.277m -632.167m -2.155 5.336m -553.60V -585.598 -1.451m -1.90V -690.507m -2. Rev.105 6.70V -1.10V -761.603p 1. 4.578 -2.255m -435.50V -202.059 -1.60V -236.40V -515.10V -410.20/73.073m -1.616m -909.425 5.643p | dV/dt_r 2.295m -592.00V 3.378 6.387 -1.582m -279.0 120.880m -2.50V -1.254 -941.981m -241.30V -831.81/183.20V -445.514 -2.871m -151.96p | variable typ min max [Temperature Range] 40.0 | variable typ min max [Voltage Range] 3.324m -2.451 -2.938m -2.70V -271.057m -1.

906p 289.781p 1.704p -955.10V -70.80V 7.909p 0.085f 1.996p 0.369p 12.711f 1.322p -652.50V -9.784p -375.144p 12.635p 4.783p 1.982p 842.307m -13.347p 2.976p -256.822p -0.607p 0.483p -2.10V 24.80V -5.862p -209.477p -320.911p 2.10V -14.163n 17.30V -32.314p -42.520p 0.70V 19.70V -6.585p 9.945p -730.520p 57.140m -78.212p 4.059p 676.60V -903.20V 13.014p -597.80V 20.856p 2.50V -18.126p | [POWER_clamp] | |Voltage I(typ) I(min) I(max) | 3.676p 67.583m -1.345p 0.990n -8.861m -126.609p 1.521p 1.40V -16.364p 10.946p 14. Rev.372n -9.30V 14.137p 510.562p 2.599p 233.50V 3.60V -32.674p 787.242n -13.160m -53.00V -15.10V -1.501u -0.824p 2.990n -13.159m -11.650m -2.909p 3.991m -1.30V -15.70V -36.799m -0.945p -867.873p -3.367p 732.984p 122.649p 2.372n -16.084p 3.165f -43.432p 0.064m -61.996p 3.428p -10.944n -256.30V -11.90V 22.754p 11.432p -7.025p 5.246p -98.151m -96.696p 1.70V -567.976p -38.301p 3.291p 178.998p 2.169p -264.084p 0.195p 8.852m -90.70V 6.30V 1.90V -14.630p -38.10V -16.60V -7.444p 565.40V 2.575p -2.475p 3.40V -567.415p -0.40V -10.823p -8.90V -3.694p 0.671n 19.171p 0.60V 5.767p -0.159m -768.263p -4.997n -0.535p 13.290p 898.431p -11.974p 9.810n -12.653p -5.50V -22.30V -135.227p -9.246p 3.752p 621.735p 15.466p 1.160m -12.076p 870.20V 61.707p -541.829p 455.736p 2.639u -3.014p -3.934u -10.434p 1.575p -13.097m -27.60V 18.043p -6.399p -486.20V 26.630p -713.1 A-34 Freescale Semiconductor .10V 11.092p -431.934u -172.088m -164.171p 3.30V 27.888p -0.173p 2.80V -1.20V -18.258p 3.886p -10.40V 15.834m -0.822p DSP56364 Technical Data.20V -13.508f 1.085p 2.975u -10.975u -10.014p -730.258p 0.415p 6. -1.589n -0.50V 17.213p 3.40V -168.019n 18.181m -1.905p 1.90V 9. 4.214p 344.160m -54.242n -13.80V -22.20V -102.722m -115.

3.90V -903.944n -27.650m -13.767p
4.10V -1.307m -61.160m -172.415p
4.20V -14.097m -78.852m -10.997n
4.30V -39.803m -96.861m -768.589n
4.40V -70.064m -115.088m -53.501u
4.50V -102.140m -133.474m -2.799m
4.60V -135.151m -151.981m -22.990m
4.70V -168.722m -170.582m -54.834m
4.80V -202.665m -189.259m -90.181m
4.90V -236.871m -207.998m -126.991m
5.10V -305.826m -245.624m -202.657m
5.20V -340.501m -264.496m -241.057m
5.30V -375.273m -283.402m -279.692m
5.40V -410.126m -302.336m -318.503m
5.50V -445.047m -321.295m -357.451m
5.60V -480.027m -340.277m -396.509m
5.70V -515.057m -359.279m -435.657m
5.80V -550.131m -378.299m -474.880m
5.90V -585.244m -397.335m -514.167m
6.10V -655.569m -435.451m -592.895m
6.20V -690.773m -454.528m -632.324m
6.30V -726.003m -473.616m -671.789m
6.40V -761.255m -492.715m -711.286m
6.50V -796.528m -511.823m -750.811m
6.60V -831.819m -530.941m -790.363m
|
|End model
[Model] ipadm_3st | ""
Model_type 3-state
| variable typ min max
C_comp 1.99p 1.86p 2.15p
| variable typ min max
[Temperature Range] 40.0 0.0 120.0
| variable typ min max
[Voltage Range] 3.30V 3.00V 3.60V
|
[Pulldown]
| pulldown in the table = pulldown subtract gnd_clamp
|Voltage I(typ) I(min) I(max)
|
-3.30V -157.134u -99.256u -219.000u
-3.20V -165.037u -104.127u -230.250u
-3.10V -173.749u -109.479u -242.685u
-3.00V -183.400u -115.386u -256.500u
-2.90V -194.148u -121.936u -271.934u
-2.80V -206.189u -129.240u -289.286u
-2.70V -219.766u -137.431u -308.933u
-2.60V -235.190u -146.680u -331.355u
-2.50V -252.856u -157.199u -357.176u
-2.40V -273.283u -169.265u -387.219u
-2.30V -297.162u -183.236u -422.595u
-2.20V -325.427u -199.590u -464.837u
-2.10V -359.384u -218.976u -516.117u
-2.00V -400.901u -242.299u -579.623u
-1.90V -452.750u -270.851u -660.217u

DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor A-35

-1.80V -519.217u -306.549u -765.681u
-1.70V -607.277u -352.346u -909.270u
-1.60V -729.045u -413.024u -1.115m
-1.50V -907.407u -496.811u -1.434m
-1.40V -1.191m -619.011u -1.987m
-1.30V -1.699m -811.079u -3.133m
-1.20V -2.799m -1.146m -6.243m
-1.10V -5.689m -1.822m -12.974m
-1.00V -10.416m -3.302m -17.948m
-0.90V -12.342m -5.449m -17.964m
-0.80V -11.672m -6.479m -16.692m
-0.70V -10.528m -6.146m -15.152m
-0.60V -9.204m -5.387m -13.338m
-0.50V -7.770m -4.535m -11.313m
-0.40V -6.286m -3.652m -9.190m
-0.30V -4.766m -2.754m -6.999m
-0.20V -3.214m -1.846m -4.740m
-0.10V -1.627m -928.990u -2.410m
0.00V 32.755e-18 18.548e-18 -1.607f
0.10V 1.604m 910.814u 2.391m
0.20V 3.124m 1.775m 4.661m
0.30V 4.566m 2.595m 6.817m
0.40V 5.928m 3.372m 8.858m
0.50V 7.210m 4.105m 10.784m
0.60V 8.411m 4.792m 12.593m
0.70V 9.529m 5.432m 14.284m
0.80V 10.562m 6.023m 15.855m
0.90V 11.508m 6.563m 17.306m
1.00V 12.367m 7.051m 18.639m
1.10V 13.138m 7.486m 19.856m
1.20V 13.821m 7.865m 20.957m
1.30V 14.417m 8.189m 21.944m
1.40V 14.930m 47.725m 22.817m
1.50V 86.564m 48.943m 23.575m
1.60V 88.497m 49.908m 136.139m
1.70V 89.946m 50.637m 138.902m
1.80V 90.974m 51.160m 140.954m
1.90V 91.689m 51.534m 142.415m
2.00V 92.200m 51.810m 143.449m
2.10V 92.586m 52.024m 144.201m
2.20V 92.895m 52.201m 144.779m
2.30V 93.154m 52.351m 145.246m
2.40V 93.380m 52.482m 145.642m
2.50V 93.581m 52.600m 145.990m
2.60V 93.764m 52.706m 146.303m
2.70V 93.931m 52.804m 146.590m
2.80V 94.087m 52.895m 146.855m
2.90V 94.233m 52.980m 147.104m
3.00V 94.370m 53.060m 147.338m
3.10V 94.500m 53.135m 147.560m
3.20V 94.624m 53.207m 147.772m
3.30V 94.744m 53.276m 147.976m
3.40V 94.859m 53.343m 148.174m
3.50V 94.974m 53.408m 148.367m
3.60V 95.089m 53.475m 148.560m

DSP56364 Technical Data, Rev. 4.1
A-36 Freescale Semiconductor

3.70V 95.208m 53.543m 148.757m
3.80V 95.336m 53.617m 148.963m
3.90V 95.478m 53.699m 149.186m
4.00V 95.641m 53.792m 149.436m
4.10V 95.833m 53.902m 149.725m
4.20V 96.065m 54.035m 150.067m
4.30V 96.347m 54.196m 150.479m
4.40V 96.693m 54.394m 150.981m
4.50V 97.117m 54.635m 151.594m
4.60V 97.636m 54.930m 152.342m
4.70V 98.266m 55.287m 153.252m
4.80V 99.024m 55.716m 154.350m
4.90V 99.931m 56.227m 155.666m
5.00V 101.005m 56.831m 157.230m
5.10V 102.264m 57.539m 159.070m
5.20V 103.730m 58.361m 161.218m
5.30V 105.422m 59.308m 163.704m
5.40V 107.357m 60.391m 166.555m
5.50V 109.556m 61.618m 169.801m
5.60V 112.034m 63.000m 173.468m
5.70V 114.809m 64.545m 177.581m
5.80V 117.897m 66.263m 182.163m
5.90V 121.311m 68.160m 187.235m
6.00V 125.066m 70.245m 192.816m
6.10V 129.172m 72.524m 198.924m
6.20V 133.642m 75.002m 205.573m
6.30V 138.485m 77.685m 212.776m
6.40V 143.709m 80.578m 220.544m
6.50V 149.320m 83.683m 228.885m
6.60V 155.326m 87.004m 237.805m
|
[Pullup]
| pullup in the table = pullup subtract power_clamp
|Voltage I(typ) I(min) I(max)
|
-3.30V 132.979u 100.794u 170.075u
-3.20V 138.984u 105.115u 178.000u
-3.10V 145.559u 109.825u 186.702u
-3.00V 152.789u 114.981u 196.300u
-2.90V 160.778u 120.648u 206.941u
-2.80V 169.651u 126.906u 218.803u
-2.70V 179.562u 133.852u 232.110u
-2.60V 190.706u 141.605u 247.141u
-2.50V 203.326u 150.317u 264.253u
-2.40V 217.736u 160.174u 283.910u
-2.30V 234.344u 171.418u 306.723u
-2.20V 253.692u 184.362u 333.513u
-2.10V 276.513u 199.421u 365.415u
-2.00V 303.830u 217.155u 404.033u
-1.90V 337.102u 238.340u 451.722u
-1.80V 378.494u 264.081u 512.067u
-1.70V 431.351u 296.004u 590.810u
-1.60V 501.113u 336.601u 697.730u
-1.50V 597.240u 389.880u 850.877u
-1.40V 737.641u 462.700u 1.087m

DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor A-37

443m -0.750m -59.424m -146.931m -6.30V -100.10V -8.781m 2.052m -0.563m -13.472m -52.10V -92. Rev.30V -94.709m 2.583m 10.766m -161.60V -84.907m -5.081m 1.237m 1.602m 0.999m -11.644m 4.014m 2.90V 8.10V 2.943m 2.272m 3.274m -2.770m -58.424m -5.033m 1.735m -59.412m -5.809m -57.640m 1.687e-18 58.363m 2.713m -51.014m 678.118m 4.20V -99.60V -101.10V -987.029m -0.939m 1.531m 3.533m -142.709m 0.846m -57.30V 3.655m 2.40V -100.00V -98.907m 12.392m 0.999m -145.746m 5.348m -1.998m -58.859m -3.519m 1.499m -2.80V 8.461m 1.40V 4.50V -95.084m -59.396u 567.724m -52.942m -162.327m -54.401m -160.982m 2.727m 11.361m 731.152m -156.70V -5.824m -152.489m -54.343m -57.622e-18 117.837m 1.269m -3.109m 3.086m 4.00V -91.561m 1.280m -9.914m 3.198m -58.828m -1.749m 3.381m 0.40V -79.302m 1.30V -2.510m 3.650m 3.128m 4.00V 4.977m 3.233m -0.70V 7.216m 0.20V 2.106u -655.40V -95.604u -1.301m -12.415m -55.20V -93.812m -158.673m -4.398m -154.50V -100.20V -1.422m -59.451m -13.90V -98.996m -53.60V 6.082m 2.381m -157.062m -0.920m 3.30V 960.017m -140.90V -102.90V -89.856u 1.00V -7.988m 0.211m -159.607m -58.391m -50.1 A-38 Freescale Semiconductor .70V -86.070m -59.987m 2.148m -0.187m -123.587m 0.10V 1.748u 1.057m -131.333m 2.00V -102.032m 4.10V -103.80V -97.410m -0.40V -3.053m 4.441m 7.794m -134.203m -127.174m -149.088m 2.585m -161.504e-18 0.224m -55.320m -57.955m -56.890m -4.90V -7.119m -153.510m -150.814m -148.128m 8.601m -157.015m -159.913m -155.70V -101.754m 9.012u 2.324m 1.20V 1.994m -3.238m -56.30V -9.497m -1.063m 2.50V -82.954m -118.866m -8.50V -4.70V -97.821m -0.928m -1.10V -99.339m -47.623m -56.712m -1.644m 1.306m -4.056m 2.295m 3.644m -0.516m 0. 4.80V -102.511m -54.60V -96.705m -48.442m -137.013m 4.00V 58.80V -6.658m -10.501m 1.778m -0.036m 3.685m -2.60V -5.80V -88. -1.416m -7.186m DSP56364 Technical Data.20V -8.662m -154.090m 2.374m -59.50V 5.

221m -313.032 -618.40V -120.786 -1.492m -173.867m -1.334m 5.494m -618.597 -929.483m -63.10V -1.002m -60.991m 5.50V -1.582m -200.050m -61.314 -773.331u -3.070 -1.174m -1.388 -3.20V -116.126m -174.311m | [GND_clamp] | |Voltage I(typ) I(min) I(max) | -3.803m -0.387 -2.30V -103.831m 4.052m -727.80V -2.199m 6.80V -111.242 -2.831 -2.234m -165.70V -110.190 -2.40V -104.647m -164.949m -62.384m -60.40V -108.668m -120.329m -70.747m 4.965m 5.003m -169.401m -65.935m -194.384m -190.90V -17.597m -405.278m -168.029m -8.560m -179.955m -61.694m -60.771m -515.770m 4.375m -40.60V -104.514m -1.981m -187.610m -1.313m -60.730m -63.629m -60.220m -1.942 -2.975m -167.10V -115.659m -61.20V -103.30V -298.503 -877.1 Freescale Semiconductor A-39 .578m -182.932m -172.640m -66.410m -414.90V -1.928m 5.394m 5.459m -166.40V -1.691 -981.978m 6.892m -836.958m -945.248m -214.60V -109.785m 6.301m -511.579m -300.138 -2.80V -105.704m -166.027m -165.239m 5.90V -845.365m -69.975 -1.257m 4.793m 6.330m -1.00V -106.50V -108.439m -170.70V -656.715m 4.403m -1.619m -169.293m 4.20V -212.247m 6.00V -113. Rev.980m -263.028m -166.720 -2.521u -336.60V -568.165 -1.296m -61.908m -1.277 -2. 4.30V -118.606m -68.185m -1.50V -122.106m 5.40V -386.90V -112.60V -116.70V -104.195m -0.498 -2.50V -104.054 -2.20V -2.779m -1.634m 5.276 -2.500 -3.187m -1.117m -162.986m 6.248m -107.20V -106.467m -163.715m -184.373m -1.305m -65.30V -2.70V -1.291m -163.337m -64.609 -2. 4.970m -1.408 -825.126 -670.014m -1.30V -107.451m -0.220 -721.887m -464.430m -1.80V -1.626m 6.636u DSP56364 Technical Data.90V -105.651m -177.513m -72.837m -14.30V -1.843m -176.50V -477.627m 5.20V -1.477m -61.474m -62.140m -1.60V -1.033 -2.70V -660.234m 4.036m -67.461m -363.935m -73.496m -0.064m -63.80V -752.166 -1.10V -1.012m 5.10V -106.60V -124.317u -201.149m -1.886m -3.10V -130.832m -164.

039p 22.837m -120.319p 3.269n -41.963p -578.597m -3.40V -13.051n -4.60V -298.365p -4.682p 44.60V 46.307p 0.611p 2.868p 23.567p -14.70V 22.90V 53.70V 49.278p -754.300p 2.70V -386.60V -27.817p 153.618p 2.158p -0.30V 11.80V 24.80V 51.994n -336.195m 4.446p -464.301m -8.026p 39.980m -414.484n -0.650p 46.133p 7.083p 30.353p 1.375m -166.980f 0.079f -351.70V -5.20V -17.50V -10.966p 3.985p 1.595p -2.581p 436.30V 62.30V 38.183p 44.966p 0.092p 0.867p 37.849p 600.078n -18.315p 776.964u -13.10V -2.496m DSP56364 Technical Data.10V -74.668m -263.493p 18.327p 1.052m -107.279p 2.632u -13.654p 20.30V -27.552n 52.463p -4.218n -27.316p -182. -0.70V -580.420m 4.317u -18.737p 0.958p 2.50V 16.20V -19.215p -1.356p 654.20V 35.948p 2.437p -6.862n -311.732n 55.629p 2.339p 492.011p 1.888m -214.20V -1.028m -313.051n -3.248m -13.772p 3.799n -0.886m -311. 4.522n 54.484n 4.743p 13.288p 2.494m -37.90V 62.463p -4.303p 3.340p 1.122p 48.632p 0.80V -10.50V -10.50V -212.60V -8.90V 27.521u -40.40V -130.50V -1.579m -1.420u 4.861p | [POWER_clamp] | |Voltage I(typ) I(min) I(max) | 3.193p 4.50V 44.269n -41.642p 2.789u -41.975p 9.029m -11.20V 8.656p 1.632p 3.146p -13.80V -2.695p 41.998p 1.303p 0.313p 1.067p 97.636p 2.067p -126.497p -694.939p 3.005n -11.737p 3.30V -26.10V 57.10V 33.959p 466.159p 25.817p -70.60V 19.691p -408.568p 210.964u -16.014m -27.378p 709.00V -26.248m -363.203p -521.40V 13.789p 32.1 A-40 Freescale Semiconductor .092p 3.637p 0.953p -9.650p 34.789u -14.40V 41.634p 16.669p 1.098p 547.325p -16.215p -450.005n -11.30V -16.582m -201. Rev.114p -826.726p -635.566p -239.968p 0.40V -580.636u 4.40V -74.90V -116.188p -11.851p 11.451m 4.803m 4.825p 379.420u -0.994n -450.10V -22.072p 323.10V 5.632u -416.20V 59.158p 3.317p 41.30V -60.300p 0.

286u -2.81/206.934u -2.431u -308.40V -1.054 6.8 Vinh = 2 | variable typ min max C_comp 2.10V -752.384p 2.975 -1.20V -1.265u -387.786 -1.720 6.165 -1.00V 3.853p 2.90V -1.687p | dV/dt_r 2.908m 5.867m 5.50V -252.199u -357.220 -877.503 -1.236u -422.373m 5.50V -2.1 Freescale Semiconductor A-41 .70V -1.283u -169. Rev.185m -1.219u -2.10V -173.0 | variable typ min max [Voltage Range] 3.856u -157.314 -929.766u -137.90p 2.30V -157.595u -2.30V -297.162u -183.609 6.461m -515.346 -2.174m -1.427u -199.80V -477.590u -464.250u -3.176u -2.881 -1.942 6.056 5.20V -845.138 -1.50V -1.691 -1.680u -331.403m 5.240u -289.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.400u -115.610m -511.430m 5.933u -2.685u -3.90V -194.187m 4.19/93.979m -721.831 6.80V -1. 4.892m -200.189u -129.032 -773.60V -1.220m -1.276 5.000u -3.030p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipadn_io | "" Model_type I/O Vinl = 0.70V -219.0 120.970m 5.749u -109.514m -836.60V -235.500u -2.256u -219.958m -300.148u -121.140m -618.037u -104.00V -183.033 -1.126 -825.399 -2.99/116. 4.478p 1.771m -670.134u -99.30V -1.84/253.0 0.330m -945.355u -2.18p | variable typ min max [Temperature Range] 40.02/147.17/80.20V -325.165 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 1.479u -242.242 -1.887m -618.30V -938.40V -273.070 -1.190u -146.166 5.127u -230.221m -464.936u -271.387 6.40V -1.294 -1.90V -568.03p 1.408 -981.837u DSP56364 Technical Data.10V -1.190 -1.30V 3.80V -206.386u -256.20V -165.60V -2.779m -727.722p 1.

243m -1.417m 8.407u -496.775m 4.895m 146.024u -1.346u -909.30V 94.60V 88.152m -0.20V 94.30V 4.10V 13.10V -1.190m -0.980m 147.146m -6.804m 146.160m 140.434m -1.189m 21.699m -811.20V -2.987m -1.40V -6.479m -16.560m 3.784m 0.138m 7.351m 145.595m 6.581m 52.908m 136.60V -729.60V -9.133m -1.70V -10.10V 94.901u -242.814u 2.00V 12.964m -0.851u -660.00V -10.90V -12.755e-18 18.70V -607.217u -306.00V -400.415m 2.306m 1.104m 3.990m 2.764m 52.590m 2.146m -15.50V 93.410m 0.207m 147.70V 89.661m 0.624m 53.286m -3.821m 7.50V 7.549u -765.766m -2.50V -7.976m DSP56364 Technical Data.105m 10.928m 3.529m 5.623u -1.30V -1.011u -1.246m 2.750u -270.563m 17.689m -1.217u -1.10V -5.607f 0.990u -2.367m 7.902m 1.338m -0.562m 6.277u -352.045u -413.233m 52.575m 1.586m 52.051m 18.90V -452.706m 146.90V 91.10V 1.792m 12.90V 11.30V 14.284m 0.779m 2.855m 0.387m -13.865m 20.024m 144.486m 19.895m 52.50V -907.817m 1.20V 13.689m 51.954m 1.214m -1.30V -4.817m 0.856m 1.948m -0.600m 145.535m -11.20V 92.079u -3.338m 3.770m -4.80V -519.772m 3.642m 2.999m -0.30V 93.564m 48.10V -359.744m 53.846m -4.855m 2. -2.508m 6.276m 147.135m 147.201m 144.976u -516.637m 138.974m -1.204m -5.497m 49.70V 93.681u -1.799m -1.1 A-42 Freescale Semiconductor .80V 10.060m 147.930m 47.593m 0.200m 51.80V 90.411m 4.201m 2.811u -1.432m 14.528m -6.00V 94.548e-18 -1.534m 142. 4.303m 2.313m -0.740m -0.822m -12.725m 22.449m -17.342m -5.500m 53.449m 2.416m -3.20V -3.810m 143.023m 15.974m 51.210m 4.946m 50.40V 14.566m 2.302m -17.154m 52.40V 93.639m 1. Rev.299u -579.391m 0.00V 92.372m 8.370m 53.124m 1.70V 9.90V 94.00V 32.60V 93.931m 52.10V 92.191m -619.754m -6.139m 1.20V 3.117u -2.384u -218.115m -1.80V 94.40V -1.604m 910.957m 1.692m -0.944m 1.482m 145.652m -9.50V 86.270u -1.380m 52.80V -11.672m -6.858m 0.087m 52.943m 23.40V 5.627m -928.60V 8.

60V 155.20V 96.00V 95.300u -2.245m 192.725m 4.90V 337.350m 4.30V 105.357m 60.320m 83.722u -1.034m 63.709m 80.50V 109.555m 5.422m 59.252m 4.543m 148. 3.699m 149.70V 98.810u DSP56364 Technical Data.803u -2. 4.70V 431.778u 120. Rev.90V 99.90V 121.60V 112.343m 148.308m 163.651u 126.683m 228.418u 306.367m 3.902m 149.024m 55.706u 141.115u 178.833m 53.070m 5.421u 365.897m 66.685m 212.00V 303.005m 56.692u 184.174m 3.253u -2.347m 54.10V 102.264m 57.60V 95.066m 70.362u 333.573m 6.979u 100.635m 151.581m 5.436m 4.723u -2.641m 53.174u 283.825u 186.704m 5.1 Freescale Semiconductor A-43 .485m 77.30V 132.10V 276.560m 3.004m 237.494u 264.648u 206.885m 6.30V 138.757m 3.266m 55.230m 5.539m 159.559u 109.556m 61.394m 150.20V 103.351u 296.513u 199.110u -2.544m 6.344u 171.227m 155.605u 247.40V 94.218m 5.70V 179.30V 234.852u 232.067u -1.361m 161.00V 125.20V 138.910u -2.794u 170.415u -2.816m 6.326m 87.70V 95.00V 101.035m 150.065m 54.102u 238.809m 64.524m 198.545m 177.326u 150.594m 4.60V 97.10V 129.475m 148.513u -2.984u 105.033u -1.067m 4.50V 149.730m 58.963m 3.117m 54.30V 96.50V 97.317u 264.40V 143.70V 114.478m 53.789u 114.702u -3.801m 5.562u 133.263m 182.693m 54.000m 173.666m 5.642m 75.342m 4.90V 160.40V 107.80V 99.311m 68.20V 253.60V 190.776m 6.391m 166.974m 53.924m 6.163m 5.981m 4.930m 152.141u -2.004u 590.160m 187.792m 149.80V 95.196m 150.90V 95.859m 53.287m 153.336m 53.186m 4.831m 157.081u 512.002m 205.075u -3.805m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.155u 404.617m 148.636m 54.40V 96.479m 4.00V 152.981u 196.80V 378.50V 94.000u -3.089m 53.830u 217.235m 6.906u 218.10V 95.20V 133.941u -2.340u 451.80V 169.208m 53.40V 217.716m 154.172m 72.931m 56.50V 203.468m 5.408m 148.618m 169.736u 160.578m 220.80V 117.10V 145.

90V -89.60V 6.828m -1.812m -158.735m -59.118m 4.441m 7.084m -59.424m -146.607m -58.60V 501.778m -0.939m 1.70V -5.50V -100.374m -59.50V -95.709m 2.174m -149.60V -101.846m -57.998m -58.057m -131.644m -0.856u 1.415m -55.237m 1.727m 11.187m -123.673m -4.198m -58.40V -95.90V 8.20V -99.015m -159.60V -96.713m -51.00V 58. -1.216m 0.510m -150.928m -1.032m 4.531m 3.017m -140.10V 2.062m -0.00V -98.604u -1.60V -5.601m -157.274m -2.20V -8.461m 1.00V 4.30V -94.587m 0.211m -159.361m 731.563m -13.272m 3.655m 2.443m -0.109m 3.052m -0.50V 5.650m 3.451m -13.348m -1.442m -137.10V -99.687e-18 58.081m 1.999m -11.320m -57.090m 2.128m 8.662m -154.152m -156.10V -92.877u -1.10V -987.866m -8.749m 3.754m 9.712m -1.269m -3.901m 1.996m -53.814m -148.381m -157.709m 0.203m -127.644m 1.20V 2.907m 12.280m -9.489m -54.029m -0.50V -82.301m -12.053m 4. Rev.80V -97.954m -118.982m 2.033m 1.70V -97.499m -2.014m 678.623m -56.70V -86.519m 1.128m 4.1 A-44 Freescale Semiconductor .240u 389.381m 0.306m -4.794m -134.561m 1.685m -2.60V -84.401m -160.056m 2.622e-18 117.424m -5.10V 1.914m 3.20V -93.295m 3.063m 2.724m -52.994m -3.339m -47.705m -48.00V -91.730u -1.396u 567.343m -57.324m 1.30V 3.907m -5.238m -56.416m -7.890m -4.955m -56.392m 0.224m -55.70V -101.880u 850.80V 8.327m -54.40V 4.501m 1.658m -10.50V -4.20V 1.987m 2.50V 597.30V 960.333m 2.913m -155.824m -152.90V -98.641u 462.640m 1.036m 3.40V -100.148m -0.088m 2.821m -0.80V -88.700u 1.013m 4.012u 2.40V -3.363m 2.40V 737.80V -6.410m -0.014m 2.70V 7.533m -142.583m 10.10V -8.510m DSP56364 Technical Data.106u -655.087m -1.233m -0.931m -6.943m 2. 4.30V -9.302m 1.809m -57.30V -100.516m 0.113u 336.00V -7.748u 1.20V -1.746m 5.082m 2.497m -1.412m -5.119m -153.770m -58.602m 0.781m 2.920m 3.504e-18 0.80V -102.472m -52.391m -50.90V -7.511m -54.398m -154.601u 697.40V -79.30V -2.988m 0.999m -145.859m -3.977m 3.

20V -106.403m -1.981m -187.20V -2.975 -1.20V -1.492m -173.30V -103.50V -108.296m -61.955m -61.786 -1.247m 6.40V -104.80V -111.832m -164.408 -825.029m -8.117m -162.330m -1.793m 6.10V -106. 4.070 -1.459m -166.50V -1.126m -174.90V -845.691 -981.278m -168.064m -63.585m -161.644m 4.467m -163.311m | [GND_clamp] | |Voltage I(typ) I(min) I(max) | -3.80V -105.165 -1.054 -2.991m 5.90V -102.730m -63.002m -60.627m 5.00V -102.461m -363.234m 4.149m -1.496m -0.313m -60.928m 5.174m -1.221m -313. 3.387 -2.239m 5.704m -166.20V -212.234m -165.582m -200.579m -300.609 -2.474m -62.1 Freescale Semiconductor A-45 .887m -464.935m -194.80V -752.30V -118.388 -3.70V -660.513m -72.410m -414.867m -1.248m -214.036m -67.659m -61.60V -124.80V -1.606m -68.50V -122.942m -162.032 -618.785m 6.20V -116.166 -1.770m 4.10V -130.500 -3.40V -386.50V -104.401m -65.640m -66.248m -107.908m -1.40V -120.720 -2.301m -511.747m 4.257m 4.199m 6.970m -1.626m 6.70V -104.560m -179.715m 4.90V -105.140m -1.958m -945.629m -60.070m -59.498 -2.10V -115.329m -70.610m -1.986m 6.277 -2.375m -40.503 -877.384m -60.60V -1.766m -161.126 -670. Rev.052m -727.978m 6.30V -298.831m 4.186m 4.10V -1.980m -263.439m -170.00V -113.10V -103.715m -184.305m -65.949m -62.242 -2.892m -836.012m 5.30V -107.373m -1.843m -176.293m 4.00V -106.314 -773.514m -1.337m -64.60V -109.668m -120.220 -721.027m -165.935m -73.430m -1.394m 5.20V -103.779m -1.771m -515.90V -1.750m -59.477m -61.220m -1.50V -477.70V -110.597m -405.578m -182.050m -61.106m 5.086m 4.384m -190.291m -163.003m -169.30V -1.942 -2.634m 5.276 -2.651m -177.028m -166.422m -59.185m -1.10V -1.30V -2.365m -69.033 -2.694m -60.619m -169.60V -104.90V -17.803m DSP56364 Technical Data.187m -1.965m 5.597 -929.138 -2.334m 5.932m -172.60V -568.40V -108.483m -63.90V -112.70V -1.647m -164.40V -1.190 -2.831 -2.494m -618.975m -167.

90V 62.632p 3.039p 22.420u -0.567p -14.618p 2.317u -201.484n 4.098p 547.650p 34.682p 44.862n -311.632u -416.861p | [POWER_clamp] | |Voltage I(typ) I(min) I(max) | 3.092p 3.30V -27.279p 2.451m -0.732n 55.248m -13.300p 0.188p -11.327p 1.737p 0.40V -74.50V -10.1 A-46 Freescale Semiconductor .20V 35.10V 57.420u 4.356p 654.10V -2.80V -2.331u -3.70V 22.868p 23.70V -5.092p 0.522n 54.446p -464.595p -2.566p -239.80V 24.20V -17.203p -521.737p 3.40V -130. 4.650p 46.014m -1.215p -450.90V -116.50V -1.193p 4.998p 1.353p 1.581p 436.888m -214.315p 776.636u 4.303p 0.158p -0.313p 1.029m -11. -0.656p 1.636u -0.269n -41.278p -754.437p -6.966p 0.484n -0.632u -13.743p 13.579m -1.50V -10.825p 379.953p -9.964u -16.959p 466.218n -27.634p 16.80V 51.968p 0.316p -182.300p 2.948p 2.963p -578.083p 30.691p -408.597m -3.70V 49.632p 0.50V 44.10V -74.90V 27.365p -4.072p 323.789u -41.195m 4.789u -14.497p -694.10V 5.654p 20.067p 97.30V -16.40V 13.886m -3.378p 709.985p 1.939p 3.70V -580.817p -70.636p 2.20V -1.817p 153.851p 11.50V 16.837m -14.837m -120.964u -13.867p 37.307p 0.133p 7.146p -13.051n -3.994n -450.980f 0.669p 1.30V -26.726p -635.114p -826.695p 41.975p 9.158p 3.582m -201.521u -40. Rev.339p 492.493p 18.463p -4.026p 39.789p 32.451m DSP56364 Technical Data.611p 2.00V -26.159p 25.288p 2.40V 41.317p 41.70V -656.568p 210.637p 0.886m -311.668m -263.20V 8.303p 3.375m -166.521u -336.90V 53.40V -13.269n -41.20V 59.317u -18.067p -126.011p 1.122p 48.215p -1.325p -16.195m -0.552n 52.958p 2.183p 44.014m -27.629p 2.849p 600.772p 3.340p 1.078n -18.319p 3.30V -60.60V -8.994n -336.30V 62.005n -11.051n -4.966p 3.463p -4.60V -116.60V 19.60V 46.642p 2.30V 38.60V -27.80V -2.30V 11.079f -351.799n -0.80V -10.20V -19.10V 33.40V -580.005n -11.10V -22.

314 -929.89p 2.609 6.851p 2.60V -235.766u -137.174m -1.908m 5.033 -1.17/74.148u -121.514m -836.496m 4.503 -1.771m -670.610m -511.50V -212.881 -1.356p | dV/dt_r 2.20V -1.126 -825.831 6.420m 4.60V -1.786 -1.070 -1.70V -1.403m 5.165 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 2.70V -386.250u -3.185m -1.165 -1.60V -2.892m -200.127u -230.30V 3.199u -357.779m -727.872p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipadni_io | "" Model_type I/O Vinl = 0.20/93.138 -1.187m 4.054 6.10V -173.028m -313.867m 5.40V -1.80V -1.387 6. Rev.399 -2.0 120.220 -877.330m -945.037u -104.01p 1.50V -1.056 5.80V -477.134u -99.556p 1.933u -2.430m 5.90V -568.30V -157.30V -938.00V 3.479u -242.000u -3.720 6.286u -2.50V -252.248m -363.17p | variable typ min max [Temperature Range] 40.749u -109.82/199.40V -1.400u -115.190u -146.970m 5. 4.958m -300.355u -2.20V -165.1 Freescale Semiconductor A-47 .80V -206.294 -1.301m -8.00/112.245p 1.942 6.10V -752.856u -157.386u -256.975 -1.0 | variable typ min max [Voltage Range] 3.803m 4.190 -1.166 5.242 -1.20V -845.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.032 -773.50V -2.221m -464.431u -308.00V -183.685u -3.176u DSP56364 Technical Data.70V -219.934u -2.346 -2.936u -271.680u -331.30V -1.240u -289.373m 5.84/252.189u -129.500u -2.90V -1. 4.02/146.10V -1.408 -981.220m -1.276 5.461m -515.691 -1.887m -618.8 Vinh = 2 | variable typ min max C_comp 2.052m -107.980m -414.494m -37.140m -618.0 0.90V -194.256u -219.979m -721.60V -298.937p 2.

817m 0. Rev.990m 2.277u -352.681u -1.265u -387.204m -5.40V 14.948m -0.692m -0.766m -2.087m 52.70V 93.851u -660.706m 146.754m -6.775m 4.415m 2.70V 89.672m -6.10V 1.90V -452.10V -359.384u -218.70V -10.00V 12.023m 15.623u -1.810m 143.974m -1.814u 2.822m -12.191m -619.10V 92.299u -579.20V 92.124m 1.236u -422.286m -3.627m -928.60V -9.548e-18 -1.90V 94.1 A-48 Freescale Semiconductor .372m 8.162u -183.575m 1.895m 52.566m 2.549u -765.024m 144.20V 3.846m -4.855m 0.590m 2.152m -0.80V -519.60V 93.595m 6.90V -12.00V 94.595u -2.764m 52.10V 13.133m -1.821m 7.214m -1.725m 22.865m 20.479m -16.689m -1.160m 140.661m 0.391m 0.410m 0.117u -2.051m 18.858m 0.931m 52.432m 14.346u -909.342m -5.217u -306.60V 8.80V -11.895m 146.90V 91.427u -199.201m 2.581m 52.928m 3.689m 51.40V 5.70V -607.417m 8.817m 1.20V -3.642m 2.90V 11.990u -2.902m 1.770m -4.799m -1.243m -1.00V -400.011u -1.40V 93.535m -11.784m 0.380m 52.00V 32.482m 145.217u -1.954m 1.944m 1.146m -6.233m 52.105m 10.20V -2.50V -907.154m 52.30V -297.755e-18 18.600m 145.80V 94.70V 9.50V -7.908m 136.219u -2.338m -0.699m -811.590u -464.00V -10.189m 21.974m 51.351m 145.564m 48.303m 2.115m -1.607f 0.387m -13.586m 52.434m -1.146m -15.856m 1.637m 138.20V 13.964m -0.40V -6.980m 147.104m 3.528m -6.562m 6.901u -242. -2.079u -3.139m 1.497m 49.593m 0.210m 4.976u -516.40V -273.270u -1.943m 23.930m 47.837u -2.855m 2.563m 17.00V 92.045u -413.449m 2.50V 7.80V 10.80V 90.604m 910.407u -496.529m 5.50V 93.20V -325.10V -1.284m 0.200m 51. 4.60V -729.804m 146.024u -1.999m -0.508m 6.60V 88.946m 50.367m 7.30V 93.779m 2.30V 4.338m DSP56364 Technical Data.416m -3.811u -1.302m -17.987m -1.40V -1.370m 53.534m 142.740m -0.411m 4.30V -1.138m 7.639m 1.283u -169.30V 14.060m 147.30V -4.750u -270.957m 1.792m 12.10V -5.50V 86.313m -0.652m -9.190m -0.449m -17.306m 1.201m 144.486m 19.246m 2.

40V 143.300u -2.693m 54.320m 83.186m 4.065m 54.20V 103.160m 187.809m 64.562u 133.035m 150.00V 125.539m 159.20V 253.555m 5.560m 3.40V 96.276m 147.30V 138.343m 148.20V 138.642m 75.524m 198.792m 149.000u -3.984u 105.287m 153.803u -2.859m 53.311m 68.252m 4.00V 95.594m 4.40V 107.730m 58.479m 4.00V 303.651u 126.930m 152.024m 55.573m 6.513u 199.326m 87.624m 53.897m 66.513u -2.617m 148.347m 54.10V 129.344u 171.174m 3.778u 120.716m 154.924m 6.070m 5.253u -2.976m 3.80V 99.485m 77.974m 53.361m 161.706u 141.342m 4. 3.1 Freescale Semiconductor A-49 .50V 109.648u 206.830u 217.963m 3.80V 169.00V 152.709m 80.326u 150.264m 57.789u 114.544m 6.163m 5.004m 237.635m 151.981m 4.560m 3.415u -2.317u 264.50V 149.422m 59.831m 157.70V 95.636m 54.418u 306.207m 147.155u 404.90V 160.581m 5.736u 160.196m 150.30V 132.00V 101.941u -2.10V 94.744m 53.885m 6.135m 147.816m 6.475m 148.172m 72.005m 56.833m 53.218m 5.559u 109.308m 163.20V 94.40V 94.115u 178.408m 148.391m 166. 4.117m 54.852u 232.357m 60.367m 3.801m 5.906u 218.545m 177.931m 56.981u 196.500m 53.578m 220.10V 95.10V 102. Rev.40V 217.757m 3.002m 205.10V 276.067m 4.825u 186.227m 155.468m 5.60V 190.543m 148.685m 212.772m 3.683m 228.10V 145.066m 70.618m 169.30V 96.70V 114.30V 105.245m 192.902m 149.90V 99.704m 5.50V 94.263m 182.350m 4.394m 150.60V 95.174u 283.20V 133.141u -2.70V 98.30V 94.208m 53.723u -2.30V 234.794u 170.436m 4.000m 173.641m 53.60V 97.034m 63.699m 149.266m 55.110u -2.979u 100.60V 155.910u -2.725m 4.50V 203.805m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.692u 184.666m 5.075u -3.90V 95.336m 53.230m 5.20V 96.556m 61.80V 117.702u -3.478m 53.70V 179.033u DSP56364 Technical Data.605u 247.90V 121.421u 365.362u 333.60V 112.50V 97.776m 6.80V 95.089m 53.235m 6.

30V -94.939m 1.240u 389.563m -13.1 A-50 Freescale Semiconductor .955m -56.920m 3.30V -2.40V -79.650m DSP56364 Technical Data.907m -5.748u 1.40V -100.856u 1.928m -1.866m -8.497m -1.20V 2.274m -2.415m -55.561m 1.272m 3.392m 0.90V 8.519m 1.982m 2.746m 5.032m 4.794m -134.533m -142.658m -10.302m 1.622e-18 117.036m 3.587m 0.269m -3.00V -91.859m -3.812m -158.60V -96.943m 2.50V -4.846m -57.880u 850.442m -137.604u -1.237m 1.655m 2.441m 7.053m 4.828m -1.014m 678.90V -89.416m -7. -1.30V 960.20V -8.40V -3.30V -100.327m -54.381m 0.644m 1.00V -7.778m -0.685m -2.40V -95.641u 462.709m 2.754m 9.60V 501.10V 2.730u -1.10V -99.994m -3.70V 431.324m 1.057m -131.60V -5.504e-18 0.451m -13.119m -153.082m 2.424m -5.443m -0.80V -6.424m -146.013m 4.00V 58.396u 567.391m -50.461m 1.954m -118.877u -1.056m 2.398m -154.999m -11.722u -1.014m 2.320m -57.80V 378.601u 697.339m -47.106u -655.10V -92.781m 2.280m -9.907m 12.113u 336.102u 238. Rev. 4.087m -1.977m 3.081u 512.381m -157.00V 4.233m -0.662m -154.749m 3.412m -5.890m -4.50V -82.80V -88.052m -0.410m -0.601m -157.10V -8.623m -56.700u 1.499m -2.216m 0.821m -0.10V 1.361m 731.306m -4.004u 590.70V -86.148m -0.607m -58.80V -97.673m -4.727m 11.644m -0.351u 296.30V 3.901m 1.70V -5.363m 2.20V 1.238m -56.090m 2.489m -54.50V 597.713m -51.128m 4.40V 4.088m 2.998m -58.90V 337.770m -58.50V -100.343m -57.00V -98.067u -1.712m -1.198m -58.511m -54.640m 1.50V -95.583m 10.10V -987.709m 0.109m 3.987m 2.224m -55.40V 737.333m 2.809m -57.174m -149.516m 0.118m 4.472m -52.340u 451.20V -93.062m -0.814m -148.724m -52.999m -145.70V -97.081m 1.602m 0.705m -48.033m 1.20V -99.531m 3.913m -155.988m 0.063m 2.70V 7.348m -1.60V 6.20V -1.029m -0.510m -150.931m -6.017m -140.301m -12.80V 8.996m -53.90V -7.810u -1.128m 8.152m -156.50V 5.90V -98.187m -123.30V -9.012u 2.494u 264.687e-18 58.60V -84.203m -127.501m 1.824m -152.

80V -102.60V -104.054 -2.234m 4.106m 5.50V -104.174m -1.247m 6.90V -112.126 -670.439m -170.932m -172.185m -1.220m -1.579m -300.027m -165.560m -179.60V -109.293m 4.750m -59.220 -721.771m -515.10V -115.606m -68.779m -1.337m -64.050m -61.00V -102.221m -313.30V -2.015m -159.955m -61.012m 5.715m 4.388 -3.166 -1.064m -63.422m -59.887m -464.40V -120.10V -1.867m DSP56364 Technical Data.770m 4.510m 3.90V -845.935m -194.138 -2.40V -1.498 -2.387 -2.30V -118.70V -110.211m -159.384m -60.190 -2.410m -414.305m -65.50V -122. Rev.494m -618.691 -981.60V -101.629m -60.981m -187.626m 6.914m 3.30V -1.975 -1.248m -214.935m -73.401m -65.80V -752.60V -568.651m -177.403m -1.978m 6.991m 5.430m -1.070 -1.30V -103.165 -1.949m -62.942 -2.374m -59.126m -174.296m -61.00V -113.408 -825.467m -163.644m 4.20V -103.986m 6.394m 5.40V -386.965m 5.793m 6.1 Freescale Semiconductor A-51 .278m -168.503 -877.597 -929.492m -173.585m -161.80V -105.003m -169.295m 3.033 -2.785m 6.610m -1.277 -2.694m -60.20V -2.461m -363.032 -618.50V -1.970m -1.70V -104.086m 4.311m | [GND_clamp] | |Voltage I(typ) I(min) I(max) | -3.640m -66.052m -727.715m -184.401m -160.474m -62.980m -263.149m -1.832m -164.070m -59.117m -162.80V -111.928m 5.578m -182.513m -72.50V -477.199m 6.301m -511.747m 4.90V -1.084m -59.330m -1.477m -61.20V -1.276 -2.239m 5.831m 4.036m -67.20V -116.659m -61.314 -773.766m -161.30V -107.735m -59.334m 5.720 -2.234m -165.10V -1.80V -1.329m -70.40V -108.483m -63.90V -105.459m -166.30V -298.60V -124.892m -836.70V -101.70V -1.20V -106.10V -103.10V -106.730m -63.384m -190.140m -1.500 -3.70V -660.514m -1.831 -2.609 -2.40V -104.975m -167.257m 4.704m -166.942m -162.634m 5.647m -164.627m 5.002m -60.958m -945.908m -1.242 -2.186m 4.373m -1.00V -106.90V -102. 4.786 -1. 3.843m -176.50V -108.291m -163.60V -1.597m -405.619m -169.365m -69.313m -60.

60V -27. Rev.611p 2.313p 1.195m -0.886m -3.964u -16.278p -754.159p 25.837m -120.789p 32.568p 210.340p 1.40V -74.20V -212.90V -116.365p -4.90V 27.691p -408.051n -3.014m -1.70V 22.817p -70.632u -416.618p 2.637p 0.420u -0.70V -656.248m -107.522n 54.650p 34.484n -0.985p 1.496m -0.051n -4.463p -4.331u -3.40V -580.316p -182.80V -2.028m -166.029m -11.10V -74.10V 33.849p 600.10V 57.40V 13.50V -10.743p 13.803m -0.317u -201.10V -22.269n -41.963p -578.632u -13.497p -694.203p -521.325p -16.146p -13.50V -10.083p 30.60V 46.80V 51.695p 41.737p 3.00V -26.356p 654.867p 37. -1.215p -1.634p 16. 4.451m -0.669p 1.632p 3.303p 3.40V -13.642p 2.092p 0.636p 2.953p -9.968p 0.70V -580.193p 4.980f 0.039p 22.862n -311.656p 1.632p 0.20V 59.317u -18.772p 3.668m -120.339p 492.994n -336.30V -16.092p 3.998p 1.650p 46.60V 19.079f -351.50V 44.50V 16.636u -0.726p -635.939p 3.067p 97.317p 41.868p 23.437p -6.837m -14.158p -0.789u -41.420u DSP56364 Technical Data.014m -27.1 A-52 Freescale Semiconductor .629p 2.80V -10.682p 44.133p 7.50V -1.446p -464.975p 9.011p 1.90V 53.114p -826.300p 2.269n -41.10V 5.799n -0.10V -2.521u -40.098p 547.353p 1.493p 18.005n -11.248m -13.215p -450.552n 52.789u -14.20V 35.30V 11.825p 379.300p 0.158p 3.307p 0.218n -27.80V -2.183p 44.60V -116.30V -26.315p 776.463p -4.20V -1.90V -17.30V -27.964u -13.072p 323.288p 2.067p -126.566p -239.378p 709.959p 466.026p 39.70V -5.319p 3.582m -200.994n -450.005n -11.078n -18.595p -2.279p 2.80V 24.966p 3.90V 62.817p 153.60V -8.948p 2.886m -311.20V -19.187m -1.10V -130.732n 55.958p 2.521u -336.484n 4.375m -40.70V 49.029m -8.30V 38.327p 1.966p 0.861p | [POWER_clamp] | |Voltage I(typ) I(min) I(max) | 3.654p 20.30V 62.737p 0.20V 8.581p 436.567p -14.122p 48.188p -11.303p 0.40V 41.851p 11.

685u -3.496m 4.80V -1.90V -194.346 -2.373m 5.250u -3.771m -670.597m -3.187m 4.970m 5.831 6.20V -17.609 6.000u -3.60V -235.90V -568.408 -981.190u -146.80V -477.185m -1. 4.908m 5. 4.126 -825.30V -938.30V 3.033 -1.849p 2.134u -99.766u -137.386u -256.975 -1.40V -130.10V -752.888m -214.50V -2.50V -1.140m -618.220m -1.221m -464.028m -313.10V -1.680u -331.02/147.028p | dV/dt_r 2.276 5.037u -104.514m -836.84/251.431u -308.786 -1.936u -271.314 -929.190 -1.266p 1.166 5.958m -300.242 -1.375m -166.668m -263.056 5.70V -219.99p 1.10V -173.494m -37.256u -219.148u -121.803m 4.636u 4.15p | variable typ min max [Temperature Range] 40.189u -129.165 -1.0 0.430m 5.60V -2.40V -1.195m 4.355u DSP56364 Technical Data.779m -727.30V -60.248m -363.294 -1.00V 3.127u -230.014p 1.980m -414.054 6.86p 2.403m 5.20V -165.371p 2.070 -1.867m 5.387 6.20/93.330m -945.70V -1.60V -1.451m 4.933u -2.500u -2. Rev.00V -183.0 120.60V -298.301m -8.979m -721.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.30V -1.165 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 2.610m -511.80V -206.174m -1.934u -2.052m -107.138 -1.691 -1.461m -515.0 | variable typ min max [Voltage Range] 3.579m -1.50V -212.720 6.411p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipado_3st | "" Model_type 3-state | variable typ min max C_comp 1.399 -2.20V -1.82/197.942 6.881 -1.400u -115.892m -200.286u -2.032 -773.00/113.220 -877.70V -386.90V -1.887m -618.240u -289.503 -1.20V -845.420m 4.479u -242.749u -109.582m -201.17/74.30V -157.1 Freescale Semiconductor A-53 .40V -1.

10V -5.689m 51.901u -242.750u -270.20V -325.146m -15.00V -400.928m 3.30V 14.20V 3.434m -1.023m 15.856m 1.1 A-54 Freescale Semiconductor .387m -13.607f 0.563m 17.70V 89.672m -6.595u -2.283u -169.590u -464.642m 2.814u 2.286m -3.60V -9.40V -6.243m -1.50V 86.270u -1.90V -452.652m -9.595m 6.784m 0.846m -4.623u -1.80V -11.755e-18 18.639m 1.948m -0.50V -907. -2.821m 7.138m 7.627m -928.964m -0.190m -0.482m 145.497m 49.265u -387.30V -297.50V -7.70V 9.40V 93.449m 2.895m 52.40V -273.976u -516.479m -16.990u -2.799m -1.40V 14.303m 2.564m 48.10V -1.087m 52.931m 52.299u -579.391m 0.725m 22.201m 144.045u -413.50V -252.105m 10.593m 0.152m -0.210m 4.50V 7.70V -10.162u -183.529m 5.80V 10.508m 6.837u -2.313m -0.974m -1.30V 4.944m 1.154m 52.637m 138.804m 146.079u -3.90V 11.661m 0.306m 1.191m -619.10V -359.770m -4.246m 2.133m -1.10V 13.581m 52.902m 1.858m 0.338m -0.943m 23.70V -607.486m 19.80V 90.217u -306.534m 142.416m -3.604m 910.775m 4.30V 93.999m -0.822m -12.70V 93.117u -2.104m DSP56364 Technical Data.199u -357.432m 14.60V 8.60V -729.792m 12.146m -6.115m -1.176u -2.342m -5.411m 4.449m -17.051m 18.90V 94.10V 92.974m 51.384u -218.590m 2.764m 52.30V -4.766m -2.60V 88.855m 2.946m 50.80V 94.957m 1.20V -3.214m -1.80V -519.754m -6. Rev.908m 136.124m 1.00V 32.20V 13.528m -6.217u -1.692m -0.284m 0.277u -352.811u -1.856u -157.415m 2.380m 52.189m 21.417m 8.40V -1.139m 1. 4.372m 8.987m -1.024m 144.548e-18 -1.011u -1.699m -811.575m 1.535m -11.60V 93.00V 92.549u -765.219u -2.346u -909.566m 2.024u -1.201m 2.160m 140.681u -1.954m 1.865m 20.562m 6.236u -422.427u -199.200m 51.233m 52.817m 0.00V 12.20V 92.706m 146.20V -2.367m 7.930m 47.586m 52.980m 147.855m 0.30V -1.895m 146.50V 93.410m 0.204m -5.740m -0.689m -1.302m -17.90V 91.351m 145.10V 1.779m 2.00V -10.40V 5.990m 2.817m 1.407u -496.810m 143.90V -12.851u -660.600m 145.

90V 121.40V 217. 4.004m 237.485m 77.80V 117.60V 97.002m 205.174u 283.115u 178.981u 196.555m 5.20V 103.683m 228.50V 109.60V 155.90V 160.350m 4.543m 148.300u -2.976m 3.825u 186.648u 206.50V 149.276m 147.80V 99.984u 105.066m 70.50V 203.320m 83.757m 3.436m 4.924m 6.230m 5.581m 5.897m 66.263m 182.422m 59.110u -2.317u 264.311m 68.545m 177.075u -3.10V 276.560m 3.1 Freescale Semiconductor A-55 .556m 61.789u 114.809m 64.408m 148.20V 133.704m 5.00V 94.692u 184.30V 132.287m 153.370m 53.636m 54.931m 56.736u 160.253u -2.50V 94.00V 101.941u -2.252m 4.573m 6.391m 166.344u 171.005m 56.544m 6.641m 53.40V 94.702u -3.347m 54.539m 159.338m 3.730m 58.40V 96.20V 96.000u -3.744m 53.699m 149.605u 247.035m 150.776m 6.10V 145.723u -2.772m 3.478m 53.80V 169.716m 154.135m 147.930m 152.034m 63.070m 5.065m 54.235m 6.336m 53.963m 3.979u 100.559u 109.70V 114.90V 95.801m 5.513u 199.594m 4.196m 150.513u -2.794u 170.160m 187.40V 107.70V 179.089m 53.367m 3.20V 138.394m 150.70V 95.10V 102.831m 157.245m 192.475m 148.067m 4.578m 220.906u 218.642m 75. Rev.778u 120.562u 133.30V 138.00V 125.00V 152.10V 129.227m 155.418u 306.618m 169.30V 96.60V 112.20V 253.981m 4.70V 98.805m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.10V 95.208m 53.357m 60.174m 3.852u 232.218m 5.361m 161.024m 55.468m 5.10V 94.060m 147.902m 149.524m 198.90V 99.617m 148.415u DSP56364 Technical Data.264m 57.30V 94.326u 150.624m 53.833m 53.20V 94.651u 126.141u -2.362u 333.00V 95.60V 95.974m 53.666m 5.910u -2.308m 163.479m 4.693m 54.421u 365.186m 4.635m 151.172m 72.50V 97.30V 105.207m 147.342m 4.803u -2.859m 53.343m 148.816m 6.709m 80.792m 149.117m 54.725m 4.30V 234.706u 141. 3.560m 3.60V 190.40V 143.266m 55.163m 5.326m 87.000m 173.885m 6.500m 53.80V 95.685m 212.

224m -55.814m -148.50V 5.988m 0.416m -7.50V -95.128m 4.30V -94.014m 2.604u -1.240u 389.828m -1.954m -118.623m -56.029m -0.880u 850.563m -13.80V 378.778m -0.982m 2.361m 731.004u 590.837m 1.381m -157.424m -5.939m 1.081u 512.40V -100.999m -11.709m 0.106u -655.724m -52.601m -157.00V 303.662m -154.754m 9.50V -82.398m -154.391m -50.472m -52.504e-18 0.770m -58.30V 3.920m 3.561m 1.746m 5.20V -8.20V -1.033u -1.640m 1.877u -1.363m 2.062m -0.274m -2.067u -1.30V 960.80V 8.082m 2.052m -0.036m 3.931m -6.090m 2.20V -99.821m -0.10V -99.10V -92.955m -56.174m -149.30V -9.20V 2.622e-18 117.10V -987.30V -100.00V -91.20V -93.856u 1.451m -13.442m -137.658m -10.705m -48.749m 3.119m -153.673m -4.90V -89.510m -150.410m -0.60V -84.700u 1.722u -1.148m -0.60V -5.118m 4.392m 0.70V -86.90V -98.50V -4.685m -2.412m -5.70V -97.10V 2.80V -6.198m -58.00V -98.60V 501.216m 0.339m -47.1 A-56 Freescale Semiconductor .866m -8.272m 3.727m 11.70V 7.90V 337.40V 4.415m -55.320m -57.602m 0.641u 462.237m 1.943m 2.824m -152.033m 1.644m -0.913m -155.340u 451.977m DSP56364 Technical Data.511m -54.70V 431.810u -1.781m 2.730u -1.333m 2.70V -5.40V -3.238m -56.10V 1.00V 4.499m -2.113u 336.601u 697.081m 1.713m -51.50V 597.20V 1.890m -4.00V -7.80V -88.907m 12.794m -134.441m 7.013m 4.687e-18 58.102u 238.128m 8.533m -142.516m 0.203m -127.461m 1.928m -1.301m -12.712m -1.327m -54.056m 2.644m 1.489m -54. -2.351u 296.109m 3.80V -97.343m -57.494u 264.846m -57.424m -146.709m 2.187m -123.306m -4.269m -3.088m 2.748u 1.348m -1.40V -79.497m -1.90V 8.809m -57. 4.40V 737. Rev.017m -140.233m -0.057m -131.032m 4.501m 1.012u 2.00V 58.607m -58.987m 2.531m 3.90V -7.907m -5.859m -3.443m -0.30V -2.10V -8.583m 10.152m -156.014m 678.60V 6.60V -96.053m 4.40V -95.324m 1.655m 2.302m 1.519m 1.996m -53.999m -145.280m -9.087m -1.830u 217.381m 0.994m -3.063m 2.155u 404.587m 0.396u 567.

500 -3.20V -1.422m -59.60V -101.138 -2.50V -104.027m -165.50V -477.513m -72.955m -61.483m -63.715m 4.20V -103.597m -405.365m -69.735m -59.234m -165.60V -109.704m -166.832m -164.050m -61.970m -1.329m -70.126m -174.70V -1.831 -2.975 -1.221m -313.126 -670.00V -106.40V -108.384m -60.914m 3.186m 4.651m -177.892m -836.981m -187.90V -845.50V -122.70V -660.647m -164.597 -929.644m 4.70V -104.474m -62.650m 3.373m -1.301m -511.10V -103.60V -124.720 -2.388 -3.958m -945.384m -190.394m 5.560m -179.30V -103.30V -2.80V -1.514m -1.90V -102.975m -167.498 -2.640m -66.459m -166. 4.052m -727.40V -104.965m 5.949m -62.991m 5.578m -182.086m 4.064m -63.313m -60.779m -1.747m 4.387 -2.634m 5.626m 6.337m -64.80V -111.494m -618.117m -162.510m 3.694m -60.106m 5.935m -194.054 -2.70V -101.278m -168.40V -386.786 -1.20V -106.10V -106.750m -59.00V -102.374m -59.410m -414.140m -1.492m -173.461m -363.467m -163.1 Freescale Semiconductor A-57 .978m 6.185m -1.609 -2.80V -105.980m -263.174m -1.60V -568.40V -1.311m | [GND_clamp] | |Voltage I(typ) I(min) I(max) | -3.812m -158.401m -65.10V -1.619m -169.291m -163.659m -61.20V -116.305m -65.276 -2.166 -1.10V -1.277 -2.149m DSP56364 Technical Data.730m -63.932m -172.60V -104.887m -464.10V -115.627m 5.610m -1.334m 5.715m -184.60V -1.30V -1.330m -1.928m 5.430m -1.998m -58. Rev.032 -618.439m -170.908m -1.70V -110.503 -877.00V -113.30V -107.843m -176.165 -1.986m 6.40V -120.295m 3.785m 6.80V -102.070 -1.942m -162.50V -1.296m -61.247m 6.211m -159.036m -67.20V -2.239m 5.070m -59.90V -105.257m 4.606m -68.015m -159.831m 4.766m -161.403m -1.80V -752.220 -721.190 -2.314 -773.691 -981.084m -59.002m -60.242 -2.199m 6.50V -108.50V -100.408 -825.90V -112.90V -1.293m 4.033 -2.30V -118.234m 4.793m 6.629m -60. 3.401m -160.477m -61.585m -161.003m -169.220m -1.771m -515.012m 5.770m 4.942 -2.935m -73.

365p -4.356p 654.566p -239.215p -450.737p 0.642p 2.50V -1.325p -16.611p 2.315p 776.10V 33.90V 53.80V 51.650p 34.60V 19.849p 600.188p -11.340p 1.789u -14.317p 41.00V -26.005n -11.980f 0.50V -10.837m -14.014m -1.122p 48.743p 13.316p -182.114p -826.579m -300.789p 32.636u -0.552n 52.300p 0.079f -351.158p -0.817p -70.789u -41.187m -1.10V 57.825p 379.654p 20.669p 1.014m -27.582m -200.695p 41.484n DSP56364 Technical Data.70V -580.20V 8.861p | [POWER_clamp] | |Voltage I(typ) I(min) I(max) | 3.70V -656.726p -635.964u -13.451m -0.278p -754. 4.446p -464.133p 7.303p 3.998p 1.420u -0.656p 1.463p -4.288p 2.484n -0.632p 3.215p -1.269n -41.994n -336.567p -14.20V -19.146p -13.1 A-58 Freescale Semiconductor .50V 16.963p -578.437p -6.029m -11.30V -16.378p 709.50V 44.886m -311.737p 3.60V -8.20V -1.90V 27.026p 39.098p 547.618p 2.958p 2.40V -74.799n -0.70V 22.493p 18.581p 436.10V -130.463p -4.20V -212.183p 44.30V -298.078n -18.50V -10.953p -9.331u -3.80V -10.60V -27.886m -3.595p -2.975p 9.072p 323.30V 11.939p 3.051n -4.803m -0.248m -214.522n 54.159p 25.636p 2.029m -8.40V 41.650p 46.948p 2.629p 2.994n -450.60V -116.20V 35.862n -311.632u -13.195m -0.30V -26.158p 3.90V 62.039p 22.269n -41.10V -74.051n -3.40V -13.011p 1.10V -22.067p -126.353p 1.497p -694.303p 0.313p 1.307p 0.279p 2.193p 4.005n -11.203p -521.067p 97.817p 153.682p 44.632p 0.732n 55.691p -408.339p 492.30V -27.521u -40.028m -166.317u -201.375m -40.868p 23.985p 1.521u -336.851p 11.317u -18.300p 2.327p 1.968p 0.70V -5.083p 30.40V -580.772p 3.668m -120.966p 3.959p 466.092p 0.634p 16.867p 37.10V 5.80V 24. -1.092p 3.319p 3.30V 62.80V -2.637p 0.964u -16.90V -17.60V 46.632u -416.568p 210.40V 13.80V -2.90V -116.218n -27. Rev.966p 0.248m -107.20V 59.70V 49.30V 38.496m -0.867m -1.

691 -1.90V -568.668m -263.174m -1.867m 5.40V -130.375m -166.636u 4.17/83.185m -1.20/92.50V -2.494m -37.503 -1.70V -1.803m 4.779m -727.514m -836.831 6.430m 5.403m 5.84/260.609 6.220 -877.20V -845.387 6.408 -981.958m -300.221m -464.10V -1.597m -3. 4.330m -945.814p 2.40V -1.276 5.30V -1.908m 5. 4.663p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [End] DSP56364 Technical Data.887m -618.70V -386.052m -107.80V -1.056 5.582m -201.301m -8.720 6.892m -200.314 -929.771m -670.81/220.070 -1.032 -773.60V -2.50V -212.579m -1.712p | dV/dt_r 2.248m -13.970m 5. Rev.346 -2.138 -1.40V -1.165 -1.054 6.80V -477.248m -363.140m -618.888m -214.50V -1.1 Freescale Semiconductor A-59 .942 6.166 5.10V -752.60V -1.220m -1.187m 4.451m 4.99/130.20V -17.30V -938.331p 1.90V -1.399 -2.190 -1.979m -721.126 -825.461m -515.028m -313.420m 4.033 -1.837m -120.20V -1.980m -414.294 -1.10V -2.975 -1.60V -298.786 -1.496m 4.657p 1.165 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 1.373m 5.881 -1.195m 4.000p 2.30V -60.03/153.610m -511.242 -1.420u 4.

1 A-60 Freescale Semiconductor . 4. Rev. NOTES DSP56364 Technical Data.

Index A out of page and refresh timings 11 wait states 31 15 wait states 33 ac electrical characteristics 4 4 wait states 27 8 wait states 29 Page mode read accesses 26 B wait states selection guide 17 write accesses 25 Page mode timings Boundary Scan (JTAG Port) timing diagram 54 1 wait state 17 bus 2 wait states 20 external address 4 3 wait states 22 external data 4 4 wait states 23 refresh access 37 C E Clock 4 clock electrical design considerations 3 external 4 emory 3 operation 6 Enhanced Serial Audio Interface 9 clocks ESAI 9 internal 4 receiver timing 51. 5 external clock operation 4 external data bus 4 dc electrical characteristics 3 external interrupt timing (negative edge-triggered) design considerations 11 electrical 3 external level-sensitive fast interrupt timing 10 PLL 4 external memory access (DMA Source) timing 12 power consumption 3 External Memory Expansion Port 4. 12 thermal 1 DRAM out of page wait states selection guide 27 DSP56364 Technical Data. 4. 52 configuration 3 timings 47 transmitter timing 50 EXTAL jitter 4 external address bus 4 D external bus control 4.1 Freescale Semiconductor Index-1 . Rev.

10 JTAG Port timing 53.1 Index-2 Freescale Semiconductor . 6 I Characteristics 6 performance issues 4 PLL design considerations 4 internal clocks 4 PLL performance issues 4 interrupt and mode control 6 Port A 4 interrupt control 6 Port C 9 interrupt timing 7 Power 2 external level-sensitive fast 10 power consumption design considerations 3 external negative edge-triggered 11 R J recovery from Stop state using IRQA 11. 12 Jitter 4 RESET 6 JTAG 12 Reset timing 7. 4. 2 Serial Host Interface (SHI) 3 Memory 3 SHI 7 Memory Configuration 3 signal groupings 1 mode control 6 signals 1 Mode select timing 7 SRAM DSP56364 Technical Data.F O functional signal groups 1 OnCE module 12 operating mode select timing 11 G P GPIO timing 52 Ground 3 package PLL 3 TQFP description 1. 3 Peripheral modules 3 Phase Lock Loop 6 PLL 4. Rev. 54 S M Serial Audio Interface (ESAI) 3 Serial Host Interface 7 maximum ratings 1.

4.1 Freescale Semiconductor Index-3 . 12 Stop timing 7 supply voltage 2 T Test Access Port timing diagram 55 Test Clock (TCLK) input timing diagram 54 thermal characteristics 2 thermal design considerations 1 Timing Enhanced Serial Audio Interface (ESAI) 50 General Purpose I/O (GPIO) Timing 47 OnCE™ (On Chip Emulator) Timing 47 Serial Host Interface (SHI) SPI Protocol Tim- ing 37 Serial Host Interface (SHI) Timing 37 timing interrupt 7 mode select 7 Reset 7 Stop 7 TQFP pin list by number 3 pin-out drawing (top) 1 DSP56364 Technical Data. read and write accesses 12 Stop state recovery from 11. Rev.

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