library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use ieee.std_logic_unsigned.all;

entity divisor is

port (

clk : in std_logic;

reset : in std_logic;

x : in STD_LOGIC_VECTOR (7 downto 0);

y : in STD_LOGIC_VECTOR (7 downto 0);

output : out STD_LOGIC_VECTOR (7 downto 0);

decimal1 : out STD_LOGIC_VECTOR (7 downto 0);

decimal2 : out STD_LOGIC_VECTOR (7 downto 0);

decimal3 : out STD_LOGIC_VECTOR (7 downto 0)

);

end divisor;

architecture divisor of divisor is

type estado is (s0, s1, s2, s3, s4);

signal estadoActual, estadoSiguiente : estado;

signal diviso : STD_LOGIC_VECTOR (7 downto 0);

signal dividendo : STD_LOGIC_VECTOR (7 downto 0);

signal R : STD_LOGIC_VECTOR (7 downto 0);

signal C : STD_LOGIC_VECTOR (7 downto 0);

signal COS : STD_LOGIC_VECTOR (7 downto 0);

signal unidades : STD_LOGIC_VECTOR (7 downto 0);

 signal decenas : STD_LOGIC_VECTOR (7 downto 0);

signal centenas : STD_LOGIC_VECTOR (7 downto 0);

signal milesimas : STD_LOGIC_VECTOR (7 downto 0);

begin

process(clk, estadoActual, x, y)

begin

if (clk'event and clk = '1') then

case estadoActual is

when s0=>

if Inicio='0' then

estadoActual<=s0;

finalz='1;'

else

estadoActual<=s1;

when s1 =>

R <= "00000000";

C <= "00000000";

diviso <= x;

dividendo <= y;

aux<=0;

unidades<=0;

decenas<="00000000";

centenas<="00000000";

milesimas<="00000000";
when s2 =>

when s3 =>

R <= diviso-dividendo;

C <= C+1;

diviso <= R;

when s4 =>

diviso<=x+x+x+x+x+x+x+x+x+x;

aux<=aux+1;

when s5=>

when s6=>

output<= C;

C<='0';

when s7=>

when s8=>

decimal1<= C;

C<='0';

when s9=>

when s10=>

decimal2<= C;

C<='0';

when s11=>

when s12=>

decimal2<= C;

C<='0';

when s13=>

when s14=>
 decimal3<= C;

C<='0';

when s14=>

output<=unidades;

decimal1<=decenas;

decimal2<=centenas;

decimal3<=milesimas;

end case;

end if;

end process;

process(clk, reset,estadoActual,estadoSiguiente)

begin

if (reset = '1') then

estadoActual <= s0;

elsif (clk'event and clk = '1') then

estadoActual <= estadoSiguiente;

end if;

end process;

process (estadoActual, diviso, dividendo) is

begin

case estadoActual is

when s0 => estadoSiguiente <= s1;

 when s1 =>

if (diviso >= dividendo) then

estadoSiguiente <= s2;

else

estadoSiguiente <= s4;

end if;

when s2 => estadoSiguiente <= s3;

when s3 => estadoSiguiente <= s1;

when s4 => estadoSiguiente <= s1;

end case;

end process;

end divisor;