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DE0 User Manual PDF
DE0 User Manual PDF
CONTENTS
Chapter 1 DE0 Package.....................................................................................................................1
1.1 Package Contents .................................................................................................................1
1.2 The DE0 Board Assembly....................................................................................................2
Getting Help.........................................................................................................................2
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Chapter 1
DE0 Package
The DE0 package contains all the components needed to use the DE0 board in conjunction with a
computer that runs the Microsoft Windows software.
Getting Help
Here are the addresses where you can get help if you encounter problems:
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• Altera Corporation
101 Innovation Drive
San Jose, California, 95134 USA
Email: university@altera.com
• Terasic Technologies
No. 356, Sec. 1, Fusing E. Rd.
Jhubei City, HsinChu County, Taiwan, 302
Email: support@terasic.com
Web: DE0.terasic.com
Chapter 2
Altera DE0 Board
This chapter presents the features and design characteristics of the DE0 board.
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Power Supply Input USB Blaster Connector Triple 4 - bit VGA DAC PS/2 Port SD Card Socket
RS - 232 Interface
Power ON/OFF Switch
50 - MHz Oscillator
16 x 2 LCD Interface
Expansion Headers (2)
The DE0 board has many features that allow the user to implement a wide range of designed
circuits, from simple circuits to various multimedia projects.
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• RS-232 transceiver
• PS/2 mouse/keyboard connector
• Two 40-pin Expansion Headers
EP3C16F484
PS/2 Triple 4-bit VGA DAC
EPCS4
USB
Config
Blaster
Device
SDRAM
One 8-Mbyte Single Data Rate Synchronous Dynamic RAM memory chip
Supports 16-bits data bus
Flash memory
4-Mbyte NOR Flash memory
Support Byte (8-bits)/Word (16-bits) mode
SD card socket
Provides both SPI and SD 1-bit mod SD Card access
Pushbutton switches
3 pushbutton switches
Normally high; generates one active-low pulse when the switch is pressed
Slide switches
10 Slide switches
A switch causes logic 0 when in the DOWN position and logic 1 when in the UP position
Clock inputs
50-MHz oscillator
VGA output
Uses a 4-bit resistor-network DAC
With 15-pin high-density D-sub connector
Supports up to 1280x1024 at 60-Hz refresh rate
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Serial ports
One RS-232 port (Without DB-9 serial connector)
One PS/2 port (Can be used through a PS/2 Y Cable to allow you to connect a keyboard and
mouse to one port)
1. Connect the provided USB cable from the host computer to the USB Blaster connector on
the DE0 board. For communication between the host and the DE0 board, it is necessary to
install the Altera USB Blaster driver software. If this driver is not already installed on the
host computer, it can be installed as explained in the tutorial Getting Started with Altera's
DE0 Board. This tutorial is available in the directory DE0\DE0_user_manual on the DE0
System CD-ROM.
2. Connect the 7.5V adapter to the DE0 board
3. Connect a VGA monitor to the VGA port on the DE0 board
4. Turn the RUN/PROG switch on the left edge of the DE0 board to RUN position; the
PROG position is used only for the AS Mode programming
5. Turn the power on by pressing the ON/OFF switch on the DE0 board
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Chapter 3
DE0 Control Panel
The DE0 board comes with a Control Panel facility that allows users to access various components
on the board from a host computer. The host computer communicates with the board through an
USB connection. The facility can be used to verify the functionality of components on the board or
be used as a debug tool while developing RTL code.
This chapter first presents some basic functions of the Control Panel, then describes its structure in
block diagram form, and finally describes its capabilities.
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The concept of the DE0 Control Panel is illustrated in Figure 3.3. The “Control Codes” that perform
the control functions is implemented in the FPGA board. It communicates with the Control Panel
window, which is active on the host computer, via the USB Blaster link. The graphical interface is
used to issue commands to the control codes. It handles all requests and performs data transfers
between the computer and the DE0 board.
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Avalon- MM Flash
Tris tate Bridge Controller Flash
The DE0 Control Panel can be used to light up the LEDs, change the values displayed on 7-segment,
monitor buttons/switches status, read/write the SDRAM and Flash Memory, read data from a PS/2
keyboard, output color pattern to LCD monitor via VGA connector, and read SD-CARD
specification information. The feature of reading/writing a word or an entire file from/to the Flash
Memory allows the user to develop multimedia application (Flash Picture Viewer) without worrying
about how to build a Memory Programmer.
Choosing the LED tab leads to the window in Figure 3.4. Here, you can directly turn the individual
LEDs on or off by selecting them individually or by clicking “Light All” or “Unlight All”.
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Choosing the 7-SEG tab leads to the window in Figure 3.5. In the tab sheet, directly use the
Up-Down control and Dot Check box to specified desired patterns, the 7-SEG patterns on the board
will be updated immediately.
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The ability to set arbitrary values into simple display devices is not needed in typical design
activities. However, it gives the user a simple mechanism for verifying that these devices are
functioning correctly in case a malfunction is suspected. Thus, it can be used for troubleshooting
purposes.
Press the Start button to start button/switch status monitoring process, and button caption is
changed from Start to Stop. In the monitoring process, the status of buttons and switches on the
board is shown in the GUI window and updated in real time. Press Stop to end the monitoring
process.
The ability to check the status of button and switch is not needed in typical design activities.
However, it provides users a simple mechanism for verifying if the buttons and switches are
functioning correctly. Thus, it can be used for troubleshooting purposes.
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A 16-bit word can be written into the SDRAM by entering the address of the desired location,
specifying the data to be written, and pressing the Write button. Contents of the location can be
read by pressing the Read button. Figure 3.7 depicts the result of writing the hexadecimal value
7eff into location 000000, followed by reading the same location.
The Sequential Write function of the Control Panel is used to write the contents of a file into the
SDRAM as follows:
1. Specify the starting address in the Address box.
2. Specify the number of bytes to be written in the Length box. If the entire file is to be
loaded, then a checkmark may be placed in the File Length box instead of giving the
number of bytes.
3. To initiate the writing of data, click on the Write a File to Memory button.
4. When the Control Panel responds with the standard Windows dialog box asking for the
source file, specify the desired file in the usual manner.
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The Control Panel also supports loading files with a .hex extension. Files with a .hex extension are
ASCII text files that specify memory values using ASCII characters to represent hexadecimal
values. For example, a file containing the line
0123456789ABCDEF
defines four 8-bit values: 01, 23, 45, 67, 89, AB, CD, EF. These values will be loaded consecutively
into the memory.
The Sequential Read function is used to read the contents of the SDRAM and place them into a file
as follows:
1. Specify the starting address in the Address box.
2. Specify the number of bytes to be copied into the file in the Length box. If the entire
contents of the SDRAM are to be copied (which involves all 8 Mbytes), then place a
checkmark in the Entire Memory box.
3. Press Load Memory Content to a File button.
4. When the Control Panel responds with the standard Windows dialog box asking for the
destination file, specify the desired file in the usual manner.
Users can use the similar way to access the Flash. Please note that users need to erase the flash
before writing data to it.
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3.6 SD CARD
The function is designed to read the identification and specification of the SD card. The 1-bit SD
MODE is used to access the SD card. This function can be used to verify the functionality of
SD-CARD Interface. Follow the steps below to exercise the SD card:
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3.7 VGA
DE0 control panel provides VGA pattern function that allows users to output color pattern to
LCD/CRT monitor using the DE0 FPGA board. Please follow the steps below to generate the VGA
pattern function:
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Chapter 4
Using the DE0 Board
This chapter gives instructions for using the DE0 board and describes each of its I/O devices.
The DE0 board contains a serial EEPROM chip that stores configuration data for the Cyclone III
FPGA. This configuration data is automatically loaded from the EEPROM chip into the FPGA each
time power is applied to the board. Using the Quartus II software, it is possible to reprogram the
FPGA at any time, and it is also possible to change the non-volatile data that is stored in the serial
EEPROM chip. Both types of programming methods are described below.
1. JTAG programming: In this method of programming, named after the IEEE standards Joint
Test Action Group, the configuration bit stream is downloaded directly into the Cyclone III
FPGA. The FPGA will retain this configuration as long as power is applied to the board;
the configuration is lost when the power is turned off.
2. AS programming: In this method, called Active Serial programming, the configuration bit
stream is downloaded into the Altera EPCS4 serial EEPROM chip. It provides non-volatile
storage of the bit stream, so that the information is retained even when the power supply to
the DE0 board is turned off. When the board's power is turned on, the configuration data in
the EPCS4 device is automatically loaded into the Cyclone III FPGA.
The sections below describe the steps used to perform both JTAG and AS programming. For both
methods the DE0 board is connected to a host computer via a USB cable. Using this connection, the
board will be identified by the host computer as an Altera USB Blaster device. The process for
installing on the host computer the necessary software device driver that communicates with the
USB Blaster is described in the tutorial Getting Started with Altera's DE0 Board. This tutorial is
available on the DE0 System CD-ROM.
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• Connect the supplied USB cable to the USB Blaster port on the DE0 board (see Figure 2.1)
• Configure the JTAG programming circuit by setting the RUN/PROG switch (see Figure 4.4)
to the PROG position.
• The EPCS4 chip can now be programmed by using the Quartus II Programmer module to
select a configuration bit stream file with the .pof filename extension
• Once the programming operation is finished, set the RUN/PROG switch back to the RUN
position and then reset the board by turning the power switch off and back on; this action
causes the new configuration data in the EPCS4 device to be loaded into the FPGA chip.
AS Mode
Config
EPCS4
Serial
Configuration
Device
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In addition to its use for JTAG and AS programming, the USB Blaster port on the DE0 board can
also be used to control some of the board's features remotely from a host computer. Details that
describe this method of using the USB Blaster port are given in Chapter 3.
There are also 10 slide switches (sliders) on the DE0 board. These switches are not debounced, and
are intended for use as level-sensitive data inputs to a circuit. Each switch is connected directly to a
pin on the Cyclone III FPGA. When a switch is in the DOWN position (closest to the edge of the
board) it provides a low logic level (0 volts) to the FPGA, and when the switch is in the UP position
it provides a high logic level (3.3 volts).
There are 10 user-controllable LEDs on the DE0 board. Each LED is driven directly by a pin on the
Cyclone III FPGA; driving its associated pin to a high logic level turns the LED on, and driving the
pin low turns it off. Figure 4.5 and Figure 4.6 show the connections between the push buttons, slide
switches, and Cyclone III FPGA
A list of the pin names on the Cyclone III FPGA that are connected to the toggle switches is given
in Table 4.1. Similarly, the pins used to connect to the pushbutton switches and LEDs are displayed
in Table 4.2 and Table 4.3, respectively.
3.3V
BUTTON0
H2
BUTTON1
G3
BUTTON2
F1
Figure 4.5. Connections between the pushbutton and Cyclone III FPGA
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D2 E4 E3 H7 J7 G5 G4 H6 H5 J6
Logic ``1``
SW9 SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 Logic``0``
Figure 4.6. Connections between the toggle switches and Cyclone III FPGA
LEDG0
LEDG0
J1
LEDG1
LEDG1
J2
LEDG2
LEDG2
J3
LEDG3
LEDG3
H1
LEDG4 LEDG4
F2
LEDG5 LEDG5
E1
LEDG6
LEDG6
C1
LEDG7
LEDG7
C2
LEDG8
LEDG8
B2
LEDG9 LEDG9
B1
Figure 4.7. Connections between the LEDs and Cyclone III FPGA
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Each segment in a display is identified by an index from 0 to 6, with the positions given in Figure
4.9. In addition, the decimal point is identified as DP. Table 4.4 shows the connections between the
FPGA pins to the 7-segment displays.
HEX0
HEX0_D0 HEX0_D0
E11
HEX0_D1
F11
HEX0_D2
HEX0_D5 H12
HEX0_D1 HEX0_D3
H13
HEX0_D6
HEX0_D4
HEX0_D4 HEX0_D2 G12
HEX0_D5
F12
HEX0_D6
F13
HEX0_DP HEX0_DP
HEX0_D3 D13
Figure 4.8. Connections between the 7-segment displays and Cyclone III FPGA
5 1
6
4 2
DP
3
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The clock distribution on the DE0 board is shown in Figure 4.10. The associated pin assignments
for clock inputs to FPGA I/O pins are listed in Table 4.5.
GPIO 0 (J4)
GPIO0_CLKIN0
(CLK12) 12 1
GPIO0_CLKIN1 3
CLK13)AB 12
( AA GPIO0_CLKOUT0
PLL1_CLKOUTn) 3 19
GPIO0_CLKOUT1
( PLL1_CLKOUTp)AB 3 21
CLOCK_50 ( AA
G21 (CLK4)
50MHz
OSC
CLOCK_50_2
B12 (CLK9) GPIO 1 (J5)
GPIO1_CLKIN0
(CLK14) 11 1
GPIO1_CLKIN1 3
(CLK15)AB 11
AA GPIO1_CLKOUT0
PLL4_CLKOUTn) 16 19
GPIO1_CLKOUT1
( (PLL4_CLKOUTp)R 6T 21
(http://de0.terasic.com).
Table 4.6. The listed information on the LCD module
Board
Description
Reference
The LCD module has built-in fonts and can be used to display text by sending appropriate
commands to the display controller, which is called HD44780. Detailed information for using the
display is available in its datasheet, which can be found on the manufacturer's web site, and from
the Datasheet/LCD folder on the DE0 System CD-ROM. A schematic diagram of the LCD module
showing connections to the Cyclone III FPGA is given in Figure 4.12. The associated pin
assignments appear in Table 4.7.
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F21 D22 D21 C22 C21 B22 B21 D20 C20 E21 F22 E22
LCD_RW
LCD_BLON
LCD_DATA0
LCD_DATA1
LCD_DATA2
LCD_DATA3
LCD_DATA4
LCD_DATA6
LCD_DATA7
LCD_DATA5
LCD_RS
LCD_EN
2 X 16 LCD Module
Figure 4.12. Connections between the LCD module and Cyclone III FPGA
Note that some LCD modules do not have backlight. Therefore the LCD_BLON signal should not
be used in users’ design projects.
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Finally, Figure 4.13 shows the related schematics. The figure shows the protection circuitry for only
two of the pins on each header, but this circuitry is included for all 72 data pins. Table 4.8 gives the
pin assignments.
(GPIO 0) (GPIO 1)
J4 J5
[AB12] GPIO0_CLKIN0 1 2 GPIO0_D0 [AB16] [AB11] GPIO1_CLKIN0 1 2 GPIO1_D0 [AA20]
[AA12] GPIO0_CLKIN1 3 4 GPIO0_D1 [AA16] [AA11] GPIO1_CLKIN1 3 4 GPIO1_D1 [AB20]
[AA15] GPIO0_D2 5 6 GPIO0_D3 [AB15] [AA19] GPIO1_D2 5 6 GPIO1_D3 [AB19]
[AA14] GPIO0_D4 7 8 GPIO0_D5 [AB14] [AB18] GPIO1_D4 7 8 GPIO1_D5 [AA18]
[AB13] GPIO0_D6 9 10 GPIO0_D7 [AA13] [AA17] GPIO1_D6 9 10 GPIO1_D7 [AB17]
5V 11 12 GND 5V 11 12 GND
[AB10] GPIO0_D8 13 14 GPIO0_D9 [AA10] [Y17] GPIO1_D8 13 14 GPIO1_D9 [W17]
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VGA_R0
H19
VGA_R1
H17
VGA_R2
H20
VGA_R3
H21
6
1 11
VGA_R
VGA_G0 VGA_G
H22
VGA_G1
J17
K17 VGA_G2 VGA_B
J21 VGA_G3
10
VGA_B0 5
K22 15
VGA_B1
K21
VGA_B2
J22
VGA_B3
K18
VGA_VS
L22
VGA_HS
L21
Figure 4.14. Connections between VGA circuit and Cyclone III FPGA
The timing specification for VGA synchronization and RGB (red, green, blue) data can be found on
various educational web sites (for example, search for “VGA signal timing”). Figure 4.15 illustrates
the basic timing requirements for each row (horizontal) that is displayed on a VGA monitor. An
active-low pulse of specific duration (time a in the figure) is applied to the horizontal
synchronization (hsync) input of the monitor, which signifies the end of one row of data and the
start of the next. The data (RGB) inputs on the monitor must be off (driven to 0 V) for a time period
called the back porch (b) after the hsync pulse occurs, which is followed by the display interval (c).
During the data display interval the RGB data drives each pixel in turn across the row being
displayed. Finally, there is a time period called the front porch (d) where the RGB signals must
again be off before the next hsync pulse can occur. The timing of the vertical synchronization (vsync)
is the same as shown in Figure 5.13, except that a vsync pulse signifies the end of one frame and the
start of the next, and the data refers to the set of rows in the frame (horizontal timing). Table 4.9 and
Table 4.10 show different resolutions of the durations of time periods a, b, c, and d for both
horizontal and vertical timing.
Detailed information for using the ADV7123 video DAC is available in its datasheet, which can be
found on the manufacturer's web site, or in the Datasheet/VGA DAC folder on the DE0 System
CD-ROM. The pin assignments between the Cyclone III FPGA and the VGA connector are listed
in Table 4.11. An example of code that drives a VGA display is described in Sections 5.3.
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U3 ADM3202
UART_RXD 12 13
U22 R1OUT R1IN RXD
UART_RTS 9 8
V22 R2OUT R2IN RTS
UART_TXD 11 14
U21 T1IN T1OUT TXD
UART_CTS 10 7
V21 T2IN T2OUT CTS
GND1
Figure 4.17. Connections between the ADM232 (RS-232) chip and Cyclone III FPGA
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PS2_KBCLK
P22
PS2_MSCLK
R21
J3
8 6
5 3
2 1
R22 PS2_MSDAT
P21 PS2_KBDAT
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DATA2
SD_DATA3 1
W21 DATA3
SD_CMD 2
Y22 CMD
3
VSS
4
3.3V VCC
SD_CLK 5
Y21 CLK
6
VSS
SD_DATA0 7
AA22 DATA0
8
DATA1
SD_WPn 11
W20 WP
SDRAM U1
DRAM_ADDR[12:0]
See Table 4.15 A[12:0]
DRAM_DQ[15:0]
See Table 4.15 D[15:0]
DRAM_BA_0
B5 BA0
DRAM_BA_1
A4 BA1
DRAM_LDQM
E7 LDQM
DRAM_UDQM
B8 UDQM
DRAM_WE_N
D6 nWE
DRAM_CAS_N
G8 nCAS
DRAM_RAS_N
F7 nRAS
DRAM_CS_N
G7 nCS
DRAM_CLK
E5 CLK
DRAM_CKE
E6 CKE
FLASH U2
FL_ADDR[12:0]
See Table 4.16 A[21:0]
FL_DQ[15:0]
See Table 4.16 DQ[14:0]
FL_DQ15_AM1
Y2 DQ15/A-1
FL_WE_N
P4 WE#
FL_RST_N
R1 RESET#
FL_WP_N
T3 WP#ACC
FL_RY
M7 RY/BY#
FL_CE_N
G8 CE#
FL_OE_N
R6 OE#
FL_BYTE_N
AA1 BYTE#
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Chapter 5
Examples of Advanced Demonstrations
This chapter provides a number of examples of advanced circuits implemented on the DE0 board.
These circuits provide demonstrations of the major features on the board, such as its video
capabilities and SD card storage. For each demonstration the Cyclone III FPGA (or EPCS4 serial
EEPROM) configuration file is provided, as well as the full source code in Verilog HDL code. All
of the associated files can be found in the DE0\demonstrations folder from the DE0 System
CD-ROM. For each of demonstrations described in the following sections, we give the name of the
project directory for its files, which are subdirectories of the DE0_demonstrations folder.
The Verilog source code for this demonstration is provided in the DE0_Default folder, which also
includes the necessary files for the corresponding Quartus II project. The top-level Verilog file,
called DE0_Default.v, can be used as a template for other projects, because it defines ports that
correspond to all of the user-accessible pins on the Cyclone III FPGA.
5.2 SD Card
Many applications use a large external storage device, such as a SD card or CF card, to store data.
The DE0 board provides the hardware and software needed for SD card access. In this
demonstration we will show how to browse files stored in the root directory of a SD card and how
to read the file contents of a specific file. The size of the SD card should be less or equal to 2GB.
Also, it is required to be formatted as FAT (FAT16 or FAT 32) File System in advance. Long file
name is supported in this demonstration.
Figure 5.1 shows the hardware system block diagram of this demonstration. The system requires a
50 MHz clock provided from the board. Four PIO pins are connected to the SD card socket. They
are SD_CLK, SD_CMD, SD_DAT and SD_WP_N. The three pins SD_CLK, SD_CMD and
SD_DAT are used to implement SD 1-bit Mode protocol for accessing the SD card content. The SD
1-bit protocol and FAT File System function are all implemented by NIOS II software. The software
is stored in the on-board SDRAM memory.
Figure 5.2 shows the software stack of this demonstration. The NIOS PIO block provides basic IO
functions to access hardware directly. The functions are provided from NIOS II system and the
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function prototype is defined in the header file <io.h>. The SD-CARD block implements SD 1-bit
mode protocol for communication with the SD card. The FAT File System block implements
reading function for FAT16 and FAT 32 file system. Long filename is supported. By calling the
exported FAT functions, users can browse files under the root directory of the SD card. Furthermore,
users can open a specified file and read the contents of the file.
The main block implements main control of this demonstration. When the program is executed, it
detects whether a SD card is inserted. If a SD card is found, it will check whether the SD card is
formatted as FAT file system. If a FAT file system is found, it searches all files in the root directory
of the FAT file system and displays their names in the nios2-terminal. If a text file named “test.txt”
is found, it will dump the file contents. If it successfully recognizes the FAT file system, it will turn
on the all of green LED. On the other hand, it will turn off all of the green LED if it fails to parse
the FAT file system. Half number of the green LED will be turn on if there is no SD card found in
the SD Card socket. If users press BUTTON2 of the DE0 board, the program will perform above
process again.
Main
SD-CARD
NIOS II PIO
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Demonstration Setup
Make sure Quartus II and NIOS II are installed on your PC.
Change Switch to “PROG” Mode to “RUN” mode in DE0 board.
Power on the DE0 board.
Connect USB Blaster to the DE0 board and install USB Blaster driver if necessary.
Execute the demo batch file “test.bat” under the batch file folder,
DE0_NIOS_SDCARD\demo_batch.
After NIOS II program is downloaded and executed successfully, a prompt message will be
displayed in nios2-terminal
Copy test files to the root directory of the SD Card.
Insert the SD card into the SD Card socket of DE0, as shown in Figure 5.3.
Press Button2 of the DE0 board to start reading SD Card.
The program will display SD Card information, as shown in Figure 5.4.
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Figure 5.5 shows the basic block diagram of this demonstration. There are two major blocks in the
circuit, called VGA_Pattern and VGA_Ctr. The VGA_Pattern block controls every pixel value for
each horizontal and vertical line; therefore the VGA_Pattern block can generate many color patterns.
The VGA_Ctr block generate VGA control signals HS and VS that depend on the user’s resolution
setting that are used to output onto the LCD/CRT monitor.
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mVGA_R VGA_R
mVGA_G VGA_G
mVGA_Y VGA_VS
SW0
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Figure 5.6. The setup for the VGA color pattern demonstration
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Pattern 1 Pattern 2
SW0 SW0
Figure 5.7. The output color pattern type for the demonstration
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Chapter 6
Appendix
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