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Datasheet PDF
Datasheet PDF
DUAL JK FLIP-FLOP
WITH SET AND CLEAR
The SN54/ 74LS76A offers individual J, K, Clock Pulse, Direct Set and Di-
rect Clear inputs. These dual flip-flops are designed so that when the clock
goes HIGH, the inputs are enabled and data will be accepted. The Logic Level DUAL JK FLIP-FLOP
of the J and K inputs will perform according to the Truth Table as long as mini- WITH SET AND CLEAR
mum set-up times are observed. Input data is transferred to the outputs on the
HIGH-to-LOW clock transitions. LOW POWER SCHOTTKY
J SUFFIX
MODE SELECT — TRUTH TABLE CERAMIC
CASE 620-09
INPUTS OUTPUTS 16
OPERATING MODE 1
SD CD J K Q Q
Set L H X X H L
Reset (Clear) H L X X L H
*Undetermined L L X X H H
N SUFFIX
Toggle H H h h q q
PLASTIC
Load “0” (Reset) H H l h L H
16 CASE 648-08
Load “1” (Set) H H h l H L
Hold H H l l q q 1
*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously.
H,h = HIGH Voltage Level D SUFFIX
L,l = LOW Voltage Level
SOIC
X = Immaterial 16
1 CASE 751B-03
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior
to the HIGH-to-LOW clock transition
ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC
LOGIC DIAGRAM
LOGIC SYMBOL
Q 2 7
Q
SD 15 SD 11
16 K Q 12 K Q
1 CP 6 CP
CLEAR (CD) SET (SD)
K 4 J C Q 14 9 J C Q 10
J D D
3 8
CLOCK (CP) VCC = PIN 5
GND = PIN 13
VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table
J, K 20
Clear 60 µA VCC = MAX, VIN = 2.7 V
Clock 80
IIH Input HIGH Current
J, K 0.1
Clear 0.3 mA VCC = MAX, VIN = 7.0 V
Clock 0.4
J, K – 0.4
IIL Input LOW Current mA VCC = MAX, VIN = 0.4 V
Clear, Clock – 0.8
IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX
ICC Power Supply Current 6.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.