MULTIPLICADOR:

library IEEE;
use ieee.std_logic_1164.all;
entity dec7_cat is
port( A: in std_logic_vector(3 downto 0);
S: in std_logic;
seg: out std_logic_vector(6 downto 0));
end dec7_cat;
architecture funlog of dec7_cat is
signal P : std_logic_vector(4 downto 0);
begin
P<= S&A;
with P select
seg<= "1111110" when "10000",--0
"0110000" when "10001",--1
"1101101" when "10010",--2
"1111001" when "10011",--3
"0110011" when "10100",--4
"1011011" when "10101",--5
"1011111" when "10110",--6
"1110000" when "10111",--7
"1111111" when "11000",--8
"1111011" when "11001",--9
"0000000" when others;
end funlog;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity multp is
port ( a,b : in integer range 0 to 15;
s : in std_logic;
DECENA,UNIDAD : out std_logic_vector(6 downto 0);
M : out integer range 0 to 255);
end multp;
architecture structure of multp is
component dec7_cat port( A: in std_logic_vector(3 downto 0);S: in std_logic;
seg: out std_logic_vector(6 downto 0));
end component;
signal U,D : std_logic_vector(3 downto 0);
begin
M<= a*b when(s='0') else
a*10 + b;
D<=conv_std_logic_vector(a, 4);
U<=conv_std_logic_vector(b, 4);
stage_a: dec7_cat port map(D(3 downto 0),s,DECENA(6 downto 0));
stage_b: dec7_cat port map(U(3 downto 0),s,UNIDAD(6 downto 0));
end structure;