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The main function of I/O system is to transfer information between processor or memory and the outside world. 6.1.1 Input/ Output System ‘The Input/Output system has two major functions = ‘Interface to the processor and memory via the system bus, ‘+ Interface to one or more 1/O devices by tailored. data links For clear understanding refer Fig. 6. Links to peripheral devices are used to exchange control, status and data between the 1/O system and the external devices. ieee Bas Sa Fd Daa Bus oer ‘Conivol Bus Processor Memory WO System Links to WO Device v0 device |] uo device || v0 device || v0 Deview a 8 ¢ D Extemal YO Devices Fig. 6.1 Generic model of computer system @-1)Microprocessor & Microcontroller System 6-2 WO and Memory Interface ‘An important point that is to be noted here is, an 1/O system is not simply mechanical connectors for connecting different devices required in the system to the system bus. It contains some logic for performing function of communication between the peripheral (I/O device) and the bus. The I/O system must have an interface internal to the computer ( to the processor and memory ) and an interface extemal to the computer ( to the external 1/0 devices ). 6.1.2 Requirements of VO System ‘The 1/O system is nothing but the hardware required to connect an 1/O device to the ‘bus. It is also called VO interface. The major requirements of an 1/O interface are : 1. Control and timing 2. Processor communication 3. Device communication 4, Data buffering 5. Error detection Al these requirements are explained here. The 1/O interface includes a control and timing requirements to co-ordinate the flow of traffic between intemal resources (memory, system bus ) and external devices. Processor communication involves different types of signal transfers such as ‘= Processor sends commands to the I/O system which are generally the control signals on the control bus. ‘+ Exchange of data between the processor and the 1/O interface over the data bus. ‘+ The data transfer rate of peripherals is often much slower than that of the processor. So it is necessary to check whether peripheral is ready or not for data transfer. If not, processor must wait. So it is important to know the status of 1/0 interface. The status signals such as BUSY, READY can be used for this purpose. + A nnumber of peripheral devices may be connected to the 1/0 interface. The 1/0 interface controls the communication of each peripheral with processor. So it rust recognize one unique address for each peripheral connected to it. The I/O interface must able to perform device communication which involves commands, status information and data. Data buffering is also an essential task of an 1/O interface. Data transfer rates of peripheral devices are quite high than that of processor and memory. The data coming from memory or processor are sent to an I/O interface, buffered and then sent to the peripheral device at its data rate. Also, data are buffered in 1/O interface so as not to tie up the memory in a slow transfer operation. Thus the 1/O interface must be able to ‘operate at both peripheral and memory speeds.Microprocessor & Microcontroller System 6-3 WO and Memory Interface 1/0 interface is also responsible for error detection and for reporting errors to the processor. The different types of errors are mechanical, electrical malfunctions reported by the device such as bad disk track, unintentional changes to the bit pattern, transmission errors etc. To fulfil all these requirements the important blocks necessary in any 1/0 interface are shown in Fig. 62. Intertace to systom bus —— VO Interfaco Fig. 6.2 Block diagram of UO interface ‘As shown in the Fig. 62, 1/O interface consists of data register, status/control register, address decoder and extemal device interface logic. The data register holds the data being ‘transferred to or from the processor. The status/control register contains information relevant to the operation of the 1/O device. Both data and status/control registers are connected to the data bus. Address lines drive the address decoder. The address decoder cenables the device to recognize its address when address appears on the address lines. The extemal device interface logic accepts inputs from address decoder, processor control lines and status signal from the 1/O device and generates control signals to control the direction and speed of data transfer between processor and 1/0 devices. ‘The Fig. 63 shows the 1/O interface for input device and output device. Here, for simplicity block schematic of 1/O interface is shown instead of detail connections. The address decoder enables the device when its address appears on the address lines. The data register holds the data being transferred to or from the processor. The status registerMicroprocessor & Microcontroller System 6-4 VO and Memory Interface contains information relevant to the operation of the 1/0 device. Both the data and status registers are assigned with unique addresses and they are connected to the data bus. Assess nes Dota nes Cont! ines {8} UO interface for input device ap rates tines Bus Data tines Control ines (©) UO interface for output device: Fig. 6.3 6.1.3 VO Ports The simplest form of 1/O interface is an I/O port. The data transfer ‘microprocessor and input device is done with the help of input port. The data between microprocessor and output device is done with the help of output port. between, ‘transferMicroprocessor & Microcontroller System 6-5 WO and Memory Interface Input port : It is used to read data from the input device such as keyboard. The simplest form of input port is a buffer. The input device is connected to the microprocessor through buffer eo shown Dalatom inp in the Fig. G4. This bulfer is trate vice buffer and its output ie available onl (Keyecar) —jinen enable. signal, is active. When microprocessor wants to road data from the input device (keyboard), the control Fig. 04 signals from the microprocessor activates the buffer by asserting enable input of the buffer. Once the buffer is enabled, data from the input device is available on the data ‘bus. Microprocessor reads this data by initiating read command Output port : It i woed to send data tothe output device ouch a0” display from the microprocessor. “The cimplost form of ‘output port is latch. The output device ie connected to the microprocessor > through latch, as shown in the Fig. 65. ‘Wado device When microprocessor wants to send data (Display) to the output device, it puts the data on the data bus and activates the clock signal of the latch, latching the data from the data bus at the output of latch Its then available at the output of latch Fig, 65 for the output device. 6.2 / Data Transfer Techniquos In 1/O data transfer, the system requires the transfer of data between I/O devices and microprocessor using I/O interface. It uses various techniques to perform I/O operations. ‘These are : * Program Controlled I/O or Programmed 1/0 or Polled 1/0. + Interrupt Driven 1/0. ‘* Hardware Controlled 1/0 or DMA.