VLSI Testing

Testability
Testability Analysis
Analysis

Virendra Singh
Indian Institute of Science (IISc)
Bangalore
virendra@computer.org

E0-286: Testing and Verification of SoC Design

Lecture - 11
Feb 15, 2008 E0-286@SERC 1
 Controllability
Controllability Examples
Examples

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 Controllability
Controllability Examples
Examples

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 Observability
Observability Examples
Examples
To observe a gate input:
Observe output and make other input values non-controlling

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 Observability
Observability Examples
Examples
To observe a fanout stem:
Observe it through branch with best observability

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 Levelization
Levelization Algorithm
Algorithm
™Label each gate with max # of logic levels from
primary inputs or with max # of logic levels from
primary output
™Assign level # 0 to all primary inputs (PIs)
™For each PI fanout:
¾Label that line with the PI level number, &
¾Queue logic gate driven by that fanout
™While queue is not empty:
¾Dequeue next logic gate
¾If all gate inputs have level #’s, label the gate
with the maximum of them + 1;
¾Else, requeue the gate
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 Controllability
Controllability -- Level
Level 0
0
Circled numbers give level number. (CC0, CC1)

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 Controllability
Controllability -- Level
Level 2
2

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Combinational
Combinational Controllability
Controllability

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 Observability
Observability for
for Level
Level 1
1
Number in square box is level from primary outputs (POs).
(CC0, CC1) CO

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 Observabilities
Observabilities -- Level
Level 2
2

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 Example
Example (PODEM)
(PODEM)
„ Select path s – Y for fault propagation

sa1

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 Example
Example --
-- Step 2 ss sa1
Step 2 sa1
„ Initial objective: Set r to 1 to sensitize fault

sa1

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 Example
Example --
-- Step 3 ss sa1
Step 3 sa1
„ Backtrace from r

sa1

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 Example
Example --
-- Step 4 ss sa1
Step 4 sa1
„ Set A = 0 in implication stack

1
0

sa1

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 Example
Example --
-- Step 5 ss sa1
Step 5 sa1
„ Forward implications: d = 0, X = 1

1
1
0
0
sa1

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 Example
Example --
-- Step 6 ss sa1
Step 6 sa1
„ Initial objective: set r to 1

1
1
0
0
sa1

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 Example
Example --
-- Step 7 ss sa1
Step 7 sa1
„ Backtrace from r again

1
1
0
0
sa1

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 Example
Example --
-- Step 8 ss sa1
Step 8 sa1
„ Set B to 1. Implications in stack: A = 0, B = 1

1
1
0
0
1 sa1

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 Example
Example --
-- Step 9 ss sa1
Step 9 sa1
„ Forward implications: k = 1, m = 0, r = 1, q = 1,
Y = 1, s = D, u = D, v = D, Z = 1
1
1
0
0
1 0 sa1 D 1
1 1
D
D
1

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 Backtrack
Backtrack --
-- Step 10 ss sa1
Step 10 sa1
„ X-PATH-CHECK shows paths s – Y and s–u–v–
Z blocked (D-frontier disappeared)
1
1
0
0
sa1

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 Step
Step 11 -- ss sa1
11 -- sa1
„ Set B = 0 (alternate assignment)

1
0

0 sa1

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 Backtrack -- ss sa1
Backtrack -- sa1
„ Forward implications: d = 0, X = 1, m = 1, r = 0,
s = 1, q = 0, Y = 1, v = 0, Z = 1. Fault not sensitized.
1
0
0
0
1
0 1 sa1
1
0
1
0
1

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 Step
Step 13 -- ss sa1
13 -- sa1
„ Set A = 1 (alternate assignment)

1
1

sa1

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 Step
Step 14 -- ss sa1
14 -- sa1
„ Backtrace from r again

1
1

sa1

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 Step
Step 15 -- ss sa1
15 -- sa1
„ Set B = 0. Implications in stack: A = 1, B = 0

1
1

0 sa1

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 Backtrack -- ss sa1
Backtrack -- sa1
„ Forward implications: d = 0, X = 1, m = 1, r = 0. Conflict:
fault not sensitized. Backtrack
1
0
1
0
0 1
1 sa1
1
0
1
0
1

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 Step
Step 17 -- ss sa1
17 -- sa1
„ Set B = 1 (alternate assignment)

1
1

1 sa1

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 Fault
Fault Tested
Tested -- Step
Step 18
18
„ Forward implications: d = 1, m = 1, r = 1, q = 0, s = D, v =
D, X = 0, Y = D

0
1
1
1
1 1 sa1 D
D
0

D
D
X

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 Example
Example (D-Algo)
(D-Algo)
¾ Primitive D-cube of Failure

D
sa1

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 Example
Example –– Step
Step 2
2
¾ Propagation D-cube for v

D
sa1 D
0

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 Example
Example –– Step
Step 2
2
¾ Forward & Backward Implications
0
1

1 1
1 D
1 sa1 D
0

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 Example
Example –– Step 3 ss sa1
Step 3 sa1
¾ Propagation D-cube for Z – test found!
0
1

1 1
1 D
1 sa1 D
0

D
D
1

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 Thank You

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