Formal Verification Based

Automated Approaches To SOC

DFT Logic Verification
Subir K. Roy
Rubin A. Parekhji
Texas Instruments
Bangalore, India
(Presenter : Sarveswara Tammali)
DAC User Track 2009 Poster Session

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 Motivation
Automate integration verifications of DFT
Logic and IPs towards
§ Cycle time reduction in verification by
minimizing usage of simulation based
SOC level verification requirements.
(Minimum 2X)
§ Si quality improvement by elimination of
all connectivity logic related bugs.
§ Deployment through common
infrastructure

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 Simulation vis-à-vis FV

§ Limitations of Simulation - Limited input test

vectors/ Manual test bench creation / Only end-to-
end bugs found – Larger debug time/ Larger
regression runtimes

§ Advantages of formal verification - No test bench

generation/ Comprehensive verification and
coverage/ Faster verification/ Properties are
generic/ Pin-points source of bug

§ Issues in FV – Intrinsic capacity limitations (1000

flops) => Rules out use of embedded
memory/memory models/IPs => Needs
partitioning and abstraction.

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 SOC DFT Logic Structure &
Different types of Integration
SOC DFT Logic Structure & Behavior
§ Canonical & Regular – Largely Independent of SOC
§ Reasonably generic nature of its interconnection
to rest of logic in SOC
Different Types of Integration
§ Static integration
§ Example : Pure connectivity
§ Dynamic integration
§ Temporal (Example : Pipeline registers in DPs)
§ Functional (Example : Switching between functional
and test modes)
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Case Study in Pure Connectivity Verification
SOC design complexity
§ Total IPs in the design = 42
§ Total Instances at top level = 117
§ Total integration bugs found by simulation = 180
§ Total effort = 6 months/8 persons (1136 man days)
§ Total PSL assertions for CBA sub-system = 6480
§ Total FV runtime = 180 minutes (3-4 secs/property)

Bug Classes Total/%

Results
Specification 18/10%
Pure 150/83.33% FV performance boost on the CBA
Connectivity Sub-system - 33X
FV performance boost on the whole
Non-IP SOC 12/6.66% SOC (extrapolated) - 38X
logic

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 Advantages of using FV for SoC Level
Connectivity checks
§ Modeling and property generation are simple
§ Allows concurrent efforts on RTL flow and
Connectivity verification flow
§ Can be used very early in the design cycle to
extract maximum benefit, as it does not require
RTL to be complete or functionally mature.
§ Can be carried out selectively on sub-systems
with high bug risks due to variability in choosing
IP configurations (Eg. Auto-generated
parameterized/configurable IPs)

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FV of Memory Data Path (Dynamic Integration - Temporal)

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Flow of Data between PBIST Controller
And Embedded Memories

Automated Flow

Command Line Arg Input_Info.xls

script

Generated
Properties &
FV env

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 FV of Testmode Entry Sequence
(Dynamic Integration - Functional)
SOC Top Level Verification Approach Through Partitioning

Icepick Top DFT

RST
nRESET Icepick Cntr
TDI

TCK FSM
TMS
Jtag Reg Mod

TM Reg
Decode
logic

CVL TM

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SOC MDP + Test Mode Entry Sequence Results
IPs/ Properties Pass Fail Block Level / Proper- Average CPU
Subsystems ties Time
Connectivity Flip-
1 148 144 4 Flops [mins.]
Verification
2 68 67 1
ICEPick IP 61 170 38
3 1344 1312 32
JTAG Regs 10 90 20
4 158 155 3
5 1363 1324 37 Connectivity 14 2 3

6 48 46 2
7 670 660 10 § In one SoC MDP, due to a
wrongly placed inverter, write-
8 172 168 4
enable pin of a memory was not
9 38 5 33
being de-asserted properly –
10 (Hard IP)* 29 21 8
caught by de-assertion property
11 (Hard IP)* 29 4 25
12 (Hard IP)** NA NA NA WZ0

13 (Hard IP)** NA NA NA
Mux Reg Mux Reg
14 (Hard IP)** NA NA NA Wrongly twen
Placed
Total 4067 3906 161 Inverter ‘1’ ‘1’ Should be
* - Only Pure Connectivity Checks here
RGS
** - Connectivity information unavailable
CSR
during first iteration of DFT FV

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Automated DFT FV Regression Flows
DFT logics to be verified Types of DFT checks to be performed
(Connectivity/MDP/Safe Val/TME/TAM etc.)

FV
Regression
IFV IFV IFV IFV Runs

Individual
Run
Reports

Consolidated
Regression
Report
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 Summary
§ For standardized SOC connectivity and DFT
logic architecture formal verification can be
easily automated and extremely efficient –
Enormous Reduction in Verification Cycle Time
+ High Quality Verification.
§ Person month reduction to complete DFT FV
after deployment of automation :
§ For Large Sized SOCs --- Factor of 4
§ Only 1 resource needed.
[Acknowledgement : Thanks to Bijitendra Mittra, Amit Roy, Supriya
Bhattacharjee, Deepanjan Roy and Lopamudra Sen from Interra India
Private Limited, Bangalore]

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