@include "cairo-defines.

vh"
module cairoOtpStateMachine
(
input wire clk
, input wire resetn
, input wire [9:0] cairoPhase
, input wire cairoJtagMfgEnable
, output wire otpTestReady
, input wire otpTestStart
, input wire [1:0] otpTestMode
, output reg otpTestDone
, output reg otpTestSuccess
, input wire [15:0] regAddr
, input wire [3:0] regMask
, input wire regRead
, output reg [31:0] regReadData
, output reg regReadDone
, input wire regWrite
, input wire [31:0] regWriteData
, output reg regWriteDone
, output reg regSlaveError
, output reg [16:0] xpmA
, output reg xpmCeb
, output reg xpmCle
, output reg xpmCpumpen
, output reg xpmDin
, output reg xpmDle
, output reg xpmPgmen
, output reg xpmReaden
, output reg xpmRstb
, output reg xpmSeltdec
, output reg xpmWeb
, input wire [31:0] xpmD
);
@Wires ;
wire cairoPhaseEnable;
@Regs ;
@Waive no_sink otpTestMode;
@Waive no_sink regMask;
@Waive no_sink regWriteData;

// WIDTH PARAMETER
parameter XPM_STATE_CTR_WIDTH = 11;

// smart Algoritham parameters

parameter XPM_NP1 = 4;
parameter XPM_NP2 = 16;
// counter Initialization parameter

parameter XPM_BIT_CTR_INIT = 5'b0;

parameter XPM_BIT_CTR_FULL = 5'h1F;
parameter XPM_BL_ADDR_CTR_INIT = 12'b0;
parameter XPM_BL_ADDR_CTR_FULL = 12'hFFF;

// Functional Parameters
parameter T_CSRST = 206; // 1000
parameter T_RW = 5; // 20
parameter T_RS = 5; // 20
parameter T_RSRD = 5; // 20
parameter T_READEN = 210; // 1000
parameter T_ACC = 10; //45
parameter T_RWH = 105; //500
parameter T_CEW = 5; //20
parameter T_REW = 5; //20
parameter T_AS = 6; //25
parameter T_DS = 5; //20
parameter T_DLES = 5; //20
parameter T_WWL = 5; //20
parameter T_DH = 5; //20
parameter T_DLEH = 5; //20
parameter T_WWH = 11; //50
parameter T_DPD = 5; //20
parameter T_PES = 206; //1000
parameter T_CPS = 415; //4000 //800
parameter T_PW = 1000; //1050 //5000 //5000/4.76
parameter T_CPH = 310; //1500
parameter T_PGMVFY = 10; //45
parameter T_PEH = 206; //1000
parameter T_PGMAS = 21; //100
// test Parameters
parameter T_RSCLE = 5; //20
parameter T_TWS = 6; //25
parameter T_CLES = 5; //20
parameter T_CLEH = 5; //20
parameter T_TWH = 7; //24
parameter T_CPES = 21; //100
parameter T_CPRD = 206; //1000
parameter T_RDCP = 21; //100
parameter T_CDCD = 5; //20
parameter T_AAC = 310; //1500
parameter T_RRC = 525; // 2500 as per spec 300 but taken 500
parameter T_RDES = 21; // 100
parameter T_CPPW = 1645; // 8000
parameter T_PGM = 2055; //10000
parameter T_CDD = 5; //20
parameter T_READENT = 210; //1000
parameter T_ACCT = 10; //45
parameter T_BCREADEN = 520; //2500
parameter T_BCACC = 310; //1500

always@(posedge clk, negedge resetn) begin

if(!resetn) begin
xpmCeb <= 1'b1;
xpmRstb <= 1'b1;
xpmWeb <= 1'b1;
xpmCle <= 1'b0;
xpmCpumpen <= 1'b0;
xpmDin <= 1'b0;
xpmDle <= 1'b0;
xpmPgmen <= 1'b0;
xpmReaden <= 1'b0;
xpmSeltdec <= 1'b0;
xpmA[16:0] <= 17'b0;
end
else begin
xpmCeb <= xpmCebNext;
xpmRstb <= xpmRstbNext;
xpmWeb <= xpmWebNext;
xpmCle <= xpmCleNext;
xpmCpumpen <= xpmCpumpenNext;
xpmDin <= xpmDinNext;
xpmDle <= xpmDleNext;
xpmPgmen <= xpmPgmenNext;
xpmReaden <= xpmReadenNext;
xpmSeltdec <= xpmSeltdecNext;
xpmA[16:0] <= xpmANext[16:0];
end
end

always@(posedge clk, negedge resetn) begin

if(!resetn) begin
stateCtr[XPM_STATE_CTR_WIDTH-1:0] <= {XPM_STATE_CTR_WIDTH{1'b0}};
end
else if(stateCtrInit) begin
stateCtr[XPM_STATE_CTR_WIDTH-1:0] <= {XPM_STATE_CTR_WIDTH{1'b0}};
end
else if(stateCtrIncr) begin
stateCtr[XPM_STATE_CTR_WIDTH-1:0] <= stateCtr + {{XPM_STATE_CTR_WIDTH-1{1'b0}},1'b1};
end
end
always@(posedge clk, negedge resetn) begin
if(!resetn) begin
otpTestInProgress <= 1'b0;
otpControllerInTestMode <= 1'b0;
end
else begin
otpTestInProgress <= otpTestInProgressNext;
otpControllerInTestMode <= otpControllerInTestModeNext;
end
end

// declaring the test register values respect to particular test

always@(posedge clk ,negedge resetn) begin
if(!resetn) begin
testword[16:0] <= 17'h00000;
end
else if(otpTestInProgress) begin
case(otpTestMode)
2'b00 : begin testword[16:0] <=17'h00000;
end
2'b01 : begin testword[16:0] <=17'h00028;
end
2'b10 : begin testword[16:0] <=17'h00068;
end
2'b11 : begin testword[16:0] <=17'h00004;
end
endcase
end
else begin
testword[16:0] <= 17'h00000;
end
end

assign cairoPhaseEnable = (cairoPhase == CAIRO_PHASE_UNTRIM || ((cairoPhase ==

CAIRO_PHASE_PERSO1) && cairoJtagMfgEnable));

assign otpTestReady = cairoPhaseEnable && ~otpTestInProgress;

always@(posedge clk, negedge resetn) begin

if(!resetn) begin
bitCtr[4:0] <= XPM_BIT_CTR_INIT;
blAddrCtr[11:0] <= XPM_BL_ADDR_CTR_INIT;
xpmBuffer[31:0] <= 32'b0;
xpmProgramError <= 1'b0;
npCtr[4:0] <= 5'b0;
testReadmode <= 1'b1;
testFail <= 1'b0;
testFail1 <= 1'b0;
testFail2 <= 1'b0;
testFailure <= 1'b0;
testSelectOut <= 1'b0;
testWriteData[31:0] <= 32'd0;
testReadData[31:0] <= 32'd0;
xpmTestBuffer[31:0] <= 32'd0;
testProgramError <= 1'b0;
testProgramDone <= 1'b0;
wrTestAddrCtr[4:0] <= XPM_BIT_CTR_INIT;
end
else begin
bitCtr[4:0] <= bitCtrNext[4:0];
blAddrCtr[11:0] <= blAddrCtrNext[11:0];
xpmBuffer[31:0] <= xpmBufferNext[31:0];
xpmProgramError <= xpmProgramErrorNext;
npCtr[4:0] <= npCtrNext[4:0];
wrTestAddrCtr[4:0] <= wrTestAddrCtrNext[4:0];
testFail <= testFailNext;
testFail1 <= testFailNext1;
testFail2 <= testFailNext2;
testFailure <= testFailureNext;
testSelectOut <= testSelectOutNext;
testWriteData[31:0] <= 32'hFFFFFFFF;
testReadData[31:0] <= testReadDataNext[31:0];
testReadmode <= testReadmodeNext;
testProgramDone <= testProgramDoneNext;
testProgramError <= testProgramErrorNext;
xpmTestBuffer[31:0] <= xpmTestBufferNext[31:0];
end
end

always@(posedge clk, negedge resetn) begin

if(!resetn) begin
state[XPM_STATE_REG_WIDTH-1:0] <= XPM_STATE_IDLE;
stateFun[XPM_STATE_FUN_REG_WIDTH – 1:0] <= XPM_STATE_FUN_IDLE;
stateTest[XPM_STATE_TEST_REG_WIDTH-1:0]<=XPM_STATE_TEST_IDLE;
end
else begin
state[XPM_STATE_REG_WIDTH-1:0] <= stateNext[XPM_STATE_REG_WIDTH-1:0];
stateFun[XPM_STATE_FUN_REG_WIDTH-1:0] <= stateFunNext[XPM_STATE_FUN_REG_WIDTH - 1:0];
stateTest[XPM_STATE_TEST_REG_WIDTH-1:0]<= stateTestNext[XPM_STATE_TEST_REG_WIDTH – 1:0];
end
end
always@(*) begin
stateNext[XPM_STATE_REG_WIDTH-1:0] = state[XPM_STATE_REG_WIDTH-1:0];
regReadDone = 1'b0;
regReadData = 32'b0;
regWriteDone = 1'b0;
regSlaveError = 1'b0;
otpTestDone = 1'b0;
otpTestSuccess = 1'b0;
otpControllerInTestModeNext = 1’b0;
otpTestInProgressNext = 1’b0
case(state)
XPM_STATE_IDLE: begin
if(otpTestReady && otpTestStart) begin
otpControllerInTestModeNext = 1'b1;
otpTestInProgressNext = 1'b1;
// stateCtrInit = 1'b1;
stateNext = XPM_STATE_TEST_CMD;
end
else if(regRead | regWrite) begin
// stateCtrInit = 1'b1;
stateNext = XPM_STATE_FUNCTIONAL;
end
end
XPM_STATE_FUNCTIONAL: begin
stateFunStart = 1’b1;
regReadUp = regRead;
regWriteUp = regWrite;
regWriteUpData = regWriteData;
regUpAddr = regAddr;
if(stateFunDone == 1’b1) begin
regReadDone = regReadUpDone;
regReadData = regReadUpData ;
regWriteDone = regWriteUpDone;
regSlaveError = regSlaveUpError;
stateNext = XPM_STATE_IDLE;
stateFunStart = 1’b0;
end
end

XPM_STATE_DFT_TEST: begin
stateTestStart = 1’b1;
if(stateTestDone == 1’b1) begin
otpTestDone = otpTestUpDone;
otpTestSuccess = otpTestUpSuccess;
stateTestStart = 1’b0;
stateNext = XPM_STATE_IDLE;
end
end
 default: begin stateNext = XPM_STATE_IDLE; end
endcase
end

always@(*) begin
stateFunNext[XPM_STATE_FUN_REG_WIDTH-1:0] <= stateFun[XPM_STATE_FUN_REG_WIDTH - 1:0];

end

always@(*) begin

bitCtrNext[4:0] = bitCtr[4:0];
xpmBufferNext[31:0] = xpmBuffer[31:0];
xpmProgramErrorNext = xpmProgramError;
npCtrNext[4:0] = npCtr[4:0];
blAddrCtrNext[11:0] = blAddrCtr[11:0];
wrTestAddrCtrNext[4:0] = wrTestAddrCtr[4:0];
xpmCebNext = xpmCeb;
xpmRstbNext = xpmRstb;
xpmWebNext = xpmWeb;
xpmCleNext = xpmCle;
xpmCpumpenNext = xpmCpumpen;
xpmDinNext = xpmDin;
xpmDleNext = xpmDle;
xpmPgmenNext = xpmPgmen;
xpmReadenNext = xpmReaden;
xpmSeltdecNext = xpmSeltdec;
xpmANext[16:0] = xpmA[16:0];

stateCtrInit = 1'b0;
stateCtrIncr = 1'b0;

otpControllerInTestModeNext = otpControllerInTestMode;
otpTestInProgressNext = otpTestInProgress;
testFailureNext = testFailure;
testFailNext = testFail;
testFailNext1 = testFail1;
testFailNext2 = testFail2;
testSelectOutNext = testSelectOut;
testReadDataNext[31:0] = testReadData[31:0];
testProgramDoneNext = testProgramDone;
testProgramErrorNext = testProgramError;
testReadmodeNext = testReadmode;
xpmTestBufferNext[31:0] = xpmTestBuffer[31:0];