June 17, 2004 19:46 Research Publishing: Trim Size: 8.50in x 11.

00in (IEEE proceedings) ieee-emc08:P291

Methods for Circuit-Based Automotive EMC

Simulation incorporating VHDL-AMS Models
Florian Frank1, Martin L. Zitzmann2 , Gernot Steinmair2 , Robert Weigel1
1
Institute for Electronics Engineering, University of Erlangen-Nuremberg, 91058 Erlangen, Germany
2
BMW Group, 80788 Munich, Germany
Email: frank@lte.e-technik.uni-erlangen.de

Solution of
Abstract— This paper provides an overview of several novel Maxwell’s equations
approaches to enhance today’s automotive EMC simulation.
The introduction of fast and efficient modeling and solving PEEC-
techniques for models of passive PCB traces leads to an improved Mesh
PEEC- Model
computational performance. Additionally, the development of a Geometry PEEC data
Parameter SLSimTM
methodology enabling co-simulations of VHDL-AMS models of Model Mesher
Extraction
active IC devices yields more accurate numerical results. After CAD Discretization
the explanation of these enhancements, the proposed simulation
flow and analysis methods are shown by means of numerical Sub-
results from a typical automotive application. circuits
Simulator
Interface
I. I NTRODUCTION Circuit-
File
The complexity of problems arising in automotive elec-
tromagnetic compatibility (EMC) analysis is increasing with
the number of electronic systems assembled in modern cars. VHDL-
AMS SMASH TM
Components containing integrated circuits (ICs) and controlled Models
sensors and actuators are influencing factors for the EMC
quality. Disturbances like electronic noise on power and Fig. 1. Circuit-based EMC simulation workflow. The gray boxes show steps
ground planes, which is known as simultaneous switching that can be improved using the methodologies presented in this paper.
noise (SSN), are transferred via the cable harnesses to the
whole system. To avoid cost and time intensive redesign
cycles in the car development process, numerical simulation In recent years an alternative method of modeling active
techniques are challenged to help identify and solve EMC devices based on VHDL-AMS [3], a hardware description
relevant problems in the early design stage. language for analog, digital, and mixed-signal applications,
For EMC analysis of automotive systems including the is going popularly. Using this language it becomes possible
system level, the component level as well as the IC level, to generate models at any kind of abstraction level, i.e. parts
several different modeling and simulation techniques are re- based on physical equations and parts based on pure functional
quired. Whereas cable harness simulations are based on a descriptions can be combined within one single model. Thus,
2D TL (transmission line) approach, for PCB simulations the models allowing accurate analysis results within a short sim-
3D PEEC (partial element equivalent circuit) method [1] is ulation time can be generated. In order to incorporate VHDL-
applied. The PEEC method enables a circuit representation AMS models into the already existing SPICE-based EMC
of the electric field integral equation (EFIE) and therefore a simulation flow, a methodology has been developed enabling
connection between the field domain and the circuit domain. the co-simulation between SPICE and VHDL-AMS.
Problems arise as soon as active devices, which are the main This paper is organized as follows. Section II gives an
sources of the above mentioned disturbances, have to be overview of the enhanced EMC modeling and simulation
modeled in order to incorporate them into circuit-based EMC process. In the next section, a short introduction to the PEEC
simulations. Due to their nonlinear behavior, it is not sufficient method is given. Furthermore, it is explained how the solu-
to use simple equivalent circuit descriptions consisting of tion process in PEEC-based circuit-simulations can be sped
voltage and current sources and lumped RLC-components up using hierarchical methods combined with special solver
to achieve an accurate analysis result. In the past, the most techniques. The functionality of a simulator interface program,
common way was to use IBIS (input/output buffer information which forms the basis of the newly developed SPICE-VHDL-
specification) [2] to describe the clamping behavior of active AMS-co-simulation methodology, is briefly explained in sec-
ICs. Unfortunately IBIS models show a significant sensitivity tion IV. In section V numerical results based on a typical
to the attached load and hence can be used within a quite automotive application are given and the last section concludes
narrowly bounded range of loading conditions only. the paper.

2008 Asia-Pacific Sympsoium on Electromagnetic Compatibility &

20 19th International Zurich Symposium on Electromagnetic Compatibility, 19–22 May 2008, Singapore
June 17, 2004 19:46 Research Publishing: Trim Size: 8.50in x 11.00in (IEEE proceedings)
2008 Asia-Pacific Sympsoium on Electromagnetic Compatibility, 19–22 May 2008, Singapore
II. EMC M ODELING AND S IMULATION P ROCESS
Using the methodologies and enhancements briefly intro-
duced in the following sections, a fast and efficient EMC
modeling and simulation process becomes possible. The im-
proved analysis workflow as shown in Fig. 1 can be ab-
stracted as follows: Before an EMC simulation run can be
started, the 3D PEEC models of the PCB traces have to
be generated. Therefore, a discretization of the geometrical
design is necessary, building the basis for the numerical model
computation. By solving Maxwell’s equations, the PEEC pa-
rameter extraction (modeling) can be accomplished, resulting
in so-called (R, L, C) PEEC models. Together with optional
SPICE subcircuits and VHDL-AMS models, SLSimTM solves
the network equations in the time domain in co-operation with
SMASH TM.
III. PEEC- BASED C IRCUIT S IMULATION
A. PEEC Model Derivation
The 3D PEEC method allows the interpretation of con-
ducting structures including dielectrics by a linear network of
basic electrical elements. This integral equation based element
method (BEM) approach is used for modeling of complex
conducting structures like PCB traces and interconnects and
leads to dense system matrices in general. The PEEC modeling
process starts with a discretization of the conducting medium
into volume and surface cells, which is necessary to approxi-
mate current and charge densities. Afterwards, the method of
moments (MoM) [4] is applied together with Galerkins method
[5] to the EFIE to determine the equivalent circuit components.
A complete theoretical derivation of the PEEC method is given
in [1].
B. Fast and Efficient Extraction of Parasitic Effects
A fast and accurate computation of matrix elements repre-
sents one major issue to implement an efficient simulation
process. This is especially important for parasitic matrices
originating from electromagnetic boundary integral equation
(BIE) approaches such as the PEEC method. BEM-based
matrices as inductance matrices and potential coefficient ma-
trices
 are dense, in general. These matrices comprise n =
O h−2 degrees of freedom (DOF) for geometric meshing
with meshsize h thus exhibiting O h−4 matrix entries [6]
in 2D. Both the TD and the FD analysis need to compute
large numbers of interactions between basis functions for each
and every simulation step, leading to enormous CPU time and
memory requirements. This can form severe limitation to the
number of DOF in practical relevant problems. Fast methods
are necessary to reduce the complexity of basic arithmetic
operations.
Hierarchical matrices (“H-matrices”) help to represent the
matrix as a decomposition of matrix subblocks. They provide
a purely mathematical approach to describe dense matrices
by so-called data-sparse matrices. Based on this kind of
description, it is possible to apply approximative algorithms
for matrix arithmetic with almost optimal complexity.
21
ieee-emc08:P291
In H-matrix-based model computation, a fast and accurate
approximation of a parasitics matrix is aspired. Controlled by
a suitable heuristics only required matrix entries have
 to be
computed, leading to a complexity reduction from O n2 to
O (nlogn) [7]. Furthermore, H-matrices provide additional
advantageous features to enhance efficiency and flexibility,
compared to fast multipole methods (FFM) [8], [9].
C. Hierarchical Matrices Based Solvers for PEEC
Utilizing iterative methods to obtain an accurate solution
of Ax = b inevitably leads to square complexity w.r.t. CPU
time and memory requirements even for sparse matrices. A
reduction to almost linear complexity can be accomplished
by approximating the PEEC-based system matrix A by a
data-sparse H-matrix AH . The approximative solution x̃ of
the system AH x = b must fulfill the accuracy condition
x − x̃  ≤ ε for a given ε > 0. Based on the formatted
H-matrix arithmetic [10], efficient preconditioning techniques
can be realized. Implementation issues for an appropriate
matrix setup and suitable preconditioning for an efficient
PEEC-based circuit simulation have to be taken into account
[11].
IV. I NTERFACE FOR
SPICE-VHDL-AMS-C O -S IMULATION
In order to improve the results of EMC simulations, an
interface has been developed enabling co-simulations between
SPICE and VHDL-AMS. Using this interface, it becomes
possible to replace simple equivalent circuits of non-linear
active devices with more realistic VHDL-AMS models. The
interface connects the SPICE-based circuit simulator SLSimTM
[12], which is part of a special EMC toolbox providing the
modeling and solving strategies mentioned above, and the
VHDL-AMS simulator SMASH TM [13].
The functionality of the interface program and the according
co-simulation flow can be abstracted as follows: SLSimTM,
which is used as master simulator, loads the SPICE netlist
and subsequently all required SPICE models. Thereafter, the
simulator SMASH TM is invoked as slave and linked into the
running master process. Finally, all additional VHDL-AMS
models are loaded and the operating point analysis as well as
the transient time domain simulation can be carried out.
A. Connection of SPICE and VHDL-AMS Models
During a mixed-language simulation, i.e., an analysis of a
combination of SPICE and VHDL-AMS models, both sim-
ulators have to compute solutions of their internal systems
of ordinary differential-algebraic equations (DAEs) indepen-
dently of each other. Nevertheless, it is necessary to make the
calculated values available for the other simulator. Therefore
special interconnecting nodes have been introduced allowing
for the exchange of voltage and current values.
These interconnecting nodes are handled by SLSimTM as
voltage controlled current sources, whose current values are
calculated by the external VHDL-AMS simulator. The latter
treats these nodes as special voltage sources, whose voltage
June 17, 2004 19:46 Research Publishing: Trim Size: 8.50in x 11.00in (IEEE proceedings) ieee-emc08:P291

19th International Zurich Symposium on Electromagnetic Compatibility, 19–22 May 2008, Singapore

values are determined and are only allowed to be changed by 0

the SPICE simulator. A drawing of one of these interconnect-
ing nodes is shown in Fig. 2. -20

|S11 | (dB)
SPICE VHDL-AMS -40
IT
-60 Measurement
IT = f (VT )
Simulation
VT
VT -80 4
VT 10 105 106 107 108 109 1010
IT Frequency (Hz)

0
Fig. 2. Interconnecting node of the SLSimTM part (white box) and the

SMASH TM part (gray box) of a mixed-language simulation model. Whereas
the former consists of a voltage controlled current source the latter consists
of a voltage source.
B. Transient Time Analysis
During a transient time analysis, the master simulator is
responsible for the adaptive time step control. This means
that SLSimTM determines the step widths and thus, the time
instances at which a corresponding analog solution is calcu-
lated as well as the synchronization between the simulator
parts is carried out. In cases where one or both simulators
could not determine a corresponding analog solution of their
internal systems of DAEs the step width will be reduced. A
recalculation of the analog solution and a reduction of the
step width, respectively, is also required if the VHDL-AMS
simulator is not able to synchronize the logic simulator part
with its analog one due to logic events. This synchronization
is required after every calculation of an analog solution point.
V. N UMERICAL R ESULTS
For both simulation and measurement purposes an auto-
motive specific demonstrator board is considered. The board
consists of four layers with dielectric medium FR4 and stems
from a typical application in automotive industry. The fully
assembled board contains a microcontroller and two power
drivers which are used to switch DC motors and lights, respec-
tively. Measurements are possible via provided connectors.
The investigated design is part of a research project named
MISEA [14].
To show the functionality of the enhancements made to
the EMC simulation process and thus the correspondence
of measurement and simulation results, a reluctance-based
model [11] of a relevant signal trace is considered. A suitably
chosen meshsize guarantees the validity of the model in the
TD as well as in the FD. The good accordance of physical
measurements and the simulation results obtained with the
generated PEEC model is shown in Fig. 3. Both model
extraction and simulation in the conventional case require a
large amount of time. Therefore, the total analysis process
cannot be carried out in less than one or two days. A first ap-
proach for simulation acceleration can be enabled by applying
simple matrix sparsification by truncation [11]. Although the
|S21 | (dB)
-20
-40
Measurement
Simulation
-60 4
10 105 106 107 108 109 1010
Frequency (Hz)
Fig. 3. Comparison between simulation and measurement results. Due to
symmetry reasons only the magnitudes of the scattering parameters S11 and
S21 are shown.
complexity of the modeling process remains almost constant,
the simulation can be accelerated by a factor of ≈ 5.
Even if a truncation enables a simple sparsification method,
it is not efficient enough to implement accurate simulations for
large industrially relevant problems. A further enhancement
can be accomplished by accelerating model extraction as
well as simulation using hierarchical techniques. Applying H-
matrix-based computation of parasitics, a modeling speed-up
by an additional factor ≈ 7 can be achieved. Compared to
conventional techniques an increased modeling accuracy can
be obtained. A gain with a factor ≈ 20 can be achieved con-
cerning storage requirements by using the H-matrix storage
format instead of the conventional coordinate sparse matrix
storage format. The simulation process can be accelerated up
to a factor of ≈ 10 by applying an algebraic multigrid (AMG)
solver [11].
Besides the improvements concerning modeling and anal-
ysis speed, further enhancements concerning the accuracy of
the simulation results can be achieved. Therefore, some of the
active devices that are assembled on the demonstrator board
will be included in the EMC simulation using accurate VHDL-
AMS models. As an example, one of the two power drivers
is used. Thus the executed co-simulation includes the VHDL-
AMS model of this device as well as the PEEC model of the
connected power trace. Other devices like the load and the
power supply are modeled using SPICE equivalent circuits.
The chosen power driver is the high-side power switch
BTS5440 of Infineon [15]. This device usually is used to
switch all kinds of resistive, inductive and capacitive loads.
In Fig. 4 it was used to switch a resistive load with R =

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June 17, 2004 19:46 Research Publishing: Trim Size: 8.50in x 11.00in (IEEE proceedings) ieee-emc08:P291

2008 Asia-Pacific Sympsoium on Electromagnetic Compatibility, 19–22 May 2008, Singapore

5 Ω. This figure compares the current at the output pin of 14.5

the co-simulation with the corresponding pure VHDL-AMS 14 VAMS Model
simulation and with a similar SPICE simulation (IBIS model IBIS Model
13.5

Vbat (V)
of the BTS5440). In the pure VHDL-AMS simulation, only
VHDL-AMS models and the SMASH TM simulator were used. 13
From the figure it is obvious that, as expected, no differences 12.5
between the curves exist. It should be evident that the co-
12
simulation takes a longer execution time than the pure VHDL-
AMS analysis and the SPICE simulation. This is due to the fact 11.5
0 0.1 0.2 0.3 0.4 0.5
that in the co-simulation two separate simulators are involved. Time (ms)
12
3
10
2.5 8
Current (mA)

2 6
1.5
1 VAMS Sim.
Co-Sim.
0.5 IBIS Sim.
0 0
0 0.1 0.2 0.3 0.4 0.5
Time (ms)
Fig. 4. Comparison of the current at the output pin of the high-side power
switch. In all simulations a resistive load with R = 5 Ω was used.
In Fig. 5 the simulation results of the co-simulation includ-
ing the PEEC model of the PCB power trace as well as an
equivalent SPICE circuit of the cable harness are shown. The
BTS5440 model was terminated with a serial connection of
a 6.676 Ω resistor and a 25 μH inductor. In the figure the
simulation results of the battery voltage and the output voltage
are compared to a corresponding analysis in which the VHDL-
AMS model was replaced by the IBIS model of the power
driver. The differences between the depicted curves are caused
by the significant load sensitivity of the IBIS model. This
was generated using simulations of the original VHDL-AMS
model, terminated by the resistive load with R = 5 Ω.
VI. C ONCLUSIONS
In the course of this paper, fast and accurate modeling
and simulation techniques have been introduced and a new
developed co-simulation methodology based on two differ-
ent simulators has been presented. The BEM-based PEEC
modeling approach proved to be useful for the analysis of
the electromagnetic behavior of 3D interconnects and traces
on PCBs. A speed increase of the model generation and
the simulation process could be obtained using hierarchical
matrices combined with special iterative solver strategies. In
addition, the simulation results could be further improved by
replacing simple equivalent circuit models of active devices
assembled on PCBs by more accurate VHDL-AMS models.
ACKNOWLEDGMENT
This work was undertaken in the course of the project
MISEA [14], supported by the Bavarian Research Foundation
(Bayerische Forschungsstiftung).
Vout (V)
4
2 VAMS Model
0 IBIS Model
-2
0.1 0.2 0.3 0.4 0.5
Time (ms)
Fig. 5. Comparison of results of simulations including the active device
BTS5440, a PEEC model, and an equivalent circuit model of the cable
harness. In one simulation the high-side power switch was represented using
a simple IBIS model and in the other a more accurate VHDL-AMS model
was used.
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