Reg. No.

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Question Paper Code : 98076

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M.E. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010

First Semester

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VLSI Design

VL 9211 — DSP INTEGRATED CIRCUITS

(Common to M.E. — Applied Electronics)

(Regulation 2009)

Time : Three hours Maximum : 100 Marks

Answer ALL questions

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PART A — (10 × 2 = 20 Marks)
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1. What is abstraction?

2. List main features of a structured design methodology.

3. What are parasitic oscillations?

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4. What is the use of DCT?

5. What are the properties of IIR filter designed using impulse invariant
techniques?

6. A multirate system is required for converting the sampling rate from 48 K

samples to 42.1 K samples. What are the interpolation factor, decimation
factor to be used?
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7. What is separator Register?

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8. What is MAG?

9. What is redundancy factor?

10. What are the fundamental operations in RNS signal processing?

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 PART B — (5 × 16 = 80 Marks)

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11. (a) (i) Describe a systematic partitioning technique for the design of a
complex DSP system. Also give a motivation for the chosen

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partitioning technique. (8)
(ii) Describe the different types of transformations between two
adjacent levels of abstraction in the design process. Also describe
different types of transformations within a design level. (8)
Or

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(b) Explain the following VLSI process technologies :
(i) Bulk CMOS technology. (8)
(ii) Bipolar Technology. (4)
(iii) GaAs Based Technology. (4)

12. (a) Explain Nyquist sampling theorem and also how to select sampling
frequency for sampling analog signal.
Or

(b)

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Find radix 2, DIT, FFT of the sequence x(n ) = {1, 1, 1, 1, 2, 2, 2, 2} .
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13. (a) Determine the impulse response coefficients of a digital filter whose
frequency response is given by
0 for | w | < 0.85 π
( )
H e jw = 
1 for 0.85π <| w | < π
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Or

(b) What is Round off noise? Explain the method to measure round off noise
in digital system.

14. (a) Explain in detail the random, linear and regular topology architectures
models used in the synthesis of VLSI layout.
Or

(b) Derive design W1 from design F using transformations such as edge

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reversal, associativity slow-down, retiming and pipelining.

15. (a) Explain the layout of Bit-serial architecture of VLSI circuits.

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Or

(b) Design an FFT processor for computing the DFT.

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