library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Reloj is

Port ( clk : in STD_LOGIC;

led : out integer range 0 to 255);

end Reloj;

architecture Behavioral of Reloj is

signal cont1: integer range 0 to 50000000;

signal cont2: integer range 0 to 255;

begin

--Contador 1

cont1<=0 when cont1=50000000 else

cont1 + 1 when clk'event and clk='1';

--Contador 2

cont2<= cont2+1 when cont1=49999999 and clk'event and clk='1';

led<=cont2;

end Behavioral;