library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use ieee.numeric_std.all;

entity contador is

Port(

frek : in std_logic;

clk : in STD_LOGIC;

bin: out std_logic_vector (13 downto 0));

end contador;

architecture Behavioral of contador is

signal cont1: integer range 0 to 50000000; --f1

signal cont2: integer range 0 to 9999; --Cuenta

signal aux: integer range 0 to 50000000;

begin

cont1<=0 when cont1=50000000 and frek='0' else

0 when cont1=500000 and frek='1' else

cont1 + 1 when clk'event and clk='1';

aux<=49999999 when frek='0' else

499999;

--Contador

cont2<= 0 when cont2=9999 else

cont2+1 when cont1=aux and clk'event and clk='1';

bin<=std_logic_vector(to_unsigned(cont2,14));

end Behavioral;