Algorithm files based.m .

mdl MATLAB SIMULINK

development file

SIMULINK.mdl

Simulation

Automatic gemeration of
VHDL code

HDL test bench VHDL RTL ( .vhd)

Hardware simulation ISIM XILINX synthesis flow

Synthesis
Download to FPGA XILINX CHIPSCOPE PRO
(a) (b) (c)

(d) (e) (f)

(g) (h) (i)

(j) (k) (l)

(a) (b) (c)