Saurabh singh poswal Email: saurabhposwal12345@gmail.

com
G-45 meenakshipuram contact:8979295201
meerut
CAREER OBJECTIVE:
To be involved in work where I can utilize my skills effectively in VLSI Domain
that offers me numerous avenues for personal and professional growth.
TECHNICAL SKILLS:
HDL : Verilog.
HVL : System Verilog.
Methodology : UVM.
Protocols : APB,SPI.
EDA Tools : Xilinx’s ISE Design, Questasim.
Programming languages : C,C++.
Scripting Language : Linux (Shell Scripting).
Operating systems : Windows, Linux.

EDUCATIONAL QUALIFICATION

ACADEMICS BOARD/ YEAR PERCENTAGE

UNIVERSITY
B.Tech (ELECTRONICS
INSTRUMENTATION) UPTU 2015 67%
INTERMEDIATE CBSE 2011 81%
HIGH SCHOOL CBSE 2009 75%

ACADEMIC PROJECT:

Synchronous FIFO Designing In Verilog

Implemented memory and accomplished read and write operation in Verilog. Developed
Verilog module of this project in Xilinx and Questasim. Developed test bench using
Verilog in Xilinx and Questasim and verified the output using waveform and transcript
with different cases.

FIFO: Implemented Verification Environment Using System Verilog

Implemented complete verification environment in System Verilog. In this

verification Environment, covered the following components
Design under
 Test Interface
Packet
Generator
Collector
Monitor
Scoreboard
FIFO: Implemented Verification Environment Using UVM

Implemented complete verification environment using UVM. In this verification

environment covered the following components
Design Under
Test Interface
Transaction(packet)
Sequence
Sequencer
Driver
Monitor
Agent
Scoreboard
Environment
Test
Top

CERTIFICATIONS:

PG Diploma course in VLSI chip design and verification from Silicon2software

Technologies.

CO-CURRICULAR ACTIVITIES:

 .Participated in Robotics competition conducted by IIT khadagpur.

 Participated in Volleyball tournament .

PERSONAL DETAILS:

Date of Birth : 31-JULY-1993

Languages Known : English, Hindi,
Area of interest :VLSI