EC#20— ARSITEKTUR KOMPUTER LANJUT TUGAS-5 CHAPTERS PIPELINING AND SUPERSCALAR TECHNIQUES SOAL-SOAL TENTANG SUPERSCALAR AND SUPERPIPELINE DESIGN ARWIN NIM. 232.06 008 Institut Teknologi Bandung MAGISTER TEKNIK ELEKTRO- ‘SEKOLAH TINGGI ELEKTRONIKA DAN INFORMATIKA INSTITUT TEKNOLOGI BANDUNG. 2006Problem 6.1 — Consider the execution of a program of 15000 instructions by a linear pipeline processor with « dock rate of 25 Mz, Assume that the instruction pipeline has five stages and that ‘one instruction is issued per clock eyde. The penalties dur to branch instructions and out-of soquence executions are ignored 4. Caleulote the speedup factarusing this pipeline to exceute the program as compared with the use of an equivalent nonpipelined processor with an equal amout of flow-through delay. 1b. Whatare the efficiency and throughput of this pipelined processor’? Information we get are m= 15,000 instructions or tasks. ef =2S Mit: © aS stages, © L-isated processor. ‘The Speatup (S,) Efficiency, (E,), and Throughput (#7) factors are Take af ST Fes (ne Ta) a” (15,000)(25) _ 989 ka(n=1) *54(15,000—1) ea, {15,000)(5) 375,000 *54(15,000—1) 15,008 75,000, = 24,99. MIPS “15.008 =4,999 Arvin. 2320600802005Problem 6.2 — Study the DEC Alpha architecture in Example 6.13, find more information in the DEC Alpha handbook, apd then answer the following questions with reasoning a. Analyze the sealabilty of the Alpha processor implementation in terms of superscalar degree and superpipeline degree. b. Analyze the scalbility of an Alpha-based multiprocessor system in tems of address space and multiprocessor support “The superpipelined superscalar DEC-21 064-A architecture consists © 3264-bitimegerregisters (EBOX) with k =7 stages. % 3264-bit floating-point registers (BOX) with & = 10 stages. Clock rate, f= 150.MEis m=? © Hy, =300 MIPS and H,, .,, = 150 Mflops. Mbit adress bus, 28-bit daa bus. Italo feaures (© Multiprocessor support (fast interlocking and interrupts) © Multiple operating system, © Possibility tohandle more numberof issues in future implementation, 4. From the superscalar and superppeine perspectives, we must compare ft wth a scalar processor which has a clock mte 25 MHz. So tha, we will hive a superipelining degre of n= 180/25 =6. Combining it with m =2., we obtain a superpipelined superscalar machine 1054 Ata ‘with degres of (myn)=(2,6). By using these values the performance of DE: machine is Arvin. 2320600802005