10. reo Ne: (TLL ELLE x Code : 71675 B.B/B, Tech, DEGREE EXAMINATION, APRILMAY 2017 ‘Third Fith/Sixth Semester Computer Science and Engineering egulations 2013) © ot Maximum : 100 marks Answer ALL 2 a List the majar componente of @ : —vf State the ned fi indinetaddroeing mode Give an example ‘Subtract (11010) (10900)1: oop on once rn Same the cece] spl ued pero rtm pra. Define hazard. Give an for data hazard. What is parallelism? ney Distinguish | multithreading and explicit multithreading. Define memory interleaving. ‘Summarize the sequence of events involved in handling an interrupt request from a single device.& & ote ® ) ® PART B—(6 = 13 = 65 marks) Explain the important measures of the performance of a computer and derive the basic performance equation. as) Or Explain direct, immediate, relative and indexed addressing modes with examples. as () . Demonstrate multiplication of two binary numbers with an example. Design an arithmetic element a this multipbcation. @ (i) Deseribe non restoring division with an exam a ae ‘operations, (What is meant by sub word Discuss the modified data path to pipelined executions with a diagram. . as) oF o by unconditional branching a ao in a pipeline processor with a o a in parallel processing with necessary © w tp Pre sp ih AY or fe th a a ae to multithreading with nesessary a3 Ne a, nr elon sie pee memories in detail. Or 2 71675» 16. () @ Explain virtual memory address translation in dotail with necessary diagrams. @. @ What i meant by Direct Memory Acoee? Broan the wi of DMA controllers in a computar system. PART C —(Q.x 15= 15 marks) G) Explain mapping functions in cache memory to determine how memory blocks are placed in cache. ® (i) Explain in detail about the Bus Arbitration techniques in DMA. (7) Or F uses branch any one of the following possibility for the design of In the first possibility, the processor has a 4-stage slot. In the possibility, it has a 6-stage pipeline alose, Compare the perfarmance of these two alternatives. branch penalty into sccount. Assume that 20% of are branch instructions and that an optumiz 80% success rate in filling in the single delay alot. Por the: the compiler is 3 71675