EE-3007 DICD LABORATORY

JOURNAL

EXPERIMENT- 1

Simulation of Full Adder

Group No. B2 G3

Group Members

1.Vaishnavi Shastri(I-8)
2. Akash Alekar (I-12)
3. Amol Vaidya(I-15)
4. Shrinath Dhote(I-49)
Objective: To simulate FULL ADDER in spice simulator

(a) To verify truth-table of full adder from waveforms

(b) To verify VTC for any one possible input pattern

Tool used:
Ngspice free simulator

Circuit diagram:

Fig: Full adder Gate Level Circuit

Fig: Nand Gate CMOS circuit

 Fig: Implementation of ex-or gate using nand gate

Functional Description of Circuit -

Basic Full Adder consist of ex-or, and, or gate but all these gates
can be implemented using nand gate by using Demorgan’s Theorem. The logical
implementation of these function is shown in figure. Hence just by using sub-circuits
of nand gate Full Adder can be implemented in ngspice.

Devices Used in Simulations: NMOSFET, W=20u, l=10u

Simulation Results:
 Fig: Full Adder Output Waveforms

Fig: VTC of Full Adder For A=B=Cin=1

Conclusions:
Hence we conclude that above waveforms verifies the truth-table of
Full Adder and VTC for input combination a=b=cin=1 is plotted using ngspice.

Appendix

SPICE Netlist –
*full adder
.include 180nm_bsim3

.subckt nand 2 5 4 1
m0 1 2 4 1 p1 w=20u l=5u
m1 1 5 4 1 p1 w=20u l=5u
m2 4 2 3 0 n1 w=10u l=5u
m3 3 5 0 0 n1 w=10u l=5u
.ends

.subckt xor 7 2 6 1
xi0 7 2 3 1 nand
xi1 7 3 4 1 nand
xi2 3 2 5 1 nand
xi3 4 5 6 1 nand
.ends

x1 a b o1 1 xor
x2 a b o2 1 nand
x3 o1 ci s 1 xor
x4 ci o1 o3 1 nand
x5 o3 o2 co 1 nand

vdd 1 0 dc 1.8
va a 0 pulse(0 1.8 0 10n 10n 10u 20u)
vb b 0 pulse(0 1.8 0 10n 10n 20u 40u)
vc ci 0 pulse(0 1.8 0 10n 10n 40u 80u)

.control
tran 10n 100u
run
plot v(a)+9 v(b)+7 v(ci)+5 v(s)+3 v(co)
.endc
.end

VTC netlist:
*full adder vtc
.include 180nm_bsim3

.subckt nand 2 5 4 1
m0 1 2 4 1 p1 w=20u l=5u
m1 1 5 4 1 p1 w=20u l=5u
m2 4 2 3 0 n1 w=10u l=5u
m3 3 5 0 0 n1 w=10u l=5u
.ends

.subckt xor 7 2 6 1
xi0 7 2 3 1 nand
xi1 7 3 4 1 nand
xi2 3 2 5 1 nand
xi3 4 5 6 1 nand
.ends

x1 a a o1 1 xor
x2 a a o2 1 nand
x3 o1 a s 1 xor
x4 a o1 o3 1 nand
x5 o3 o2 co 1 nand

vdd 1 0 dc 1.8
vabc a 0 dc 1.8

.control
dc vabc 0 1.8 0.1
run
plot v(s) v(co) vs v(a)
print v(s) v(co) v(a) > addervtc
.endc
.end