CHAPTER 1

LOW POWER VLSI DESIGN

–A REVIEW
Introductory aspects and need of Low Power design are discussed,
VM, CM and other circuit methods are reviewed in the perspective
of Low Power design. Some important considerations are also
discussed for the Device Technology adoption in this work

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Reducing Power is a phenomenal development which has gained importance with
developments of deep submicron and nanometer technologies. This CHAPTER
briefly introduces the importance of the Analog and Current Mode design
methods in a power conscious environment.

1.1 INTRODUCTION
Latest developments in the field of VLSI Technology show an increasing interest
in analog circuit design. The main aim of analog integrated circuits (ICs) is to
satisfy circuit specifications through circuit architectures with the required
performance. They can be used either as “stand-alone” topologies or connected to
the digital part to implement mixed analog-digital functions, utilized in a wide
field of applications. Though numerous researchers predicted a reduced utilization
of analog architectures and an increased development of the digital counterpart,
analog circuitry continues to be a necessary part of the technology. In fact, analog
circuits are needed in many VLSI systems such as filters, D/A and A/D
converters, voltage comparators, current and voltage amplifiers, Neuromorphic
and artificial systems by developing chips and systems that process information
collectively using predominantly analog circuits, to emulate natural signal
processing, neural computational systems and biologically inspired processing
systems etc, [29]. Moreover, the recent trend towards miniaturization has given a
strong and decisive boost to the design of low-voltage low-power (LV LP) analog

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integrated circuits design, which are widely utilized in portable-system
applications [1-3].

During the last decades low-voltage/low-power applications are becoming more

and more important because of the increasing portable electronics market. The
emerging rush to the mobile communications including voice, picture, and data
transfer and the need of mobile computers which have almost the same
performance as their immobile counterparts are advancing the continuous
improvement of low-power high-performance integrated circuits.

A subscriber unit of a mobile phone, for example, spends typically most of its
time in the stand-by mode, so that its stand-by power must be kept below a
specified value to maximize the battery lifetime. On the other hand, when a
communication takes place, the unit must perform high speed computations; it
will de-compress the incoming signal and compress the outgoing signal.

Due to the fact that the energy density of commonly used batteries is limited, they
have become a bottleneck in reducing the weight of portable devices. Therefore,
saving weight can only be achieved by reducing the total power consumption.
This is contrary to the fast growing number of devices on a chip due to the
increasing system complexity. Therefore, the power problem has to be solved on
the transistor and circuit levels.

Ultra Large Scale Integration (ULSI) CMOS technology is perfectly suitable for
the requirements of portable electronics due to its scalability and low power
consumption. Various new MOS device architectures have been recently reported
with channel lengths down to the nanometer range, but no general investigation

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has proven that one of these structures is optimal to meet a certain performance
goal.

System requirements for portable electronics are best met by MOS circuits
featuring a restricted drain-source leakage current of the single transistors and
highest possible switching speed. To accomplish this, the devices have to be
optimized for these specifications, so that the prototypes and building blocks are
optimum in performance.

This has led to the implementation of new design circuit strategies in low-cost
CMOS technology. Information processing can be done on node voltages (VM or
voltage mode processing) or in terms of branch currents (CM or current mode
processing). VM techniques received much wider attention whereas, attention to
the CM techniques started just a few decades earlier [4,5].

1.2 VOLTAGE MODE TECHNOLOGY : A REVIEW

There were a few reasons why VM dominated [13]

(i) A node voltage is easy to measure without modifying the topology and
operation whereas the measurement of the branch current is less
convenient to measure and requires a change of circuit configuration or
additional circuitry.

(ii) The infinite impedance looking into the gate of MOS transistors makes
these devices an ideal choice for VM circuits, especially in cascade
configurations

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 (iii) Easy to obtain a high voltage gain of VM circuits using techniques such
as cascode and regulated cascode.

(iv) Higher biasing voltages were not so critical as of today.

(v) Switching noise was not a critical issue with the presence of a high
supply voltage.

(vi) Low speed operations did not concern the charge and discharge of nodal
capacitors over a long period of time.

(vii) VM is a bit historic. It took off first and now posses a huge knowledge
bank. CM is the latest development.

(viii) Feedback is easy to handle in VM. The output signal can be used for
load and feedback simultaneously.

(ix) In VM systems, Gain and bandwidth are at odds. So a trade off is

necessary.

(x) In VM, the design components are often required to be linear because
they control voltage and current at various nodes of the circuit.

(xi) Parasitic capacitances some times turn out treacherous. The clock feed
through and charge sharing between intermediate nodes are common
problems of the VM dynamic circuits.

(xii) Design matrices are Low Voltage, Low Power and bandwidth. It is
extremely difficult to achieve all three in VM systems. A compromise is
a solution. Similar situation do occur in CM systems, but there the
compromise is not so tight as is in VM systems.

The CMRR is one of the major achievements of the VM systems. OPAMP

emerged as a main design block in the VM analog circuit applications and
dominated the market. The situation is nowadays changing. The aggressive device

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scaling has serious concerns regarding the performance of VM circuits rather than
the CM circuits.

1.3 CURRENT MODE - AN EMERGING WAY OF

THINKING
Some of the reasons to chose CM technique may be as following:

1. Device scaling also scales biasing and threshold voltages down, causing a
reduction in signal swing and increased delay. But the CM circuits are
practically immune to such effects.

2. Their ability to overcome the limitation of a constant gain-bandwidth

product [13]

3. The trade-off between speed and bandwidth, to improve performance in

terms of

a. Low-voltage characteristics

b. Slew-rate and bandwidth. [6,10,11]

4. CM does not need High Voltage Gain, so high performance amplifiers are
not needed.

5. CM circuits do not need high precision passive components, therefore they

can be designed almost entirely with MOSFETs. This makes the CM
circuits quite compatible with typical digital world.

6. The current-mode approach is equally a powerful technique. All the analog

IC functions, which were traditionally been designed in VM can also be
implemented in CM.

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 7. The CM technique has the capability to improve Bandwidth. This
improvement is different from the improvement of a voltage amplifier as in
the VM case, BW improves on the cost of Gain, whereas in case of CM, the
improvement is a bit more general, i.e. the BW improves without much
gain loss. This point can be demonstrated as below.

8. CM technique is fully compatible with the existing VM.

1.4 CM/VM : AN OVERVIEW

Design people try to define the Voltage Mode (VM) and Current Mode (CM) as
two fulfledged design methodologies, but till today, it is hard to demarcate one
from the other. However, this way of thinking has generated some very important
design building blocks [127], and has reformed the analog design a lot. In this
section the VM and CM amplifiers are considered. The mode of the amplifier can
be defined on the basis of the principal signals on the way they control it’s
operation. Generally I-V characteristic is not always linear, therefore considering
the mode is also important while designing the amplifier. A VM amplifier may
not work satisfactorily under CM scheme.

1.4.1 OPAMP BASED VM AMPLIFIER

+
Vin Vout
−
-

R2
R1

FIGURE 1.1: OPAMP based VM Amplifier

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Analysis of the circuit of Fig.1.1 is presented below. Assume A – open loop gain
of the OPAMP, Ao – open loop dc gain, A(s) – single dominant pole model of the
OPAMP, β – voltage signal feedback factor, s – Laplace domain representation,
s = jω and ω o – the dominant pole frequency [19].

Vout A
= (1.1)
Vin 1 + βA

R1
β= (1.2)
R1 + R2

Ao
A( s ) = (1.3)
s
1+
ωo

Ao
Vout 1 + β Ao
= (1.4)
Vin s
1+
ω o (1 + β Ao )

1.4.2 OPAMP BASED CM AMPLIFIER

+
− I out
I in
R2
R1

FIGURE 1.2: OPAMP based CM Amplifier

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With same assumptions as considered in the above VM amplifier, circuit analysis
concludes the following results [19]:

I out R
= K = −(1 + 2 ) (1.5)
I in R1

Ao
A( s ) = (1.6)
s
1+
ωo
⎛ R2 ⎞
⎜ ⎟
⎜
K ≈ − 1+
R1 ⎟ (1.7)
⎜ s ⎟
⎜ 1+ ⎟
⎝ ω o (1 + Ao ) ⎠

Equations 1.4 and 1.7 show that the gain of the above VM and CM amplifiers
modify the system frequency ω o (1 + βAo ) ; β < 1 and ωo (1 + Ao ) . Clearly the second
case shows an improvement in both system frequency and gain magnitude. The
frequency responses of the VM and CM amplifiers are given in Figure 1.3. The
feedback network is used same for the purpose of direct comparison of their
characteristics.

1.4.3 FREQUENCY RESPONSE PLOTS OF VM/CM

AMPLIFIERS

It is evident from figure 1.3 that the feedback in VM amplifier enhances dominant
pole frequency by the feedback factor but with gain reduction by the same
feedback factor. In CM amplifier, the gain is not large, but whatever the gain, it
stays almost same, however, the dominant pole frequency is enhanced by the
feedback factor.

A well-known current-mode circuit is the Current-Feedback Operational

Amplifier (CFOA) [23]. The CFOA shows a constant bandwidth with respect to

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the closed-loop gain and a very high slew-rate compared to the traditional
OPAMP. This high slew rate makes the CFOA, a circuit of primary importance in
the design of modern LV LP ICs [23]. The first stage of CFOA is the current-
conveyor (CC). Therefore the CC can be considered the basic CM building block.

Open Loop
Gain Ch.
CM Amplifier

VM Amplifier

FIGURE 1.3: Frequency Response of VM/CM Amplifier [19].

The quest for active device, actually starts with the proposition by Tellegin, and
was later formalized by Carlin with the introduction of the Nullor - Norator
concept. OPAMP and the CCII are the basic active devices. Nullor - Norator
approach realizes undefined impedance levels, therefore, realization for sensible
transfer characteristics, feedback is needed depending upon the type of function
realized between the input and output variables.

Analog amplifiers are classified as voltage controlled voltage source (VCVS),

voltage controlled current source (VCCS), current controlled voltage source
(CCVS) and current controlled current source (CCCS) as they realize the gains in
terms of voltage ratio, trans-conductance, trans-resistance and current ratio
respectively. Thus OPAMP is a voltage amplifier and the OTA is the trans-

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conductance amplifier. Again as usual, the feedback circuit can sample voltage
output or current output and feeds back voltage or current signal input, therefore,
total sixteen possibilities arise, out of which, we can consider four possibilities of
enhanced impedance. By the term ‘enhanced’ it is meant that the impedance
decreases for voltage output and increases for a current output, and like that [19].

From Figure 1.3, it is also worth noting that the GBW product is no more a
constant, in fact the GBW enhances as shown in the sparsely dashed line. For LV-
LP design constraints, trans-resistance feedback configuration is found more
suitable than others [12,19,24]. Since the transresistance feedback has the effect to
decrease the input and the output impedance levels at the ends of the resistor of
Fig.1.5, it is possible to define, for the block depicted in Fig.1.5, a high
impedance (voltage) input terminal (1), a low impedance (current) input terminal
(2), a high impedance (current) output terminal (3) and a low impedance (voltage)
output terminal (4). This solution presents all the possible combinations of low
and high impedances for both input and output terminals, so this is really a
generic block.

I out I out
+ + +
gm + gm
Vin Vin

I out = gmVin

FIGURE 1.4: Transconductance Amplifier FIGURE 1.5: A CCII derived from an OFC
(Ideal Zi and Zo are ∞) It is also known as an with a designated feedback. Also it is similar
OFC with all node voltages and node currents to a Transconductance Amplifier with
defined [19]. Transresistance feedback [19].

This circuit of Fig.1.5 is the current conveyor, and if the output impedance is
adjusted through a voltage buffer, this circuit results into a CFOA. It is a hybrid

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amplifier because it has different impedance levels for different types of signals.
It is also referred in literature as floating conveyor or operational floating
conveyor [24]. The OFC is a versatile and is a quite useful device and can be a
part of the CFOA or can be transformed into a CCII. In fact a CCII can be natural
sequel of OFC of the applied feedback [19]. This apparently is the reason why the
design of CCCII is considered over here in this work.

The usefulness of CMOS current-mode circuits in combating the difficulties

arising from the reduction of the supply voltage and the increase in the operation
speed has received an increasing attention both from industry and academia
recently Therefore, the CM techniques have started taking a lead [6-9] in the
design.

1.5 TECHNOLOGY ADOPTED IN THIS WORK

There are various fabrication technologies prevailing for the fabrication of

CMOS. These are in general the Bulk Silicon, Gallium Arsanide – GaXAsy and
Silicon on Insulator – SOI etc.

GaXAsy is a specific composition which is used for some specialized high speed
applications only. This can not be considered as a general purpose material. Bulk
silicon and SOI are rivals. Bulk devices posses various advantages like easy to
design, fabrication and implement, lowest power delay product, low cost, general
purpose, adaptable to any further improvement and have practically favored
scaling up to the deep submicron and nanomater scales [131].

SOI devices need some extra masks, therefore are costlier and have some serious
disadvantages. SOI devices have their bulk floating and a parasitic BJT, which

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substantially distorts the performance [108,110]. The Floating Body Effect can be
relieved by using a fully depleted SOI, but this SOI do not support scaling.
Furthermore, due to the presence of insulating oxide layer, drain field lines
interact with the source leaving the source influenced by the drain [110].
Advanced SOI can support aggressive scaling, but this requires specialized
materials and processes and opens new challenges [96]. Therefore Bulk Silicon is
still considered a standard in IC fabrication and is considered here as the base
technology through out this work.

1.6 LOW POWER DESIGN

The need for low power design is an age old necessity. Development of the solid
state transistor itself is an enthusiastic step towards low power. Biasing supplies
for solid-state circuits, for crude transistors of those days, were reduced to few
tens of volts from hundreds of volts required for similar tube based circuits. With
the advancement of the technology the necessity for reducing power grew greater.
The power consideration grew so great that it acquired a position as a design
parameter along with the other two parameters the speed and chip area, each one
having a bearing on the others [62].

FIGURE 1.6: Triangle of Design Parameters

Reduction of power is tackled at every possible level, right from the device level
up to the system level. Advancement of technology brings in smaller devices that
would need lower biasing. Further, a smaller device has lower parasites,

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especially capacitance, which usually charge and discharge with every circuit
transition and dissipate a reduced energy per cycle.

In literature, one can see the terms like low power design and power aware
design. low power design refers to reducing power of the design without an
emphasis on performance, whereas power aware design refers to reducing the
overall power with due consideration to the performance as well [93].

1.6.1 DEVICE LEVEL SOLUTIONS

o Use of advanced devices, power and speed usually improve but problems
like leakage aggravate with each new technology.
o The use of SOI CMOS is proposed as a solution for performance, but SOI
devices have some inherent problems which mar their general purpose
usage as a standard technology. Refer section 1.5.
o Nano devices like Carbon Nano Tubes (CNT) are proposed in fabrication
of FETs, called CNTFETs [105]. These CNTFETs are expected to achieve
extreme performance, but their fabrication is still a problem in itself.
o Use of Devices like multigate FETs(FinFETs) and Floating Gate FETs
[106]. These devices address some of the problems of the advanced
technologies very well, but invoke some reliability concerns [105].

1.6.2 CIRCUIT LEVEL SOLUTIONS

In Digital Technology, a wide spectrum of methods is available for alleviating the
problems in deep submicron and nanometer technologies, but Analog is an
establishing field and therefore LV and LP are developing techniques.

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 o Large biasing is usually needed for large swing, but deeply scaled devices
may not afford it. A thicker gate oxide is required to suppress gate leakage,
but it increases VTH and is expected to slow down the speed [105].

o Scaled VDD needs scaled VTH, to maintain high channel current, but needs
extra fabrication steps, hence more cost and longer turn around time [107].

o Techniques based on the Devices like multigate FETs(FinFETs) and

Floating Gate FETs (FGFET) are quite promising. FGFETs can be
programmed by charge storing, to operate at variable VTH. Reliability is a
major problem [105].

o Ultra LV circuits can be achieved by using switched capacitance (SC)

technique. This technique is hard to implement in deep submicron as it
needs clock boosting in SC circuits to achieve accurate sampling [105].

o Current mode circuits are found more suitable as they are usually lesser

voltage dependent, and show no such limitations. Power can be drastically

reduced without any performance deterioration [6,7,19].

Power reduction mechanism in analog circuits is entirely different from

what required in digital circuits. Various LV and LP techniques are
developing that can suite the needs of analog integrated circuits. MOS
current is quadratic with voltage, therefore it appears more appropriate to
handle circuits in terms of current signals than the corresponding voltage
signals. CM techniques are thus expected to support power aware designing
of the Analog VLSI.

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