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CreatingAnADCUsingFPGAResources PDF
CreatingAnADCUsingFPGAResources PDF
Lattice Semiconductor
5555 Northeast Moore Ct.
Hillsboro, Oregon 97124 USA
Telephone: (503) 268-8000
www.latticesemi.com
1 Leveraging FPGA and CPLD Digital Logic to Implement Analog to Digital Converters
The ADC is a common analog building block and almost always is needed when
interfacing digital logic, like that in an FPGA or CPLD, to the “real world” of analog
sensors. This white paper will explain the implementation of both a low frequency (DC
to 1K Hz) and higher frequency (up to 50K Hz) ADC using reference designs and demo
boards available from Lattice Semiconductor. A sample application for each design:
one for a system monitor in a network switch, and another for frequency detection in an
audio communication system, will be examined.
2 Leveraging FPGA and CPLD Digital Logic to Implement Analog to Digital Converters
Once the digital signal has been constructed, the Digital Output can be optionally
filtered to remove any unwanted high frequency components introduced by system
noise or feedback jitter (explained in more detail below). After the optional digital filter
block, an optional memory buffer can be used for debug/testing purposes. The digital
output can be sampled by the memory buffer and then scanned out via a JTAG port into
a personal computer running signal analysis software.
3 Leveraging FPGA and CPLD Digital Logic to Implement Analog to Digital Converters
Initially the RC circuit is set to rise to half of the full voltage swing of the Analog Input by
applying a logic ‘1’ on the Generic Output. Once the voltage is at the one half point, the
output of the LVDS input will indicate whether the Analog Input value is above or below
the RC circuit voltage. If the Analog Voltage is higher, the most significant bit of the
digital output is a logic ‘1’. If the Analog voltage is lower, the digital output is a logic ‘0’.
The SAR moves to the next bit with the sample time cut in half (for a value of one
quarter of the full voltage swing). This process is repeated until the desired accuracy of
the A to D converter is reached. In the example in Figure 2, observe how the RC circuit
voltage gradually approaches the Analog Input value. In this simple example, the 4-bit
digital output of the SAR (0101) is shown at the bottom of the diagram.
4 Leveraging FPGA and CPLD Digital Logic to Implement Analog to Digital Converters
The Low Frequency design can be used to monitor several analog voltage levels that
represent the outputs of various supply voltages and environmental sensors. The
CPLD implementation can monitor PCB power supply voltages (3.3V, 2.5V and 1.8V) as
well as temperature and humidity sensors and an open cabinet alarm. In order to
measure multiple analog inputs one LVDS input will be used for each analog voltage
along with additional RC circuits. Because the analog voltages are slowly changing, the
LVDS outputs can be multiplexed so that the digital logic function can be shared
between each input.
5 Leveraging FPGA and CPLD Digital Logic to Implement Analog to Digital Converters
6 Leveraging FPGA and CPLD Digital Logic to Implement Analog to Digital Converters
The graph at the lower right of Figure 4 shows a sample Analog Input waveform in red
and the output of the sampling flip-flop: a blue column represents a logic ‘1’ and a white
column represents a logic ‘0’. Notice the way the ‘1’s and ‘0’s change in a common
Pulse Code Modulated (PCM) format. Using a Cascaded Integrator Comb (CIC) Filter
the PCM input data can be translated into an output stream that mirrors the frequency of
the Analog Input stream. The CIC function basically integrates (adds or subtracts) the
single bit PCM signals to generate a continuous output signal of the desired number of
bits. In the example at the bottom of Figure 4, treating the blue bits as a ‘1’ and the
white bits as a ‘-1’, it is clear by inspection that a summing (integrating) operation will
generate a digital representation of the input waveform. (Notice that the output
waveform will be shifted by about a half-cycle, since a sequence of ‘1’s will correspond
to an increase in the digital value, whereas in the diagram in Figure 4, a sequence of
‘1’s is shown during the ‘high’ portion of the waveform and a series of ‘0’s is generated
during the ‘low’ portion.)
The voltage from the RC circuit may oscillate around the Analog Input level due to the
“tracking” process created b y the feedback loop. The RC circuit voltage will be moved
from just above to just below the Analog Input level as the oversampling flip-flop
changes between a ‘1’ and ‘0’ result. This process continues until the Analog Input level
changes. This high frequency noise can be eliminated by the use of the optional digital
filters.
7 Leveraging FPGA and CPLD Digital Logic to Implement Analog to Digital Converters
The higher frequency design can monitor multiple audio frequency sidebar signals used
to communicate operational and environmental conditions. For example, 5K Hz and
12K Hz signals can be issued periodically to indicate the state of a remote audio
monitoring system. These signals can indicate the environmental condition
(temperature and humidity) of the equipment. As in the previous example, multiple
analog signals can be supported by simply adding more LVDS inputs. The design could
be a hub for up to 8 analog signals. By time multiplexing the inputs, only a single copy
of the digital logic would need to be used.
8 Leveraging FPGA and CPLD Digital Logic to Implement Analog to Digital Converters
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9 Leveraging FPGA and CPLD Digital Logic to Implement Analog to Digital Converters