Cycle #0

ARF RRF
Reg Data(initial) Data(current) B Tag RR Tag ARF # Data Valid Busy
$0 0x40 0
$1 0x41 1
$2 0x42 2
$3 0x43 3
$4 0x44 4
$5 0x45 5
$6 0x46 6
$7 0x47 7

Reorder Buffer
Dispatch Buffer Hp/Tp
IA RR Tag Instr OP1 V OP2 V Off B B
I
F
IA
RR
S

ALU Reservation Station

ALU Pipeline
IA B Instr OP1 V OP2 V R
stage IA (Result)
0

LSU Reservation Station

IA B Instr OP1 V OP2 V off R

Store Pipeline Load Pipeline

stage IA (Addr) (Data) stage IA (Addr) (Data)
0 0
Memory Contents
Address Initial Value Current Value
80 0x40
Store Buffer 81 0x41
Completed Load Buffer
IA Data Addr 82 0x42
IA Addr
83 0x43
Finished
84 0x44
85 0x45
Committed
86 0x46
87 0x47
88 0x48
89 0x49