14.

ก ก ก

14.1

14.1 ก กก

! "
ก# %$ & '( ) * "'"+ ' ) , '" ! -
!' . ก ก/ "0) " ก 1 ก2 3- - ก . ก "0
' ' 4 - - '"ก ) " "0% -) * ) "ก "0
)"ก ก ก) * (Analog to Digital conversion , A/D) %
- 'ก )', ' 4! - - "! - ) * $ 3- - ก . ก $ ก
F ก ก กG - . ก % -) * ก -
) * ก (Digital to Analog Conversion , D/A )

14.2 !" " # ก (Digital-to-Analog Converter 3

D/A )
' 3I ") " - '$ % -) * + ก+ ก "0 ) * ก !JJK ,
!JJK กG! -

14.2 ก ก ) * ก

163
) + +ก ) * ก'" &")( Binary Weighted DAC R/2R
Ladder ก . &"'" )" "0

14.2.1 Binary Weighted DAC

14.3 ' U ก (Inverting Amp.)

+Z ' )F "0! - ก + ' - [Z $ '"+ ) ก \Rf/Rin

14.4 Binary Weighted DAC

' $ " 14.4 ) G ! - ) ^[Z . Z )ก )', _^ D3- D0 $ . b0c

Vout = 0 ^

3- D3- D0 $ . b1c ! - ) ^[Z $ Z

Vout = - Vref x Rf x(1/1k + 1/2k + 1/4k + 1/8k)
Vout = -Vref x 1 x(1/1 + 1/2 + 1/4 + 1/8)
Vout = -Vref x (1 + .5 + .25 + .125)
Vout = -1.875 x Vref

164
)( 3- Vref = +5V Vout )', [Z ) * b1c ' ! - -9.375 ^ ก . % -'" . 'ก
I0 - %(-+ ' - % 0I +. + Eout

14.5 DAC 8

14.2.2 R/2R Ladder

) * &" "%(-ก ! % ก 4 ) * ' )[ %(-+ + ' - . %(-)[" 2 + +,
1R ก 2R )( 1 K ก 2K '" ก/ ' $ " 14.6 _I ' 3 )+ ^ %(-
Thevenincs theorem

14.6 DAC R/2R Ladder 8

ก " @ A3B C!DE F GHI Thevenin

3 Rth K Thevenin
". ' 3 Rth ! - 0"
0 Rth = 1 k, 1 Rth = 1 k, 2 Rth = 1 k, 3 Rth = 1 k, 4 Rth = 1 k, 5 Rth = 1 k,
6 Rth = 1 k 7 Rth = 1 k

165
 14.7 Thevenin equivalent )[, Rth

3 Vth K Thevenin
". ' 3 Vth ! - "0

14.8 Thevenin equivalent )[, Vth )', 7 ) * '1'

0 Vth = 46.875 mV, 1 Vth = 93.75 mV, 2 Vth = 0.1875 V, 3 Vth = 0.375 V,
4 Vth = 0.75 V, 5 Vth = 1.5 V, 6 Vth = 3V 7 Vth = 6V

14.2.3 กD ก DAC
Resolution
) * ") Gก " Z " D/A ' 3 - ! - "0 I0 $ก . D/A , +. ! -
ก
V 
Vres =  REF
n 
 2 

A! K A ก
Analog Levels = 2 n

166
@@ D (Accuracy)
) * ก ) " ) " + ก + "+. ! - ก ก. ) * ) ^)_ ^ +) ^[Z )', ) G'
)ก (Full scale)

@ R (Speed)
' 3I + ') G Output settling time _I ) * ) " - %(-)[, - +) ^[Z )', [Z '"
ก ) "

ก U"!V !E DAC
DAC " " - % -+ ) ^[Z ก' '+ [Z )', [Z % -+ ' ก I0 ) ^[Z กG
- '"+ ' ก I0 ก )[' I0 [Z 0 กG - % -+ ) ^[Z )[' I0 % 0 ) ก -
3I ก 0 % ) * DAC กG'"ก 4 )["0 )( ก ก 4 )["0 % DAC '" 2 % +, Non-
linear distortion Non-monotonic distortion

Non-Linear Distortion:
ก/ ก 4 )["0 "0 % -+ ) ^[Z ) G !') ก

14.9 ก 4 )["0 Non-linear

Non-Monotonic Distortion
ก/ ก 4 )["0 "0 % -+ ) ^[Z ) G !') ก + 0 % -+
) ^[Z 0 " [Z '"+ )[' I0

167
 14.10 ก 4 [ Monotonic

D DAC 2 '" - 8 ^ + + ') " @ ± 0.2% + resolution

+ + ') " % ) '
Resolution = 1/22 = 1/4 = 25% , Resolution = (1/4)(8V) = 2V
Accuracy = (±0.2%)(8V) = ±16mV

\ ก @

V =V −  V +ref −V ref− 
+ X 10  
V OUT = Output Voltage
 2 V
OUT ref n
 -
ref = VoltageReference-
 V max −V min 
V OUT = V min + X 10  n
 2 −1  V +
ref = VoltageReference+
 
V min =Minimum output voltage
 V +ref −V ref− 
Re solution =  
V max = Maximum outputvoltage
 2 X
n
 10 = Input value base10
 V max −V min 
Re solution =  n n= .
 2 −1 
 
V OUT = V ref + X 10 Re solution
−

V OUT = V min + X 10 Re solution

14.2.4 DAC0800
DAC 0800 ) * ' " . - ") * DAC '" [Z 8 % )- ^[Z ) * ก .
) * ' $ 4.11 G ก! ก' %$ $ " 14.12

168
 14.11 ก/ 3 DAC0800

K @ 3 D
1 GND Ground
2 IOUTc Output
4. IOUT Outputc
5 B1 MSB Input
: : :
12 B8 LSB Input
14 VREF(+) Reference voltage for output
15 VREF(-) Reference voltage for output

14.12 ! ก' DAC0800

169
 D ก V E3F BV\ # !

14.13 ก %(- DAC0800

D ก AT89C2051 ก DAC0800

14.14 ก %(- DAC0800 ก AT89C2051

14.3 ก # !" " (Analog-to-Digital Converter 3

A/D 3 A2D)
% & '( ! ) * "'"+ ' ) , '" ! -!' . ก ก " .
) "0' ' 4 - + '[ ) ^ 0 '!' ' 3 .! - "ก ก
I ) "0 + 0 กG!'! - $% $ !JJK 0 ก .' ' 4 -
- '"ก ก ) "ก ' $ " 14.15 3I 0 ก . % & '(
' %(- % )'- % & '( )( Z F$'_I ) * [ + ' - - 3$ก
% -) * [ !JJK ) " ก - - Z ก ^ ") " ก )_G )_ ^ , )_ ^
) ^[Z "! - ก)_G )_ ^ "0 + ) * "'"+ ' ) , , ") " กก ! ก

170
 0" - 3$ก % )- * - ก) * , "
)"ก ADC ก "0 I ! )- * !JJK " $% $ "[ - ' .! ' 4
% ! -

14.15 ก/ ก %(- ADC

ก ก) * 0 '" $ &" )(
ก) * ก %(- Analog comparator ' $ " 14.16 _I % -) ^[Z
ก' 1 ก ก "0 '" &" , "ก)(
- Digital Ramp ADC (Counter method)
- Successive Approximation
- Parallel Comparator (1Flash2)
- Dual Slope

14.16 ก/ ADC 1

171
14.3.1 Digital Ramp ADC (Counter method)

14.17 ก/ ADC Counter methgod

G ก! ก ' &" "0 $% $ " 14.17 '"ก . "0

1) )', ) ' % - START = 0 ) * ก ")_G (Counter) % -! -) * 0
Zก ก "0 START - ) * 1 )[, ) ' ก .
2) + ก 3$ก % -) * + ก Vax DAC
3) + Vax 3$ก . ! ) " ) " ก + [Z Va ) " ) " (Comparator)
3- Va > Vax ) ^[Z EOC = 1 . % -4 ก AND START EOC
Clock ! -) * Clock K ) - กG + I0 ! ) "
ก กG ) * ! ' 0 " 2 3 ก Va - ก , ) ก Vax
3- Va < , = Vax ) ^[Z EOC = 0 Z ) * ก ) G 0 ก
.

14.3.2 Successive Approximation

14.18 ก/ ADC Successive Approximation

172
 G ก! ก ' &" "0 $% $ " 14.18 '"ก . "0
1) )', ) ' % - START = 0 ) * ก ")_G Control logic Control
Register % -) * 0 Zก [ - ' 0 ก. . " - )_G , ")_G ) * " 7
ก "0 START - ) * 1 )[, ) ' ก .
2) + ก 3$ก % -) * + ก Vax DAC
3) + Vax 3$ก . ! ) " ) " ก + [Z Va ) " ) " (Comparator)
3- Va > Vax ) ^[Z ) " ) " ) * 1 EOC = 1 )',
Clock ) - ' Control logic )_G " Z% -) * 1 [ - ' 0 ) , ก Z ' 1
. -ก ! ) " ) " % '
3- Va < Vax ) ^[Z EOC = 1 )', Clock ) - ' Control logic ")_G
" Z% -) * 0 [ - ' 0 ) , ก Z ' 1 . -ก !
) " ) " % '
ก . $% - 3 "0 ก . + Zก (% " "0'" 8 ) , Va = Vax
) ^[Z EOC ) ก 0 Z . ) * ก ) G 0 ก .

&"ก "0% -+ ') G ' กก ก "ก 0 + กG3$ก I ) * &" " '%(-ก ' ก

14.3.3 Parallel Comparator (`Flash") ADC

) * &" ") G " Z %(-% + " ก %(- " - ก + ') G $
กG'" - ) " % - + )[ %(-„ ^ ^% ก - ' ก 0 I ) ' ก ก %(- "- ก
. -
ก/ ก - ) " ) " ) - . ) " ) " )( 3-

14.19 ก/ ADC Flash

173
 - ก ADC 2 '" . 4 ) G _I '" - 8 ^ 0 )G 0 ^2 ^
4 ^ 6 ^ 0 - %(- ) " ) " 3 ' $ " 14.20 0 )', K [Z
)( 5 V ) - ' ) " ) " 0 3 .ก ) " ) " ก - ! -) ^[Z
) * 011 )- I % -) [^ Z ) * ! " 10 ' $ " 14.20

14.20 ADC Flash 2

14.3.4 ADC c
ก ก "! -ก ' - '"ADC , "ก)( ADC "%(-% ก (Joystick)
++ '[ ) ^ Apple II '" $ '$ " 14.21 . Threshold Detector %(- Op-amp "
%(- - " inverting ) * 2.5 ^ , %(- 74LS14 , 74HCT14 กG! - .
กก. - Potentiometer _I ) * + ' - " + ! - กก . %(-ก + RC
time constant ")ก กก Z% -ก C 1 µF 0 "0ก ( ^ ( ^ Z "0 -
ก ' !' + )_ )_ ^

14.21 ก/ ADC Apple II A-to-D for joystick

174
14.3.5 KF ก 3 !K ADC
Resolution
) ', ก % DAC ) * ก. + + '4 [ ก quantizing _I ) * ก 4 [ ก
+ " -

Accuracy
) ', ก % DAC ) * ก + "3$ก - )', ) " ก + " - ก + "ก. ! -

Conversion Time
) "%(-% ก

Sample and Hold

)', '"+ '3" $ 3- !' - ก % -)ก + '4 [ ) , ก ) "%(- + %(-
Sample and Hold

14.22 ก %(- Sample and Hold

Sampling Rate
+ '3" ก )( 3- ) * 44 kHz กG ' 3I ก )ก I0 Zก
22.7 µS

14.23 ก/ ก Z'

175
14.3.6 ADC0804 8-Bit µP Compatible A/D Converters

14.24 ก/ ADC 0804 ! ก ') ก

ก %(- ADC0804 ก AT89C51

ReadADC0804:
MOVX @R0,A
JB INT0,$
MOVX A,@R0
RET

14.25 ก %(- ADC0804 ก AT89C51

176
14.3.7 ADC K ! 10 " K T89C51AC2
T89C51AC2 '" ADC 10 F$ % '"+Z ' ) "0

14.26 G ก! ก ' ADC T89C51AC2

[Z ! - 8 ( ' )[ ก_^
) * ADC 10
) % ก 20 µS
%(- - +2.4 3I +3 ^
[Z ! - 0 0 3I 3 ^
' 3 ) ^ [ ^_"[" $! -
ก. + '3" Šก ! -
Integral non-linearity ! 1 LSB $ Z !')ก 2 LSB
Differential non-linearity ! 0.5 LSB $ Z !')ก 1 LSB

- ก. % ก %(- '" "0

ADC Port1 I/O Functions

ADC "0%(- [ ^ 1 'ก I/O ก. " " ) ^ ADCF 3- % -) * 1 % - . - "
) * [Z ADC 3- % )- * 0 % - . - )" * [ ^ I/O

ADA E ก
%(-) % ก 11 Šก ) setup !' - ก 4 µS '"! ก'
) ก ' $ " 14.27

177
 14.27 ! ก 'ก . ADC T89C51AC2

A/D Converter clock

14.28 ADC Converter clock

ADC Standby Mode
3- !'! -%(- ADC ' 3% - ADC %$ standby mode ! - % - ADEN % " ) ^
ADCON ) * 0 % ' "0 ก. $ ) " ' 1 !' + ^

" B กD KF
ADCF (ADC Configuration Register) %(-ก. - " [ ^ P1

14.29 - " " ) ^ ADCF

178
ADCON (ADC Control Register) %(-ก. ก . ) * 3 ก .

14.30 - " " ) ^ ADCON

ADCLK (ADC Clock prescaler) %(-ก. + Šก

14.31 - " " ) ^ ADCLK ADDH ADDL

ADDH A ADDL (ADC Data high byte and low byte register) ) * + " ! -

14.32 - " " ) ^ ADCLK ADDH ADDL

179
 D ก @ @\ ADC

[1] Configure P1.2 and P1.3 in ADC channels

ADCF = 0Ch // configure channel P1.2 and P1.3 for ADC
ADCON = 20h // Enable the ADC

[2] Start a standard conversion

// The variable "channel" contains the channel to convert
// The variable "value_converted" is an unsigned int
ADCON and = F8h // Clear the field SCH[2:0]
ADCON | = channel // Select channel
ADCON | = 08h // Start conversion in standard mode
while((ADCON and 01h)! = 01h) // Wait flag End of conversion
ADCON and = EFh // Clear the End of conversion flag
value_converted = (ADDH << 2)+(ADDL) // read the value

[3] Start a precision conversion (need interrupt ADC)

// The variable "channel" contains the channel to convert
EADC = 1 // Enable ADC
ADCON and = F8h // clear the field SCH[2:0]
ADCON | = channel // Select the channel
ADCON | = 48h // Start conversion in precision mode

3- - ก % - ADC ' 3 ) ^ [ ^! - - % - EA = 1 -

180
A " B V BK T89C51AC2

14.33 ) ^[ ^ T89C51AC2
A! @ @ K " BV B

ก ก 3 !@ @ @ K ก " BV B

! @ @ K " BV B cK T89C51AC2

181