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14MVD0123
14MVD0106
Aditya Vibhute
14MVD0123
1
Scripting Languages and Verification Lab (Winter Sem 2014-15)
14MVD0123
14MVD0106
OBJECTIVE:
Write a PERL Program to Generate a Test bench for a given Verilog Code.
DESCRIPTION:
#!usr\bin\perl
open OUT,">fulladd_tb.v";
open IN,"fulladd.v";
$test_vector=9;
while($a=<IN>)
{
if($a=~/module\s(\w+)\((.*)\)\;/)
{
$name=$1;
$portlist=$2;
}
if ($a=~/input\s+(.*)\;/)
{
$input=$1;
@b=split/,/,$input;
$k=@b;
}
2
Scripting Languages and Verification Lab (Winter Sem 2014-15)
14MVD0123
14MVD0106
if($a=~/output\s+(.*)\;/)
{
$output=$1;
}
}
for($i=0;$i<$test_vector;$i=$i+1)
{
{
%b=0;
foreach $j(@b)
{
$data=int(rand(2));
print OUT"\#205j=$data\;\n";
}
print OUT"\n";
}
print OUT"\#200\$stop\;\n";
print OUT"end\n\n";
print OUT"endmodule\n";
close IN;
close OUT;
3
Scripting Languages and Verification Lab (Winter Sem 2014-15)
14MVD0123
14MVD0106
OUTPUT
4
Scripting Languages and Verification Lab (Winter Sem 2014-15)
14MVD0123
14MVD0106
pl script:
#! usr/bin/perl
open out,">count_tb.v";
open in ,"count.v";
$test_vector=10;
while($a=<in>)
{
if($a=~ /module\s(\w+)\((.*)\)\;/)
{
$name=$1;
$ports=$2;
}
if($a=~ /output\s+(.*)\;/)
{
$output=$1;
@d=split / /,$output;
}
if($a=~ /input\s+(.*)\;/)
{
$input=$1;
@b=split/,/,$input;
$k=@b;
}
}
5
Scripting Languages and Verification Lab (Winter Sem 2014-15)
14MVD0123
14MVD0106
Verilog Code:
module count(out,clk,rst);
output [3:0] out;
input clk,rst;
reg [3:0]out;
initial
begin
out=4'b0;
end
always(@posedge clk)
begin
out=out+1;
end
endmodule
OUTPUT:
CONCLUSION:
6
Scripting Languages and Verification Lab (Winter Sem 2014-15)
14MVD0123
14MVD0106
Hence we have successfully generated t es t benches for Verilog codes using
PERL Interpreter for both combinational and sequential logic.