library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity alu_4bit is
Port ( n1 : in STD_LOGIC_VECTOR (3 downto 0);
n2 : in STD_LOGIC_VECTOR (3 downto 0);
op : in STD_LOGIC_VECTOR (2 downto 0);
result : out STD_LOGIC_VECTOR (3 downto 0);
flag : out STD_LOGIC);
end alu_4bit;

architecture Behavioral of alu_4bit is

begin
process(n1,n2,op)
variable temp : std_logic_vector(4 downto 0);
begin
flag<='0';
case op is
when "000"=>
temp :=('0' &n1)+n2;
result <=temp(3 downto 0);
flag <=temp(4);
when"001" =>
if(n1>n2) then
result <= n1 - n2;
else
result <= n2 -n1;
end if;
when "010" =>
result <= n1 nand n2;
when "011" =>
result <= n2 nor n2;
when "100" =>
result <= not n2;
when "101" =>
result <= n1 or n2;
when "110" =>
result <= n1 xor n2;
when others =>
result <= n1;
end case;
end process;
end Behavioral;