Ex 6 PDF

-----------------------------------------------------
--
-- PROBLEMA 6
-----------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
-----------------------------------------------------
entity vehicles is
port(
A, B: in std_logic;
clock: in std_logic;
reset: in std_logic;
I,D,S: out std_logic
);
end vehicles;
-----------------------------------------------------
architecture FSM of vehicles is
-- definim els estats del model:
-- NV: No Vehiculo , LV: Llega Vehiculo
-- VC: Vehiculo Corto, VL: Vehiculo Largo
-- ESA: Error Sensor A, ESB: Error Sensor B
type state_type is (NV, LV, VC, VL, ESA, ESB);
signal estat_seguent, estat_present: state_type;
begin
-- procés concurrent 1: registres d'estat
process(clock, reset)
begin
if (reset='1') then
estat_present <= NV;
elsif (clock'event and clock='1') then

estat_present <= estat_seguent;
end if;
end process;
-- procés concurrent 2: xarxa combinacional
process(estat_present, A, B)
begin
-- fem servir la sentència case pe a modelar la transció d'estats
case estat_present is
when NV =>
I<='0'; D<='0'; S<='0';
if (A='1')and(B='0') then
estat_seguent <= LV;
elsif (A='0')and(B='1') then
estat_seguent <= ESB;
else
estat_seguent <= NV;
end if;
when VC =>
I<='1'; D<='0'; S<='1'; --
estat_seguent <= ESA;
else
estat_seguent <= VC;
end if;
when VL =>
I<='0'; D<='1'; S<='1';
else
estat_seguent <= VL;
end if;
when LV =>
I<='0'; D<='0'; S<='1';
estat_seguent <= VL;

estat_seguent <= VC;
else
estat_seguent <= LV;
end if;
when ESA =>
I<='0'; D<='0'; S<='1';
estat_seguent<=VC;
estat_seguent<=ESA;
else
estat_seguent<=VC;
end if;
when ESB =>
I<='0'; D<='0'; S<='1';

else
end if;
end case;
end process;
end FSM;
-----------------------------------------------------

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-----------------------------------------------------

I,D,S: out std_logic

architecture FSM of vehicles is

-- definim els estats del model:

-- NV: No Vehiculo , LV: Llega Vehiculo

-- VC: Vehiculo Corto, VL: Vehiculo Largo

-- ESA: Error Sensor A, ESB: Error Sensor B

type state_type is (NV, LV, VC, VL, ESA, ESB);

signal estat_seguent, estat_present: state_type;

-- procés concurrent 1: registres d'estat

estat_present <= NV;

elsif (clock'event and clock='1') then

-- procés concurrent 2: xarxa combinacional

-- fem servir la sentència case pe a modelar la transció d'estats

I<='0'; D<='0'; S<='0';

estat_seguent <= LV;

elsif (A='0')and(B='1') then

estat_seguent <= ESB;

elsif (A='1')and(B='1') then

estat_seguent <= ESB;

estat_seguent <= NV;

I<='1'; D<='0'; S<='1'; --

elsif (A='1')and(B='0') then

estat_seguent <= ESA;

estat_seguent <= VC;

I<='0'; D<='1'; S<='1';

estat_seguent <= NV;

estat_seguent <= VL;

I<='0'; D<='0'; S<='1';

estat_seguent <= VL;

elsif (A='0')and(B='1') then

estat_seguent <= LV;

when ESA =>

I<='0'; D<='0'; S<='1';

estat_seguent <= NV;

elsif (A='0')and(B='1') then

elsif (A='1')and(B='0') then

when ESB =>

I<='0'; D<='0'; S<='1';

estat_seguent <= NV;

estat_seguent <= ESB;

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