The Thumb instruction set What is Thumb?

„ Thumb is:
„ Outline:
• a compressed, 16-bit representation of a
Î the Thumb programmers’ model subset of the ARM instruction set
• Thumb instructions – primarily to increase code density
• Thumb implementation – also increases performance in some cases

• Thumb applications „ It is not a complete architecture

• all ‘Thumb-aware’ cores also support the
ARM instruction set
– therefore the Thumb architecture need only
support common functions

©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 1 ©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 2

The Thumb bit The Thumb programmers’ model

31 28 27 8 7 6 5 4 0 r0
shaded registers have
r1 restricted access
NZCV unused IF T mode
r2
r3
Lo registers
„ The ‘T’ bit in the CPSR controls the r4
r5

interpretation of the instruction stream r6

r7

• switch from ARM to Thumb (and back) by r8

r9
executing BX instruction r10
r11
• exceptions also cause switch to ARM code r12
Hi registers

SP (r13)
– return symmetrically to ARM or Thumb code LR (r14)
CPSR

PC (r15)

©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 3 ©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 4

The Thumb programmers’ model The Thumb programmers’ model

„ Thumb register use: „ Thumb-ARM similarities:

• r0 - r7 are general purpose registers • load-store architecture
• r13 is used implicitly as a stack pointer – with data processing, data transfer and control
– in ARM code this is a software convention flow instructions

• r14 is used as the link register
– implicitly, as in the ARM instruction set
• a few instructions can access r8 - r15
• the CPSR flags are set by data processing
instructions & control conditional branches
©2001 PEVEIT Unit - ARM System Design
• support for 8-bit byte, 16-bit half-word and
32-bit data types
– half-words are aligned on 2-byte boundaries
– words are aligned on 4-byte boundaries
• 32-bit unsegmented memory
Thumb – v4 - 5 ©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 6

1
The Thumb programmers’ model The Thumb instruction set

„ Thumb-ARM differences:
„ Outline:
• most Thumb instructions are unconditional
– all ARM instructions are conditional • the Thumb programmers’ model
• most Thumb instructions use a 2-address Î Thumb instructions
format • Thumb implementation
– most ARM instructions use a 3-address format
• Thumb applications
• Thumb instruction formats are less regular
– a result of the denser encoding
• Thumb has explicit shift opcodes
– ARM implements shifts as operand modifiers
©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 7 ©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 8

Thumb branch instructions Thumb branch instructions

15 12 11 8 7 0
„ These are similar to ARM instructions
1101 cond 8-bit offset (1) B<cond> <label> except:
15 11 10 0 • offsets are scaled to half-word, not word
11100 11-bit offset (2) B <label>
• range is reduced to fit into 16 bits
Some instructions (e.g. BL) work in two
15 12 11 10 0
1111 H 11-bit offset (3) BL <label>
„

15 7 6 5 3 2 0
stages
010001110 H Rm 000 (4) BX Rm

©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 9 ©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 10

Thumb branch instructions Thumb software interrupts

„ Branch and eXchange (BX) 15 8 7 0

11011111 8-bit immediate
• to return to ARM or Thumb caller:
BX lr ; replaces MOV pc, lr

„ Subroutine calls „ The Thumb SWI operates exactly like

• later ARMs support BLX instruction the ARM SWI
• to synthesize BLX or earlier ARM: • the (interpreted) immediate is just 8 bits
ADR r0, subr + 1; “+ 1” to enter Thumb mode
– Thumb Angel SWI uses value 0xAB
ADR lr, return ; save return address
• r0 call value is exactly as in ARM code
BX r0 ; calls subr
return ... ; • the SWI handler is entered in ARM code
– the return automatically selects ARM or Thumb
©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 11 ©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 12

2
Thumb data processing instructions Thumb data processing instructions

15 10 9 8 6 5 3 2 0 15 10 9 6 5 3 2 0
000110 A Rm Rn Rd (1) ADD|SUB Rd,Rn,Rm 010000 Op Rm/Rs Rd/Rn (5) <Op> Rd/Rn,Rm/Rs

15 10 9 8 6 5 3 2 0 15 10 9 8 7 6 5 3 2 0
0 0 0 1 1 1 A #imm3 Rn Rd (2) ADD|SUB Rd,Rn,#imm3 010001 Op D M Rm Rd/Rn (6) ADD|CMP|MOV Rd/Rn,Rm

15 13 12 11 10 8 7 0 15 12 11 10 8 7 0
0 0 1 Op Rd/Rn #imm8 (3) <Op> R d/Rn ,#imm8 1010 R Rd #imm8 (7) ADD Rd,SP|PC,#imm8

15 13 12 11 10 6 5 3 2 0 15 8 7 6 0
0 0 0 Op #sh Rn Rd (4) LSL|LSR|ASR Rd,Rn,#shift 10110000 A #imm7 (8) ADD|SUB SP,SP,#imm7

©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 13 ©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 14

Thumb data processing instructions Thumb single register data transfers

Notes:
15 13 12 11 10 6 5 3 2 0
„ 011 B L #off5 Rn Rd (1) LDR|STR{B} Rd,[Rn,#off5]
• in Thumb code shift operations are 15 12 11 10 6 5 3 2 0
separate from general ALU functions 1000 L #off5 Rn Rd (2) LDRH|STRH Rd,[Rn,#off5]
– in ARM code a shift can be combined with an
15 12 11 9 8 6 5 3 2 0
ALU function in a single instruction
0101 Op Rm Rn Rd (3) LDR|STR{S}{H|B} Rd,[Rn,Rm]
• all data processing operations on the ‘Lo’
15 11 10 8 7 0
registers set the condition codes 01001 Rd #off8 (4) LDR Rd,[PC,#off8]
– those on the ‘Hi’ registers do not, apart from
CMP which only changes the condition codes 15 12 11 10 8 7 0
1001 L Rd #off8 (5) LDR|STR Rd,[SP,#off8]

©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 15 ©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 16

Thumb multiple register data

New Thumb opcodes
transfers
15 12 11 10 8 7 0 „ Most significant differences from ARM:
1100 L Rn reg list (1) LDMIA|STMIA Rn!,
{<reg list>}
15 10 9 8 7 0
PUSH ; STMFD sp!,{…}
101111 LR reg list (2) POP|PUSH {<reg list>{,R}}
POP ; LDMFD sp!,{…}
NEG ; RSB Rd, Rs, #0
• These map directly onto the ARM forms: LSR ; MOV Rd, Rd, LSR <Rs | #5>
PUSH: STMFD SP!, {<regs>{, lr}} ASR ; MOV Rd, Rd, ASR <Rs | #5>
POP: LDMFD SP!, {<regs>{, pc}} LSL ; MOV Rd, Rd, LSL <Rs | #5>
– note restrictions on available addressing modes ROR ; MOV Rd, Rd, ROR Rs
compared with ARM code

©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 17 ©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 18

3
The Thumb instruction set Thumb instruction decompressor
B operand bus

Outline:
ARM instruction
„ data in immediate fields decoder

• the Thumb programmers’ model mux

select ARM or

• Thumb instructions Thumb stream

Thumb
Î Thumb implementation select high or
decompressor
low half-word
• Thumb applications mux

instruction
pipeline

data in from memory

©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 19 ©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 20

Thumb - ARM instruction mapping The Thumb instruction set

15 13 12 11 10 8 7 0
0 0 1 10 Rd #imm8 „ Outline:
‘always’
condition • the Thumb programmers’ model
• Thumb instructions
major opcode,
format 3: MOV/
minor opcode destination zero immediate • Thumb implementation
CMP/ADD/SUB denoting ADD and source
shift value
with immediate & set CC register Î Thumb applications

31 28 27 26 25 24 21 20 19 16 15 12 11 0
1110 00 1 0100 1 0 Rd 0 Rd 0000 #imm8

©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 21 ©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 22

Thumb applications Thumb applications

„ Thumb code properties: „ For the best performance:

• 70% of the size of ARM code • use 32-bit memory and ARM code
• 30% less external memory power „ For best cost and power-efficiency:
• 40% more instructions
• use 16-bit memory and Thumb code
„ With 32-bit memory:
„ In a typical embedded system:
• ARM code is 40% faster than Thumb code
• use ARM code in 32-bit on-chip memory
„ With 16-bit memory: for small speed-critical routines
• Thumb code is 45% faster than ARM code • use Thumb code in 16-bit off-chip memory
for large non-critical control routines
©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 23 ©2001 PEVEIT Unit - ARM System Design Thumb – v4 - 24