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Slides 15B PCI Express PDF
Slides 15B PCI Express PDF
Joe Winkles
Senior Staff Engineer
MindShare, Inc.
Signal Link
Wire Lane
Packet
PCIe PCIe
Device Link (x1, x2, x4, x8, x12, x16 or x32) Device
A B
Packet
D-
Vcm
V Diffp
D+
PCIe Legacy
Endpoint Endpoint PCI/PCI-X
Legend
PCI Express Device Downstream Port
PCI Express Device Upstream Port
CPU
Root
RCRB
Bus 0
FSB
PCI Express
GFX
GFX Root Complex
DDR
SDRAM
PCI Express Slots
Serial ATA PCI
HDD
USB 2.0 IO Controller Hub
(ICH) IEEE
LPC 1394
Slot
S
IO
COM1 GB
COM2 Add-In Add-In Add-In
Ethernet
FSB
PCI Express
GFX
GFX Root Complex
DDR
Endpoint SDRAM
10Gb
InfiniBand
InfiniBand Switch Ethernet Switch Fiber
Switch
Endpoint Channel
“Out-of-Box”
Endpoint
RAID Disk array
10Gb PCI Express
Add-In Switch SCSI
Ethernet to-PCI
Endpoint Endpoint Endpoint
PCI
PCI Express
Link Gb Slots
Add-In IEEE
Ethernet S
IO 1394
Endpoint COM1
COM2
PCI-SIG Developers Conference Copyright © 2006, PCI-SIG, All Rights Reserved 10
Transaction Types,
Address Spaces
Request are translated to one of four transaction types by
the Transaction Layer:
1. Memory Read or Memory Write. Used to transfer data from or to a
memory mapped location
– The protocol also supports a locked memory read transaction variant.
2. I/O Read or I/O Write. Used to transfer data from or to an I/O location
– These transactions are restricted to supporting legacy endpoint
devices.
3. Configuration Read or Configuration Write. Used to discover device
capabilities, program features, and check status in the 4KB PCI Express
configuration space.
4. Messages. Handled like posted writes. Used for event signaling and
general purpose messaging.
Completion with Data (used for memory, IO and configuration read completions) CplD
Completion for Locked Memory Read without Data (used for error status) CplLk
MRd FSB
Requester:
-Step 1: Root Complex (requester)
initiates Memory Read Request (MRd) Root Complex
-Step 4: Root Complex receives CplD DDR
SDRAM
MRd CplD
Switch A Switch C
MRd
CplD
MRd CplD
Completer:
Endpoint Endpoint -Step 2: Endpoint (completer)
receives MRd
-Step 3: Endpoint returns
Completion with data (CplD)
PCI-SIG Developers Conference Copyright © 2006, PCI-SIG, All Rights Reserved 14
DMA Transaction
Processor Processor
FSB
Completer:
-Step 2: Root Complex (completer)
receives MRd Root Complex
-Step 3: Root Complex returns DDR
Completion with data (CplD) SDRAM
CplD MRd
Switch A Switch C
CplD
MRd
CplD MRd
Requester:
Endpoint Endpoint -Step 1: Endpoint (requester)
initiates Memory Read Request (MRd)
-Step 4: Endpoint receives CplD
PCI-SIG Developers Conference Copyright © 2006, PCI-SIG, All Rights Reserved 15
Peer-to-Peer Transaction
Processor Processor
FSB
Root Complex
DDR
SDRAM
CplD MRd MRd CplD
Switch A Switch C
CplD
Link
Link
Link
Ordered-Set Ordered-Set
Physical Layer Physical Layer
Transmitted Received
Link
PCI Express
GFX
GFX Root Complex
DDR
Endpoint SDRAM
10Gb
InfiniBand
InfiniBand Switch Ethernet Switch Fiber
Switch
Endpoint Channel
“Out-of-Box” Endpoint
RAID Disk array
10Gb PCI Express
Add-In Switch SCSI
Ethernet to-PCI
Endpoint Endpoint Endpoint
Slot PCI
Video Slots
SCSI S IEEE
PCI Express Camera IO 1394
Link Endpoint COM1
COM2
TC/VC Mapping
Arbitration
VC0
TC[7:0] Buffers Buffers TC[7:0]
VC1
TC[7:3]
maps to VC1
VC1
VC1 One physical Link,
multiple virtual paths
Link
Transmitter Receiver
Receiver sends Flow Control Packets (FCP) which are a type of DLLP (Data Link Layer Packet)
to provide the transmitter with credits so that it can transmit packets to the receiver
Replay
Buffer De-mux De-mux
Error
Mux Mux Check
Tx Rx Tx Rx
DLLP
ACK /
NAK
Link
TLP
Sequence TLP LCRC
PCIe -
PCIe PCIe
THANK YOU!
Joe Winkles
Senior Staff Engineer
MindShare, Inc.