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(Ebook) Cmos Analog Circuit Design (Allen-Holberg) PDF
(Ebook) Cmos Analog Circuit Design (Allen-Holberg) PDF
0-1
I. INTRODUCTION
Contents
I.1 Introduction
I.2 Analog Integrated Circuit Design
I.3 Technology Overview
I.4 Notation
I.5 Analog Circuit Analysis Techniques
Allen and Holberg - CMOS Analog Circuit Design Page I.0-2
Organization
Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS
CIRCUITS
Chapter 5 Chapter 6
CMOS CMOS
Subcircuits Amplifiers
SIMPLE
DEVICES
Introduction
Allen and Holberg - CMOS Analog Circuit Design Page I.2-1
I.1 - INTRODUCTION
GLOBAL OBJECTIVES
• Teach the analysis, modeling, simulation, and design of analog circuits
implemented in CMOS technology.
• Emphasis will be on the design methodology and a hierarchical
approach to the subject.
SPECIFIC OBJECTIVES
1. Present an overall, uniform viewpoint of CMOS analog circuit design.
2. Achieve an understanding of analog circuit design.
• Hand calculations using simple models
• Emphasis on insight
• Simulation to provide second-order design resolution
3. Present a hierarchical approach.
• Sub-blocks → Blocks → Circuits → Systems
4. Examples to illustrate the concepts.
Allen and Holberg - CMOS Analog Circuit Design Page I.2-1
FILTERS AMPLIFICATION
1935-1950
1992
Comparison Comparison
with design Implementation with design
specifications specifications
Simulation
Physical Definition
Physical Verification
Parasitic Extraction
Fabrication
Product
Allen and Holberg - CMOS Analog Circuit Design Page I.2-4
Video
Acoustic
Seismic imaging
Sonar Radar
Telecommunications Microwave
BiCMOS
Bipolar analog
MOS analog
Optical
GaAs
Silicon IC Technologies
WHY CMOS???
DIGITAL ANALOG
MIXED-SIGNAL IC
Allen and Holberg - CMOS Analog Circuit Design Page I.4-1
I.4 NOTATION
SYMBOLS FOR TRANSISTORS
Drain Drain
Source Source/bulk
n-channel, enhance- n-channel, enhance-
ment, VBS ≠ 0 ment, bulk at most
negative supply
Drain Drain
Source Source/bulk
p-channel, enhance- p-channel, enhance-
ment, VBS ≠ 0 ment, bulk at most
positive supply
Allen and Holberg - CMOS Analog Circuit Design Page I.4-2
SYMBOLS FOR CIRCUIT ELEMENTS
Operational Amplifier/Amplifier/OTA
V I
+ +
AvV1 G mV1
V1 V1
- -
VCVS VCCS
I1 I1
Rm I 1 Ai I 1
CCVS CCCS
Allen and Holberg - CMOS Analog Circuit Design Page I.4-3
Notation for signals
Id
id
ID
iD
time
Allen and Holberg - CMOS Analog Circuit Design Page II.0-1
Contents
Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS
CIRCUITS
Chapter 5 Chapter 6
CMOS CMOS
Subcircuits Amplifiers
SIMPLE
DEVICES
Allen and Holberg - CMOS Analog Circuit Design Page II.0-3
OBJECTIVE
Basic Steps
• Oxide growth
• Thermal diffusion
• Ion implantation
• Deposition
• Etching
Photolithography
Means by which the above steps are applied to selected areas of the silicon
wafer.
Silicon wafer
0.5-0.8 mm
125-200 mm
Oxidation
The process of growing a layer of silicon dioxide (SiO2)on the surface of a
silicon wafer.
Original Si surface tox
SiO 2
Uses:
• Provide isolation between two layers
• Protect underlying material from contamination
• Very thin oxides (100 to 1000 Å) are grown using dry-oxidation
techniques. Thicker oxides (>1000 Å) are grown using wet oxidation
techniques.
Allen and Holberg - CMOS Analog Circuit Design Page II.1-3
Diffusion
Movement of impurity atoms at the surface of the silicon into the bulk of
the silicon - from higher concentration to lower concentration.
High Low
Concentration Concentration
t1<t2<t3
N(x)
NB
t1 t2 t3
Depth (x)
Finite-source diffusion:
N0
Gaussian
t1<t2<t3
N(x)
NB
t1 t2 t3
Depth (x)
Allen and Holberg - CMOS Analog Circuit Design Page II.1-4
Ion Implantation
Ion implantation is the process by which impurity ions are accelerated to a
high velocity and physically lodged into the target.
Fixed atoms
Concentration
peak
N(x)
NB
0
Depth (x)
Allen and Holberg - CMOS Analog Circuit Design Page II.1-5
Deposition
Deposition is the means by which various materials are deposited on the
silicon wafer.
Examples:
• Silicon nitride (Si3N4)
• Silicon dioxide (SiO2)
• Aluminum
• Polysilicon
There are various ways to deposit a meterial on a substrate:
• Chemical-vapor deposition (CVD)
• Low-pressure chemical-vapor deposition (LPCVD)
• Plasma-assisted chemical-vapor deposition (PECVD)
• Sputter deposition
Materials deposited using these techniques cover the entire wafer.
Allen and Holberg - CMOS Analog Circuit Design Page II.1-6
Etching
Etching is the process of selectively removing a layer of material.
When etching is performed, the etchant may remove portions or all of:
• the desired material
• the underlying layer
• the masking layer
Important considerations:
• Anisotropy of the etch
lateral etch rate
A = 1 - vertical etch rate
Mask
Film c
b
Underlying layer
Allen and Holberg - CMOS Analog Circuit Design Page II.1-7
Photolithography
Components
• Photoresist material
• Photomask
• Material to be patterned (e.g., SiO2)
Positive photoresist-
Areas exposed to UV light are soluble in the developer
Negative photoresist-
Areas not exposed to UV light are soluble in the developer
Steps:
1. Apply photoresist
2. Soft bake
3. Expose the photoresist to UV light through photomask
4. Develop (remove unwanted photoresist)
5. Hard bake
6. Etch the exposed layer
7. Remove photoresist
Allen and Holberg - CMOS Analog Circuit Design Page II.1-8
Photomask
UV
Light
Photomask
Photoresist Polysilicon
Allen and Holberg - CMOS Analog Circuit Design Page II.1-9
Polysilicon
Photoresist
Photoresist
Polysilicon
Polysilicon
Positive Photoresist
Allen and Holberg - CMOS Analog Circuit Design Page II.2-1
p- substrate
(a)
Si3N4
SiO2
n-well
p- substrate
(b)
n- field implant
n-well
p- substrate
(c)
p- field implant
Si3N4
Photoresist
n-well
p- substrate
(d)
FOX FOX
n-well
p- substrate
(e)
Polysilicon
FOX FOX
n-well
p- substrate
(f)
SiO2 spacer
Polysilicon Photoresist
FOX FOX
n-well
p- substrate
(g)
n+ S/D implant
Polysilicon Photoresist
FOX FOX
n-well
p- substrate
(h)
Polysilicon Photoresist
FOX FOX
n-well
p- substrate
(i)
LDD Diffusion
Polysilicon
FOX FOX
n-well
p- substrate
(j)
FOX FOX
n-well
p- substrate
(k)
BPSG
FOX FOX
n-well
p- substrate
(l)
BPSG
FOX FOX
n-well
p- substrate
(m)
Metal 2
Metal 1
BPSG
FOX FOX
n-well
p- substrate
(n)
Metal 2 Metal 1
Passivation protection layer
BPSG
FOX FOX
n-well
p- substrate
(o)
Polysilicide Polysilicide
Metal
Silicide
FOX FOX
(a) (b)
II.3 - PN JUNCTION
CONCEPT
Metallurgical Junction
iD
+vD -
Depletion
region
p-type n-type
semicon- semicon-
ductor ductor
iD
+vD -
xd
xp xn x
0
1. Doped atoms near the metallurgical junction lose their free carriers
by diffusion.
2. As these fixed atoms lose their free carriers, they build up an
electric field which opposes the diffusion mechanism.
3. Equilibrium conditions are reached when:
PN JUNCTION CHARACTERIZATION
xd
xp xn
p-type n-type
semi- semi-
con- con-
ductor ductor
iD
+vD -
Impurity concentration ( cm-3 )
ND
x
0
-NA
Depletion charge concentration ( cm-3 )
qND
xp
x
0 xn
-qNA
Electric Field (V/cm)
Eo
Potential (V)
φo− v D x
xd
Allen and Holberg - CMOS Analog Circuit Design Page II.3-3
kT NAND NAND
φo = ln 2 = V t ln
q ni ni2
xn =
2εsi(φo-vD)NA
qND(NA+ND) 1
x ∝
N
2εsi(φo-vD)ND
xp = qND(NA+ND)
Depletion capacitance-
εsiqNAND 1 Cj0
Cj = A 2(NA+ND) =
φo-vD φo-vD
Breakdown voltage-
εsi(NA+ND) 2
BV = 2qN N Emax
A D
Allen and Holberg - CMOS Analog Circuit Design Page II.3-4
SUMMARY - CONTINUED
Current-Voltage Relationship-
vD Dppno D n n p o
iD = IsexpV - 1 where Is = qA L + L
t p n
25
20
iD 15
Is 10
5
0
-5
-4 -3 -2 -1 0 1 2 3 4
vD/Vt
10 x1016
8 x1016
16
iD 6 x10
Is
4 x1016
2 x1016
0
-40 -30 -20 -10 0 10 20 30 40
vD/Vt
Allen and Holberg - CMOS Analog Circuit Design II.4-1
W,
th
id
W
el
Polysilicon
n
an
Ch
Fig. 4.3-4
p+ n+ n+
n-channel
Channel
Length, L
p-substrate (bulk)
TYPES OF TRANSISTORS
iD
Depletion Enhancement
Mode Mode
vGS
VT (depletion) VT (enhancement)
Allen and Holberg - CMOS Analog Circuit Design II.4-2
CMOS TRANSISTOR
N-well process
Polysilicon
L SiO2 L
)
(p+
(n+
p+)
n+)
W W
in (
in (
rce
rce
sou
sou
dra
dra
n+
p+
FOX
n-well
p- substrate
Figure 2.3-1 Physical structure of an n-channel and p-channel transistor in an n-well technology.
P-well process
• Inverse of the above.
Polarity of Polarity of
Type of Device Polarity of vDS
vGS and V T vBULK
+ +
n-channel, enhancement Most negative
- +
n-channel, depletion Most negative
- -
p-channel, enhancement Most positive
+ -
p-channel, depletion Most positive
Drain Drain
Source Source/bulk
n-channel, enhance- n-channel, enhance-
ment, VBS ≠ 0 ment, bulk at most
negative supply
Drain Drain
Source Source/bulk
p-channel, enhance- p-channel, enhance-
ment, VBS ≠ 0 ment, bulk at most
positive supply
Allen and Holberg - CMOS Analog Circuit Design II.5-1
FOX FOX
p+ bottom-plate implant
p- substrate
(a)
FOX
Inter-poly SiO2
p- substrate
(b)
M3
M2
T
M1
B Poly
M3 T
M2
T B
M1
M2 B
M1
B T
Poly
M2
T
M1
B
Figure 2.4-2 Various ways to implement capacitors using available interconnect layers.
M1, M2, and M3 represent the first, second, and third metal layers respectively.
Cdesired
Top plate
parasitic
Bottom plate
parasitic
Figure 2.4-3 A model for the integrated capacitors showing top and bottom plate parasitics.
Allen and Holberg - CMOS Analog Circuit Design II.5-3
PROPER LAYOUT OF CAPACITORS
• Use “unit” capacitors
• Use “common centroid”
Want A=2*B
Case (a) fails
Case (b) succeeds!
(a) A1 A2 B
(b) A1 B A2
x1 x2 x3
Figure 2.6-2 Components placed in the presence of a gradient, (a) without common-
centroid layout and (b) with common-centroid layout.
Allen and Holberg - CMOS Analog Circuit Design II.5-4
NON-UNIFORM UNDERCUTTING EFFECTS
Large-scale distortion
Corner-rounding distortion
Allen and Holberg - CMOS Analog Circuit Design II.5-5
VICINITY EFFECT
C
A B
C
A B
Corner clipping:
Clip
corners
Street-effect compensation:
Allen and Holberg - CMOS Analog Circuit Design II.5-7
ERRORS IN CAPACITOR RATIOS
Let C1 be defined as
C1 = C1A + C1P
and C2 be defined as
C2 = C2A + C2P
C2A
C
2P
C2A
1 +
C2 C2A + C2P
C1 = C1A + C1P = C1A C1P
1 + C1A
Thus best matching is achieved when the area to periphery ratio remains
constant.
Allen and Holberg - CMOS Analog Circuit Design II.5-8
CAPACITOR PARASITICS
Top Plate
Top plate
parasitic Desired
Capacitor
Bottom plate
Bottom Plate parasitic
SiO2 p+
FOX FOX
n- well
p- substrate
(a)
Metal
Polysilicon resistor
FOX
p- substrate
(b)
Metal
n+
p- substrate
(c)
Metal
Emitter (p+) Base (n+)
Depletion regions
p n p
Emitter Base Collector
Carrier concentration
ppE
nn(x)
ppC
pn(0)
NA npE(0) ND
NA
pn(x)
npE
pn(wB) ppC
x
x=0 x=wB
II.6 - LATCHUP
VDD
S G D=B S G D=A
Well tie
Substrate tie
p-substrate RP-
(a)
VDD
RN- Q2
A
Q1
B
RP-
(b)
Figure 2.5-3 (a) Parasitic lateral NPN and vertical PNP bipolar transistor in CMOS
integrated circuits. (b) Equivalent circuit of the SCR formed from the parasitic
bipolar transistors.
Allen and Holberg - CMOS Analog Circuit Design II.6-2
PREVENTING LATCHUP
VDD VSS
FOX
n-well
p- substrate
VDD
p+ – n-well diode
Bonding
Pad
To internal gates p+ resistor
n+ – substrate diode
VSS
(a)
Metal
n+ FOX p+ FOX
n-well
p-substrate
(b)
Figure 2.5-5 Electrostatic discharge protection circuitry. (a) Electrical equivalent circuit (b) Implementation
in CMOS technology
Allen and Holberg - CMOS Analog Circuit Design II.8-1
1B
1A
2E
2B
2A
2F
2C
2D
3C 3A 3E 3D
3B
4C 4B
4A
5C
5A
5B
5D
5E
5F 5G 5H
7A
7B
6B
7C
6A
7D
8A
8B
9B
9A
9C
Metal
FOX FOX
Active area
Polysilicon
drain/source
gate
Contact L
Cut
Active area
drain/source
Metal 1
(a) (b)
Figure 2.6-4 Example layout of MOS transistors using (a) mirror symmetry, and
(b) photolithographic invariance.
PLI IS BETTER
Allen and Holberg - CMOS Analog Circuit Design II.8-9
Resistor Layout
Metal
FOX FOX
Substrate
Cut
L
Metal 1
Metal
Substrate
Active area W
Well diffusion
Contact
Cut
Metal 1
L
Figure 2.6-5 Example layout of (a) diffusion or polysilicon resistor and (b) Well resistor
along with their respective side views at the cut line indicated.
Allen and Holberg - CMOS Analog Circuit Design II.8-10
Capacitor Layout
Polysilicon 2
Metal
FOX
Substrate
Polysilicon gate
Polysilicon gate
Polysilicon 2
Cut
Metal 1
(a)
FOX
Substrate
Metal 2 Metal 1
Metal 3 Metal 3
Via 2
Via 2
Metal 2
Cut
Via 1
Metal 1
(b)
Figure 2.6-7 Example layout of (a) double-polysilicon capacitor, and (b) triple-level
metal capacitor along with their respective side views at the cut line indicated.
Allen and Holberg - CMOS Analog Circuit Design Page III.0-1
Contents
Perspective
Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS
COMPLEX
CIRCUITS
Chapter 5 Chapter 6
CMOS CMOS Amplifiers
Subcircuits
SIMPLE
Chapter 2 Chapter 3
Chapter 4 Device
CMOS CMOS Device
Characterization
Technology Modeling
DEVICES
Allen and Holberg - CMOS Analog Circuit Design Page III.1-1
vGS ≤ VT:
+ + iD
v GS iD
= VT - VDS
Source
and Gate Drain - =0.1V
bulk
0
p substrate (bulk) 0 VT 2VT 3VT v GS
vGS = 2VT:
+ + iD
v GS iD
VDS
Source = 2VT -
- =0.1V
and Gate Drain
bulk
0
p substrate (bulk) 0 VT 2VT 3VT v GS
vGS = 3VT:
+ + iD
v GS iD
VDS
Source = 3VT-
and Gate Drain - =0.1V
bulk
0
p substrate (bulk) 0 VT 2VT 3VT v GS
Allen and Holberg - CMOS Analog Circuit Design Page III.1-3
vDS = 0V:
+
VGS + iD v DS iD
Source = 2VT - = 0V
Gate -
and Drain
bulk
p substrate (bulk)
0
0 0.5VT VT v DS
vDS = 0.5VT:
+
VGS + iD v DS = i D
Source = 2VT - 0.5VT
Gate -
and Drain
bulk
0
p substrate (bulk) 0 0.5VT VT v DS
vDS = VT:
+ iD
VGS + iD v DS
Source = 2VT - =VT
Gate -
and Drain
bulk
x
p substrate (bulk) 0 0.5V T VT vDS
Allen and Holberg - CMOS Analog Circuit Design Page III.1-4
vGS = VT:
+ + v = iD
v GS = iD DS
Source VT 4V
- - T
and Gate Drain
bulk
vDS(sat)
0
p substrate (bulk) 0 VT 2VT 3VT 4VT v DS
vGS = 2VT:
+ + v = iD
v GS = iD DS
Source 2VT - - 4VT
and Gate Drain
bulk
vDS(sat)
0
p substrate (bulk) 0 VT 2VT 3VT 4VT v DS
vGS = 3VT:
+ + v = iD
v GS = iD DS
Source 3VT 4V
- - T
and Gate Drain
bulk
vDS(sat)
0
p substrate (bulk) 0 VT 2VT 3VT 4VT v DS
Allen and Holberg - CMOS Analog Circuit Design Page III.1-5
iD (mA)
1.0 VGS=4V
0.5 VGS=3V
VGS=2V
VGS=1V
0
0 2 4 6 8 10
vDS (V)
Transconductance Characteristics of an n-channel MOSFET
2.0
Transconductance Characteristics of a n-channel MOSFET VDS=8V
.MODEL MN1K100 NMOS VTO=1 KP=200U LAMBDA=0.01 VDS=6V
.DC VGS 0 5 0.5 VDS 2 8 2
MOSFET1 2 1 0 0 MN1K100 VDS=4V
1.5 .PRINT DC ID(MOSFET1)
VGS 1 0
VDS 2 0
.PROBE
iD (mA) .END
VDS=2V
1.0
0.5
0
0 1 2 3 4 5
vGS(V)
Allen and Holberg - CMOS Analog Circuit Design Page III.1-6
n+ n+
v(y)
Source dy Drain
p- y
0 y y+dy L
Derivation-
• Let the charge per unit area in the channel inversion layer be
QI(y) = C ox[vGS − v(y) − VT] (coulombs/cm2)
• Define sheet conductivity of the inversion layer per square as
cm2 coulombs amps 1
σS = µoQI(y) v·s cm2 = volt = Ω/sq.
• Ohm's Law for current in a sheet is
iD dv
JS = = σ E = σ S
W S y dy .
Rewriting Ohm's Law gives,
iD iDdy
dv = σ W dy = Q (y)W
S µo I
where dv is the voltage drop along the channel in the direction of y.
Rewriting as
iD dy = WµoQI(y)dv
and integrating along the channel for 0 to L gives
L vDS vDS
⌡WµoCox[vGS−v(y)−VT] dv
⌠ ⌠WµoQI(y)dv = ⌠
⌡iDdy = ⌡
0 0 0
After integrating and evaluating the limits
2
WµoCox vDS
iD = (v −V )v −
L GS T DS 2
Allen and Holberg - CMOS Analog Circuit Design Page III.1-7
iD
vDS = vGS - VT
Increasing
values of vGS
vDS
iD = 0, vGS − VT < 0
(Ignores subthreshold currents)
µCoxW
2L 2(vGS − VT) − v DS vDS , 0 < vDS < vGS − VT
iD =
µCoxW 2
iD = 2L (vGS − VT) , 0 < vGS − VT < vDS
Allen and Holberg - CMOS Analog Circuit Design Page III.1-8
L vDS vDS
⌠
⌡ iD dy = ⌠ ⌡ WµoCox[vGS − v(y) − V T]dv
⌡ WµoQI(y)dy = ⌠
0 0 0
Assume that the threshld voltage varies across the channel in the following
way:
VT(y) = VT + ∆v(y)
where V T is the value of the threshold voltage at the source end of the
channel.
v
WµoCox v2(y) DS
iD = (vGS−VT)v(y) − (1+∆)
L 2 0
or
WµoCox v2DS
iD = (vGS−VT)vDS − (1+∆)
L 2
To find vDS(sat), set the derivative of iD with respect to vDS equal to zero
and solve for vDS = vDS(sat) to get,
vGS − VT
vDS(sat) = 1+∆
Therefore, in the saturation region, the drain current is
WµoCox
2
iD = v GS − V T
2(1+∆)L
Allen and Holberg - CMOS Analog Circuit Design Page III.1-9
iD
Decreasing values
of bulk-source voltage
VBS = 0
vDS ≥ vGS - VT
vGS
VT0 VT1 VT2 VT3
In general, the simple model incorporates the bulk effect into V T by the
following empirically developed equation-
p+ n+ n+
p- Substrate/Bulk
VSB1>0V:
VSB1 Gate Drain
- + VGS>VT VDS>0
Bulk Source Poly
p+ n+ n+
p- Substrate/Bulk
p+ n+ n+
p- Substrate/Bulk
Allen and Holberg - CMOS Analog Circuit Design Page III.1-11
G B vDS
+ +
vGS vBS
- --
S
Non-saturation-
WµoCox vDS2
iD = (vGS − V T)vDS −
L 2
Saturation-
WµoCox vDS(sat)2
iD = (v − VT)vDS(sat) − (1 + λvDS)
L GS 2
WµoCox
2L (vGS − VT) (1 + λvDS)
= 2
where:
µo = zero field mobility (cm2/volt·sec)
Cox = gate oxide capacitance per unit area (F/cm2)
λ= channel-length modulation parameter (volts-1)
VT = VT0 + γ 2|φf| + |vBS| − 2|φf|
VT0 = zero bias threshold voltage
γ = bulk threshold parameter (volts1/2)
2|φf| = strong inversion surface potential (volts)
When solving for p-channel devices, negate all voltages and use the n-
channel model with p-channel parameters and negate the current. Also
negate VT0 of the p device.
Allen and Holberg - CMOS Analog Circuit Design Page III.1-12
iD /ID0
vDS = vGS - VT
vGS -VT
1.0 = 1.0
Non-Sat VGS0 - VT
Region Saturation Region
vGS-VT = 0.867
0.75 VGS0 - VT
Channel modulation effects vGS-VT = 0.707
0.5 VGS0 - VT
vGS-VT = 0.5
VGS0 - VT
0.25 vGS-VT = 0
Cutoff Region VGS0 - VT
0 vDS
0 0.5 1.0 1.5 2.0 2.5 VGS0 - VT
Notation:
W W
ß = K' = (µoCox)
L L
Note:
µoCox = K'
Allen and Holberg - CMOS Analog Circuit Design Page III.1-13
GRAPHICAL INTERPRETATION OF λ
Assume the MOS is transistor is saturated-
µCoxW
∴ iD = 2L (vGS − VT) 2(1 + λvDS)
µCoxW
∴ iD(0) =
2L (vGS − VT)
2
Now,
iD = iD(0) [1+λvDS] = iD(0) + λiD(0) vDS
or
1 1
vDS = i −
λiD (0) λ
D
vDS
1
1 λiD(0)
iD
iD(0)
-1
λ
or
iD
iD3(0) VGS3
iD2(0)
iD1(0) VGS2
VGS1
vDS
-1
λ
Allen and Holberg - CMOS Analog Circuit Design Page III.1-14
Typical Parameter
Model Parameter
Value Units
Parameter Description
NMOS PMOS
VT0 ThresholdVoltage forVBS = 0V 0.75±0.15 −0.85±0.15 Volts
(sat.)
inversion
These values are based on a 0.8 µm silicon-gate bulk CMOS n-well process.
Allen and Holberg - CMOS Analog Circuit Design Page III.1-15
iD (nA)
Weak
1000.0 inversion
iD
region Strong
100.0 inversion
region
10.0
1.0
0 VT VON vGS 0 VT VON vGS
This model is appropriate for hand calculations but it does not accommodate
a smooth transition into the strong-inversion region.
W qvGS
iD ≅ L IDO exp nkT
kT
vgs < V T + n
q
Weak-Moderate-Strong Inversion Approximation
Moderate
inversion region
iD (nA)
Weak
1000.0 inversion
region Strong
100.0 inversion
region
10.0
1.0
0 vGS
Allen and Holberg - CMOS Analog Circuit Design Page III.2-1
SiO2
Gate
Source Drain
C1 C2
C3
C4
CBS CBD
Bulk
Depletion Capacitors
Bulk-drain pn junction -
CBD
Capacitance
approximation
for strong for-
ward bias
CBD0xArea
(FC).φ B
VBD
Forward φ B
Reverse Bias Bias
For strong forward bias, approximate the behavior by the tangent to the
above CBD or CBS curve at vBD or vBS equal to (FC)·φ B.
CBD0A BD vBD
CBD = 1 − (1+MJ)FC + FC , vBD > (FC)·φ B
(1+FC)1+MJ φB
and
CBS0ABS vBS
CBD = 1 − (1+MJ)FC + FC , vBS > (FC)·φ B
(1+FC)1+MJ φB
Allen and Holberg - CMOS Analog Circuit Design Page III.2-3
H G
C
D
Source Drain
F
E
A B
SiO2
Bulk
(CJ)(AX) (CJSW)(PX)
CBX = + , vBX ≤ (FC)(PB)
vBX MJ vBX MJSW
1 − 1 −
PB PB
and
(CJ)(AX) vBX
CBX = 1 − (1 + MJ)FC + MJ
(1 − FC)1+MJ PB
(CJSW)(PX) vBX
,
+ 1 − (1 + MJSW)FC + (MJSW)
(1 − FC)1+MJSW PB
vBX ≥ (FC)(PB)
where
Overlap Capacitance
Mask L
Oxide encroachment
Actual
L (Leff) Actual
Mask
W (Weff)
LD W
Gate
Bulk
Figure 3.2-5 Overlap capacitances of an MOS transistor. (a) Top view showing
the overlap between the source or drain and the gate. (b) Side view.
Overlap Overlap
C5 Gate C5
FOX FOX
Source/Drain
Bulk
Capacitance
C2 + 2C5
CGS
C1 + _23 C2
CGS, CGD
C1 + _12 C2
vDS = constant
vBS = 0
CGS, CGD CGD
C1, C3
CGB
2C5
0
Non- vGS
Off Saturation
Saturation
VT vDS +VT
Figure 3.2-7 Voltage dependence of CGS, CGD, and CGB as a function of VGS
with VDS constang and VBS = 0.
iD
v DS = v GS - VT
Non-Sat
Region
Saturation
Region
Cutoff Region
0
0 0.5 1.0 1.5 2.0 2.5
vDS = constant
Allen and Holberg - CMOS Analog Circuit Design Page III.2-7
Off
CGB = C2 + 2C5 = Cox(Weff )(Leff ) + CGBO(Leff )
rD
Cbd
inrD
Cgd
gbd
gds
gmvgs
G inD B
Cgs gmbsvbs gbs
inrS Cbs
Cgb rS
∂IBD
gbd = (at the quiescent point) ≅ 0
∂VBD
and
∂IBS
gbs = (at the quiescent point) ≅ 0
∂VBS
The channel conductances, gm, gmbs, and gds are defined as
∂ID
gm = (at the quiescent point)
∂VGS
∂ID
gmbs = (at the quiescent point)
∂VBS
and
∂ID
gds = (at the quiescent point)
∂VDS
Allen and Holberg - CMOS Analog Circuit Design Page III.3-2
Saturation Region
γ
gmbs = gm = η gm
2(2|φF| + VSB)1/2
ID λ
gds = go = ≅ ID λ
1 + λ VDS
Relationships of the Small Signal Model Parameters upon the DC Values of Voltage
and Current in the Saturation Region.
Small Signal DC Current DC Current and DC Voltage
Model Parameters Voltage
gm ≅ (2K' IDW/L)1/2 _ 2K' W
≅ (V -V ) GS T
L
gmbs γ (2IDβ)1/2 γ ( β (VGS −VT) )
2(2|φF | +VSB) 1/2
2(2|φF | + VSB)1/2
gds ≅ λ ID
Allen and Holberg - CMOS Analog Circuit Design Page III.3-3
Nonsaturation region
∂Id
gm = = β VDS
∂VGS
∂ID βγ VDS
gmbs = =
∂VBS 2(2|φF | + VSB)1/2
and
gds = β (VGS − VT − VDS)
Noise
2 4kT
i nrD = ∆f (A2)
rD
2 4kT
i nrS = ∆f (A2)
rS
and
Drain Current
1 + fb
iDS = BETA vGS − VT − 2 vDE ⋅ vDE (1)
Weff Weff
BETA = KP L = µeffCOX (2)
eff Leff
GAMMA ⋅ fs
fb = fn + (6)
4(PHI + vSB)1/2
Note that PHI is the SPICE model term for the quantity 2φf . Also be aware that PHI is
always positive in SPICE regardless of the transistor type (p- or n-channel).
DELTA πεsi
fn = (7)
Weff 2 ⋅ COX
xj LD + wc LD
1/2
wp 2
fs = 1 − 1− − x
xj + wp
(8)
Leff xj j
2⋅εsi 1/2
xd = (10)
q ⋅ NSUB
Allen and Holberg - CMOS Analog Circuit Design Page III.4-2
wp wp2
wc = xj k1 + k2 − k3 (11)
xj xj
Threshold Voltage
ETA⋅8.15-22
VT = Vbi − v + GAMMA ⋅ f ( PHI + v )1/2 + f ( PHI + v ) (12)
C L 3 DS s SB n SB
ox eff
or
Saturation Voltage
vgs − VT
vsat = (15)
1 + fb
1/2
vDS(sat) = vsat + vC − vsat + vC
2 2
(16)
VMAX ⋅ Leff
vC = (17)
µs
If VMAX is not given, then vDS(sat) = vsat
Effective Mobility
U0
µs = when VMAX = 0 (18)
1 + THETA (vGS − VT)
µs
µeff = when VMAX > 0; otherwise µeff = µs (19)
vDE
1+
vC
Channel-Length Modulation
When VMAX = 0
Allen and Holberg - CMOS Analog Circuit Design Page III.4-3
1/2
∆L = xd KAPPA (vDS − vDS(sat)) (20)
when VMAX > 0
1/2
ep ⋅ xd 2 ep ⋅ xd 2 2
∆L = − 2 + 2 + KAPPA ⋅ xd 2 ⋅ (vDS − vDS(sat)) (21)
where
vC (vC + vDS(sat))
ep = (22)
Leff vDS (sat)
iDS
iDS = (21)
1 − ∆L
In the SPICE Level 3 model, the transition point from the region of strong inversion to
the weak inversion characteristic of the MOS device is designated as von and is greater
than VT. von is given by
von = VT + fast (1)
where
where iDS is given as (from Eq. (1), Sec. 3.4 with vGS replaced with von)
1 + fb
iDS = BETAvon − VT − v ⋅v (4)
2 DE DE
Allen and Holberg - CMOS Analog Circuit Design Page III.4-4
Typical Model Parameters Suitable for SPICE Simulations Using Level-3 Model
(Extended Model). These Values Are Based upon a 0.8µm Si-Gate Bulk CMOS n-
Well Process
Parameter Parameter Typical Parameter Value
Symbol Description N-Channel P-Channel Units
VTO Threshold 0.7 ± 0.15 −0.7 ± 0.15 V
UO mobility 660 210 cm2/V-s
DELTA Narrow-width threshold 2.4 1.25
adjust factor
ETA Static-feedback threshold 0.1 0.1
adjust factor
KAPPA Saturation field factor in 0.15 2.5 1/V
channel-length modulation
THETA Mobility degradation factor 0.1 0.1 1/V
NSUB Substrate doping 3×1016 6×1016 cm-3
TOX Oxide thickness 140 140 Å
XJ Mettallurgical junction 0.2 0.2 µm
depth
WD Delta width µm
LD Lateral diffusion 0.016 0.015 µm
NFS Parameter for weak 7×10 11 6×10 11 cm-2
inversion modeling
CGSO 220 × 10 −12 220 × 10 −12 F/m
CGDO 220 × 10 −12 220 × 10 −12 F/m
CGBO 700 × 10 −12 700 × 10 −12 F/m
CJ 770 × 10 −6 560 × 10 −6 F/m2
CJSW 380 × 10 −12 350 × 10 −12 F/m
MJ 0.5 0.5
MJSW 0.38 0.35
NFS Parameter for weak 7×1011 6×1011 cm-2
inversion modeling
Allen and Holberg - CMOS Analog Circuit Design Page III.4-5
Temperature Dependence
The temperature-dependent variables in the models developed so far include the: Fermi
potential, PHI, EG, bulk junction potential of the source-bulk and drain-bulk junctions,
PB, the reverse currents of the pn junctions, IS, and the dependence of mobility upon
temperature. The temperature dependence of most of these variables is found in the
equations given previously or from well-known expressions. The dependence of mobility
upon temperature is given as
T BEX
UO(T) = UO(T0)
T0
where BEX is the temperature exponent for mobility and is typically -1.5.
KT
vtherm(T) =
q
T2
EG(T) = 1.16 − 7.02 ⋅ 10−4 ⋅
T + 1108.0
EG(T0) EG(T)
PHI(T) = PHI(T0) ⋅ − vtherm(T) 3 ⋅ ln +
T T
−
T0 T0 vtherm(T0) vtherm(T)
PHI(T)= 2 ⋅ vtherm ln
NSUB
ni (T)
3/2
⋅ exp EG ⋅ − 1 ⋅
⋅
T T 1
ni(T) = 1.45 ⋅ 1016
T0 T 0 2 ⋅ vtherm(T0)
For drain and source junction diodes, the following relationships apply.
EG(T0) EG(T)
PB(T) = PB ⋅ − vtherm(T) 3 ⋅ ln +
T T
−
T0 T 0 v (T
therm 0) v therm(T)
IS(T0) EG(T0) T
+ 3 ⋅ ln
EG(T)
IS(T) = ⋅ exp −
N therm 0)
v (T v therm(T) T 0
“M,” tells SPICE that the instance is an MOS transistor (just like “R” tells
SPICE that an instance is a resistor). The “1” makes this instance unique
(different from M2, M99, etc.)
The four numbers following”M1” specify the nets (or nodes) to which the
drain, gate, source, and substrate (bulk) are connected. These nets have a
specific order as indicated below:
Following the net numbers, is the model name governing the character of the
particular instance. In the example given above, the model name is “NCH.”
There must be a model description of “NCH.”
The transistor width and length are specified for the instance by the
“W=100U” and “L=1U” expressions.
The default units for width and length are meters so the “U” following the
number 100 is a multiplier of 10-6. [Recall that the following multipliers
can be used in SPICE: M, U, N, P, F, for 10-3, 10-6, 10-9, 10-12 , 10 -15 ,
respectively.]
Additional information can be specified for each instance. Some of these are
Drain area and periphery (AD and PD) ← calc depl cap and leakage
Source area and periphery (AS and PS) ← calc depl cap and leakage
Drain and source resistance in squares (NRD and NRS)
Multiplier designating how many devices are in parallel (M)
Initial conditions (for initial transient analysis)
The number of squares of resistance in the drain and source (NRD and NRS)
are used to calculate the drain and source resistance for the transistor.
Allen and Holberg - CMOS Analog Circuit Design Page III.3-2
Geometric Multiplier: M
To apply the “unit-matching” principle, use the geometric multiplier feature
rather than scale W/L.
This:
(a) (b)
MODEL Description
A SPICE simulation file for an MOS circuit is incomplete without a
description of the model to be used to characterize the MOS transistors used
in the circuit. A model is described by placing a line in the simulation file
using the following format.
MODEL PARAMETERS :
LEVEL=1 VTO=1 KP=50U GAMMA=0.5 LAMBDA=0.01
εox
KP = UO
TOX
Other parameters:
IS: Reverse current of the drain-bulk or source-bulk junctions in Amps
JS: Reverse-current density in A/m2
JS requires the specification of AS and AD on the model line. If IS is
specified, it overrides JS. The default value of IS is usually 10-14 A.
If CBD and CBS are entered, these values override CJ and NSUB calculations.
In order for CJ to result in an actual circuit capacitance, the transistor instance must
include AD and AS.
In order for CJSW to result in an actual circuit capacitance, the transistor instance must
include PD and PS.
XQC: Channel charge flag and fraction of channel charge attributed to the drain
Allen and Holberg - CMOS Analog Circuit Design Page IV.0-1
Contents
Organization
Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS
CIRCUITS
Chapter 5 Chapter 6
CMOS CMOS
Subcircuits Amplifiers
SIMPLE
DEVICES
1
Allen and Holberg - CMOS Analog Circuit Design Page IV.1-1
W eff
iD = K' S (v GS - V T ) 2 (1 + λ v DS ) (1)
2L
eff
2
W eff v DS
iD = K' L (v G S - V T ) v D S - (2)
L eff 2
V T = V T0 + γ 2| φ F | + v S B - 2| φ F | (3)
x = v GS (8)
1
Allen and Holberg - CMOS Analog Circuit Design Page IV.1-2
2
Allen and Holberg - CMOS Analog Circuit Design Page IV.1-3
Mobility degradation
region
v DS > VDSAT
1/2
( iD )
Weak inversion
region 1/2
K S′ Weff
m=
2 L eff
b ′ = VT0
v GS
(a)
v DS = 0 . 1 V
iD
K L′ Weff
m= vDS
L eff
vGS
(b)
Figure B.1-1 (a) iD1/2 versus vGS plot used to determine VT0 and K'S. (b) iD versus
vGS plot to determine K'L.
W eff W eff v D S
iD = K' L v DS v GS - K' L v DS V T + (11)
L eff L eff 2
Plot iD versus vGS as shown in Fig. B.1-1(b), the slope is seen to be
3
Allen and Holberg - CMOS Analog Circuit Design Page IV.1-4
∆iD W eff
m = ∆v = K' L vDS (12)
GS Leff
x= 2| φ F | + v SB − 2| φ F | (15)
m=γ (16)
b = V T0 (17)
4
Allen and Holberg - CMOS Analog Circuit Design Page IV.1-5
1/2
(i D )
Figure B.1-2 iD1/2 versus vGS plot at different vSB values to determine γ.
VSB = 3 V
VSB = 2 V
VT
VSB = 1 V
m=γ
VSB = 0 V
0.5 0.5
( vSB + 2 φ F ) − ( 2 φF )
5
Allen and Holberg - CMOS Analog Circuit Design Page IV.1-6
x = v DS (20)
m = λ i'D (21)
Plot iD versus v DS , and measure the slope of the data in the saturation
region, and divide that value by the y-intercept to getλ.
Saturation region
Nonsaturation
region
iD
i'D m = λ i'D
v DS
Consider two transistors, with the same widths but different lengths,
operating in the nonsaturation region with the same vDS. The widths of the
transistors are assumed to be very large so that W ≅ Weff. The large-signal
model is given as
2
K' L W eff v
iD = L DS
(v - V )v -
T 0 D S 2 (23)
eff G S
6
Allen and Holberg - CMOS Analog Circuit Design Page IV.1-7
and
∂ID K' L W eff
= gm = VD S (24)
∂V GS L eff
The aspect ratios (W/L) for the two transistors are
W1
L1 + ∆L (25)
and
W2
(26)
L2 + ∆L
Implicit in Eqs. (25) and (26) is that ∆L is assumed to be the same for both
transistors. Combining Eq. (24) with Eqs. (25) and (26) gives
K' L W
gm1 = L + ∆ L v DS (27)
1
and
K' L W
gm2 = L + ∆ L v DS (28)
2
where W 1 = W 2 = W (and are assumed to equal the effective width). With
further algebraic manipulation of Eqs. (27) and (28), one can show that,
gm1 L2 + ∆L
= (29)
gm1 - gm2 L2 - L1
which further yields
(L 2 - L 1 ) g m1
L 2 + ∆L = L eff = g (30)
m1 - gm2
L2 and L1 known
gm1 and gm2 can be measured
Similarly for W eff :
(W 1 - W 2 )g m2
W 2 + ∆W = W eff = g (31)
m1 - gm2
Equation (31) is valid when two transistors have the same length but
different widths.
7
Allen and Holberg - CMOS Analog Circuit Design Page IV.1-8
One must be careful in determining ∆L (or ∆W) to make the lengths (or
widths) sufficiently different in order to avoid the numerical error due to
subtracting large numbers, and small enough that the transistor model
chosen is still valid for both transistors.
8
Allen and Holberg - CMOS Analog Circuit Design Page IV.3-1
µsCoxW v2
(v DS + γ v
iD = GS - V )v -
T DS 2 DS 2| φ F |
L
2γ
− 3 [(v DS + 2| φ F |) 1.5 - (2| φ F |)] 1.5 (1)
where W and L are effective electrical equivalents (dropping the subscript,
“eff”, for convenience).
(UCRIT)εsi UEXP
µs = µo (2)
Cox[v GS - V T - (UTRA)v DS ]
Eq. (2) holds when the denominator term in the brackets is less than unity.
Otherwise, µo = µs. To develop a procedure for extracting µo, consider
the case where mobility degradation effects are not being experienced, i.e.,
µs = µo, Eq. (1) can be rewritten in general as
iD = µ o f(C ox , W, L, v GS , V T , v DS , γ , 2|φ F |) (3)
This equation is a linear function of vGS and is in the familiar form of
y = mx + b (4)
where b = 0.
1
Allen and Holberg - CMOS Analog Circuit Design Page IV.3-2
Region of
variable
mobility
iD
Region of
constant
mobility
Weak-inversion
region
v GS
2γ
− 3 [(v DS + 2| φ F |) 1.5 - (2| φ F |)] 1.5 (1)
and
2
Allen and Holberg - CMOS Analog Circuit Design Page IV.3-3
ε si
f2 = (7)
[v GS - V T - (UTRA)v DS ]C o x
The units of f 1 and f 2 are FV2/cm2 and cm/V respectively. Notice that f 2
includes the parameter UTRA, which is an unknown. UTRA is disabled in
most SPICE models.
iD
y = log f (10)
1
m = UEXP (11)
b = log( µo) + UEXP[log(UCRIT)] (12)
By plotting Eq. (8) and measuring the slope, UEXP can be determined.
The y-intercept can be extracted from the plot and UCRIT can be
determined by back calculation given UEXP, µo, and the intercept, b.
3
Allen and Holberg - CMOS Analog Circuit Design Page IV.4-1
kT iC
v BE = q ln (1)
JSA E
and
iE
βdc = i − 1 (2)
B
AE is the cross-sectional area of the emitter-base junction of the BJT.
iE = iB (β dc + 1) (3)
Plot iB as a function of iE and measure the slope to determine β dc.
and
k T
b = y-intercept = − ln(JSA E ) (6)
q
Since the emitter area is known, JS can be determined directly.
1
Allen and Holberg - CMOS Analog Circuit Design Page IV.5-1
• Resistors
• Contact resistance
W w - Bias
RS = Rw (3)
Lw
where
Rn = resistance of narrow resistor (Ω)
1
Allen and Holberg - CMOS Analog Circuit Design Page IV.5-2
Rw
Rn
A Wn Ww F
Ln
Lw
B C D E
where
RwLn
k=R L (6)
n w
and
W n - Bias W w - Bias
RS = Rn = Rw (7)
Ln Lw
2
Allen and Holberg - CMOS Analog Circuit Design Page IV.5-3
10 squares
RA=220 Ω
20 squares
RB=420 Ω
R A = R 1 + 2R c; R1 = N 1RS (8)
and
R B = R 2 + 2R c; R2 = N 2RS (9)
N1 is the number of squares for R1
RS is the sheet resistivity in Ω/square
Rc is the contact resistance.
RB - RA
RS = N - N (10)
2 1
and
2R c = R A − N 1R S = R B − N 2R S (11)
3
Allen and Holberg - CMOS Analog Circuit Design Page IV.5-4
V1 − V2 V1 + V2
R= VBIAS =
IR 2
IR
V1 V2
VSS
27.0
26.5
Resistance (kΩ)
26.0
25.5
25.0
4
Allen and Holberg - CMOS Analog Circuit Design Page IV.5-5
Contact Resistance
Pad 1
Pad 3 Pad 4
Metal pads
Pad 2
Pad 1
RC
R
RC
Pad 4
R
RC
Pad 3
RM
RM
Pad 2
5
Allen and Holberg - CMOS Analog Circuit Design Page IV.5-1
V. Characterization of Capacitance
MOS capacitors
CGS, CGD, and CGB
Depletion capacitors
CDB and CSB
Interconnect capacitances
Cpoly-field, Cmetal-field, and Cmetal-poly (and perhaps multi-metal
capacitors
Normally SPICE calculates CDB and CSB using the areas of the drain and
source and the junction (depletion) capacitance, CJ (zero-bias value), that it
calculates internally from other model parameters. Two of these model
parameters, MJ and MJSW, are used to calculate the depletion capacitance
as a function of voltage across the capacitor.
1
Allen and Holberg - CMOS Analog Circuit Design Page IV.5-2
CGS0 and CGD0, are modeled in SPICE as a function of the device width,
while the capacitor CGB0 is per length of the device
Measure the CGS of a very wide transistor and divide the result by the
width in order to get CGS0 (per unit width).
Gate
2
Allen and Holberg - CMOS Analog Circuit Design Page IV.5-3
For very narrow transistors, the capacitance determined using the previous
technique will not be very accurate because of fringe field and other edge
effects at the edge of the transistor. In order to characterize CGS0 and
CGD0 for these narrow devices, a structure similar to that given in Fig.
B.6-1 can be used, substituting different device sizes. Such a structure is
given in Fig. B.6-3. The equations used to calculate the parasitic
capacitances are the same as those given in Eq. (1).
3
Allen and Holberg - CMOS Analog Circuit Design Page IV.5-4
CGB0
Drain
Gate overhang
Gate
Source
FOX FOX
Diffusion source
CGB Cpoly-field
4
Allen and Holberg - CMOS Analog Circuit Design Page IV.5-5
C BD and C BS
-MJ -MJSW
VJ VJ
CJ(VJ) = ACJ(0)1 + PB + PCJSW(0)1 + (4)
PB
where
VJ = the reverse bias voltage across the junction
Plotting log[CJ(VJ)] versus log[1 + VJ/PB] and determine the slope, −MJ,
and the Y intercept (where Y is the term on the left), Log[ACJ(0)].
Knowing the area of the capacitor, the calculation of the bottom junction
capacitance is straightforward.
5
Allen and Holberg - CMOS Analog Circuit Design Page V.0-1
V. CMOS SUBCIRCUITS
Contents
Organization
Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS
CIRCUITS
Chapter 5 Chapter 6
CMOS CMOS
Subcircuits Amplifiers
SIMPLE
WHAT IS A SUBCIRCUIT?
Example
Operational
Amplifier
Complex Circuits
Simple Circuits
Biasing Input Different- Second Gain Output
Circuits ial Amplifier Stage Stage
SWITCH PROPERTIES
Ideal Switch
RAB(on) = 0Ω
A B
RAB(off) = ∞
Nonideal Switch
CAB
IOFF
ROFF
VOFF
RON
+ -
A B
CAC CBC
C
RA + RB
VControl
-
Allen and Holberg - CMOS Analog Circuit Design Page V.1-2
Symbol
Bulk
A B A B
(S/D) (D/S)
C (G)
On Characteristics of A MOS Switch
K’W v D S
iD =
L (v G S - V T ) - 2 vDS
∂iD K’W
∂vDS = L v G S − V T − v D S
Thus,
∂vDS 1
RON = ∂i = K’W
D (v G S − V T − v D S )
L
1 1
ROFF ≈ i λ = I ≈∞
DS OFFλ
Allen and Holberg - CMOS Analog Circuit Design Page V.1-3
Assume the MOS switch connects to circuits and the analog signal can vary
from 0 to 5V. What are the voltages required at the terminals of the MOS switch
to make it work properly?
Bulk
(0 to 5V) (0 to 5V)
(S/D) (D/S) Circuit
Circuit
1 2
• The bulk voltage must be less than or equal to zero to insure that the
bulk-source and bulk-drain are reverse biased.
• The gate voltage must be greater than 5 + VT in order to turn the switch
on.
Therefore,
VBulk ≤ 0V
V G ≥ 5 + VT
(Remember that the larger the value of VSB , the larger VT)
Allen and Holberg - CMOS Analog Circuit Design Page V.1-4
100µA
V1 =10V
V1 Id V1=9V
60µA
V1 =8V
V1 =7V
V2
-5
20µA
Id
V1=2V
-20µA
V1=3V
V1=4V
-60µA
V1 =5V
V1 =6V
-100µA
-1V -0.6V -0.2V 0.2V 0.6V 1V
V2
100kΩ
W/L = 3µm/3µm
MOS Switch On Resistance
10kΩ
W/L = 15µm/3µm
W/L = 30µm/3µm
1kΩ
W/L = 150µm/3µm
100Ω
1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
Gate-Source Voltage
SPICE Input File:
MOS Switch On Resistance as a f(W/L)
M1 1 2 0 0 MNMOS W=3U L=3U
M2 1 2 0 0 MNMOS W=15U L=3U
M3 1 2 0 0 MNMOS W=30U L=3U
M4 1 2 0 0 MNMOS W=150U L=3U
.MODEL MNMOS NMOS VTO=0.75, KP=25U, LAMBDA=0.01, GAMMA=0.8
PHI=0.6
VDS 1 0 DC 0.001V
VGS 2 0 DC 0.0
.DC VGS 1 5 0.1
.PRINT DC ID(M1) ID(M2) ID(M3) ID(M4)
.PROBE
.END
Allen and Holberg - CMOS Analog Circuit Design Page V.1-6
Finite ON Resistance
φ1
RON
+ +
VSS + +
VIN C1 vC1 VIN C1 vC1
- -
- -
φ1 φ1
C2
+ +
+
vIN VSS VSS vOUT
CHold vOUT
- - -
Allen and Holberg - CMOS Analog Circuit Design Page V.1-7
EXAMPLES
vDS L/W
RON ≈ =
iD K'(VG-V S -V T)
106
RON =
25(10-1) = 4444Ω
VG
2. If V G=10V at t=0, what is the W/L
C2=10pF
value necessary to discharge C1 to
with 5% of its intial charge at +
+
t=0.1µS? Assume K'=25µA/V2 5V
and V TO = 1V. - C1=20pF
-
v(t) = 5exp(-t/RC) →
10-7 10-7
exp = 20 → RC =
RC ln(20)
10
Therefore, R = 6 x 103Ω
W
Gives L = 2.67
Allen and Holberg - CMOS Analog Circuit Design Page V.1-8
Distributed Model
CGDO CGSO
D S
RCH CGC=Cox
CGDO CGSO
Cox Cox
2 2
D S
RCH
Model:
vG dvG
dt
+
vIN CHold
-
Other Considerations:
• Source resistance effects the amount of charge shared between the drain and
the source.
• The maximum gate voltage before negative transition effects the amount of
charge injected.
Allen and Holberg - CMOS Analog Circuit Design Page V.1-10
To develop some intuition about the fast and slow cases, it is useful to model the
gave voltage as a piecewise constant waveform (a quantized waveform) and
consider the charge flow at each transition as illustrated below. In this figure, the
range of voltage at CL illustrated represent the period while the transistor is on.
In both cases, the quantized voltage step is the same, but the time between steps is
different. The voltage accross CL is observed to be an exponential whose time
constant is due to the channel resistance and channel capacitance and does not
change from fast case to slow case.
vCL
∆V
vGATE
Voltage
Time
(d)
∆V
Voltage
Time
(e)
Figure 4.1-10 (a) Illustration of slow ramp and (b) fast ramp using a quantized voltage
ramp to illustrate the effects due to the time constant of the channel resistance and capacitance.
Allen and Holberg - CMOS Analog Circuit Design Page V.1-11
φ1
CGS CGD
+
VSS +
VIN CBS CBD C1 vC1
-
-
Clock Feedthrough
Assume slow fall and rise times
φ1
Switch ON
∆φ1 Switch OFF Clock signal couples through CGD on the
rising part of signal when switch is off, but
φ1 VIN charges C1 to the right value regardless.
Clock signal couples through
CGS CGD CGD on the falling part of the
signal when the switch is off.
+
VSS +
VIN CBS C1 vC1
-
-
φ1
Switch ON
Switch OFF vIN+VT
φ2
Switch ON
VT Switch OFF
t t t t
φ1 1 2 3 4 φ2
C2
M1 M2
+ +
VSS C1 VSS vOUT
VIN
- -
assuming: CGS1=CGS2=CGD1=CGD2 = CG
CG
∆V C1 = − (VIN + VT)
CG+C1
CG CG
VC1 = VIN 1 − −V T
C1+CG CG+C1
CG
∆V C1 (t2-t3) = C +C VT
G 1
Allen and Holberg - CMOS Analog Circuit Design Page V.1-13
CG
VC1 = VIN 1−C +C
1 G
+
Once M2 turns on (at t3 ), all of the charge on C1 is transferred to C2.
C1 C1 CG
∆VO = −VC1 = −V IN 1 −
C2 C2 C1+CG
+
Between times at t3 and t4 additional charge is transferred to C1 from the
channel capacitance of M2.
Cch
∆V O
(t3-t4)= − (Vclk −V T)
C2
C1 CG Cch
∆V O = −V IN 1− − (Vclk − V T)
C2 C1+CG C2
C1
Ideally the output voltage change is −VIN so the error due to charge
C2
feedthrough is:
C1 CG Cch
∆V O (error) = VIN − (Vclk − V T)
C2 C1+CG C2
Allen and Holberg - CMOS Analog Circuit Design Page V.1-14
Consider the gate voltage traversing from VH to VL (e.g., 5.0 volts to 0.0 volts,
respectively) described in the time domain as
v G = V H − Ut (3)
V HT = V H − V S − V T (5)
the error (the difference between the desired voltage V S and the actual voltage,
VCL) due to charge injection can be described as
Allen and Holberg - CMOS Analog Circuit Design Page V.1-15
W · C G D 0 C c h
2 π U CL W · C G D 0
+
V error = + (V S + V T − V L ) (6)
CL 2β CL
W·CGD0 + C ch
β V HT W·CGD0
3
2
V error = V H T − 6U C + C (V S + V T − V L ) (8)
CL L L
Case 2
vG
Case 1
0.2 ns
10 ns
Time
Case 1:
The first step is to determine the value of U in the expression
vG = VH - Ut
For a transition from 5 volts to 0 volts in 0.2 ns, U = 25 × 109
In order to determine operating regime, the following relationship must be tested.
Allen and Holberg - CMOS Analog Circuit Design Page V.1-16
2 2
β VHT β VHT
2CL >> U for slow or 2CL << U for fast
Observin g that there is a backbias on the transistor switch effecting VT, VHT is
VHT = VH - VS - VT = 5 - 1 - 0.887 = 3.113
giving
2
β VHT 110×10-6× 3.1132
2CL = = 2.66 × 109 << 25 × 109 thus fast regime.
2 × 200f
Verror = 19.7 mV
Case 2:
The first step is to determine the value of U in the expression
v G = VH - Ut
For a transition from 5 volts to 0 volts in 10 ns, U = 5 × 108 thus indicating the slow regime
according to the following test
1.58×10-15
176×10-18 + 2 314×10-6 176×10-18
Verror = + (5 + 0.887 - 0 )
200×10-15 220×10-6 200×10-15
Verror = 10.95 mV
Allen and Holberg - CMOS Analog Circuit Design Page V.1-17
φ φ
W1 WD = W1
L1 LD 2L1
M1 MD
VSS VSS
vG
0V
C
+ +
vin > 0 vout
VSS
- -
vG
3VT
2VT
VT
t
ON OFF ON
Allen and Holberg - CMOS Analog Circuit Design Page V.1-18
CMOS SWITCHES
"Transmission Gate"
VSS
A B
VDD
Advantages -
1.) Larger dynamic range.
2.) Lower ON resistance.
Disadvantages -
1.) Requires complementary clock.
2.) Requires more area.
Allen and Holberg - CMOS Analog Circuit Design Page V.1-19
A B
+ VDD
VAB 1 µA
50µ
- 2µ
3kΩ
2.5kΩ
Switch On Resistance
VDD = 4V
2kΩ VDD = 4.5V
1.5kΩ VDD = 5V
1kΩ
0.5kΩ
0kΩ
0V 1V 2V 3V 4V 5V
VAB
SPICE File:
Simulation of the resistance of a CMOS transmission switch
M1 1 3 2 0 MNMOS L=2U W=50U
M2 1 0 2 3 MPMOS L=2U W=50U
.MODEL MNMOS NMOS VTO=0.75, KP=25U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5
.MODEL MPMOS PMOS VTO=-0.75, KP=10U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5
VDD 3 0
VAB 1 0
IA 2 0 DC 1U
.DC VAB 0 5 0.02 VDD 4 5 0.5
.PRINT DC V(1,2)
.END
Allen and Holberg - CMOS Analog Circuit Design Page V.1-20
If N-channel and P-channel devices are “resistively” scaled (i.e., sized to have the
same conductance at equivalent terminal conditions) the resistance versus voltage
(common mode) will appear as shown below.
280
270
5v
260
250 Id
R
5v
240
230 V
220 0.1
210
0 1 2 3 4 5
V
Allen and Holberg - CMOS Analog Circuit Design Page V.1-21
Example
VDD
M1 φA
φA
CPump M6
M4 +
M7 M8
φA
φB VDBL
M2
CHold
M3
φB φA φB
M5 -
VSS
φA
φB
Operation:
DC K'W
i = iD = ( ) [ vGS - VT ]2
2L
β
= 2 ( vGS - VT ) 2 , ignore λ
or
v 2iD
v = vDS = vGS = VT +
Small signal β
i
G D
+
v gm v gmbs vbs rds
-
S S
v 1 1
If VBS = 0 , then ROUT = i = g +g ≈ g
M DS M
If V BS ≠ 0?
VDD
M2
Vout
M1
VSS
β2
β1 v DS2 - V T 2 + VT1
vDS1 =
where
vGS1 = vDS1 and v GS2 = vDS2
Example :
β
iD1 = ( vGS - VT ) 2
2
β 1 = 4.0 µA/V2 β 2 = 11.1 µA/V2
K'n = 17 µA/V2 K'p = 8 µA/V2
1
then ( W/L )1 = 4.25 and ( W/L )2 = 1.34
Allen and Holberg - CMOS Analog Circuit Design Page V.2-3
Concept:
I
I
- +
VC I1 I2
+
M1 vDS M2 + R
VC
- -
Consider :
Assume both devices are non-saturated
2
v DS
I1 = β 1 (v DS + V C - V T )v DS -
2
2
v DS
I2 = β 2 (V C - V T )v DS - 2
2 2
v DS v DS
I = I1 + I2 = β v D S 2 + (V C - V T )v D S - 2 + (V C - V T )v D S - 2
1
I = 2β(VC - VT)vDS R = 2β(V - V )
C T
Allen and Holberg - CMOS Analog Circuit Design Page V.2-4
Implementation :
VDD
+
V
M3A - C M3B
S + M1 +
VGS S
VGS
S D -
M2A G- i M2 G M2B
i
- vDS +
R
VSS
Allen and Holberg - CMOS Analog Circuit Design Page V.2-5
Voltage-Current Characteristic :
2mA
Vc=7V
6V
5V
1mA
W=15u 4V
L=3u 3V
I(VSENSE)
VBS=-5.0V
0
-1mA
-2mA
-2 -1 0 1 2
VDS
NMOS parallel transistor realization
M1 2 1 0 5 MNMOS W=15U L=3U
M2 2 4 0 5 MNMOS W=15U L=3U
.MODEL MNMOS NMOS VTO=0.75, KP=25U, LAMBDA=0.01, GAMMA=0.8
PHI=0.6
VC 1 2
E1 4 0 1 2 1.0
VSENSE 10 2 DC 0
VDS 10 0
VSS 5 0 DC -5
.DC VDS -2.0 2.0 .2 VC 3 7 1
.PRINT DC I(VSENSE)
.PROBE
.END
Allen and Holberg - CMOS Analog Circuit Design Page V.2-6
vAB
iAB V DD
M2A M2B
+ +
M1A
VC
- VC
M1B
-
M3A M3B
+ V
- C
V SS
VAB
Allen and Holberg - CMOS Analog Circuit Design Page V.2-7
VC
i1 R i1
v1 + v1 +
v2 v2
v2 v2
- - v1 -
- v1
i2 i2
R
VC
Assume the MOSFET's are in the non-saturation region
1
i1 = β(V C - v 2 -V T )(v 1 - v 2 ) - 2 (v 1 - v 2 ) 2
1
i2 = β(V C - v 2 -V T )(-v 1 - v 2 ) - (-v 1 - v 2 ) 2
2
Rewrite as
1
i1 = β(V C - v 2 -V T )(v 1 - v 2 ) - (v 1 2 - 2v 1 v 2 + v 2 2 )
2
1
i2 = β(V C - v 2 -V T )(-v 1 - v 2 ) - (v 1 2 + 2v 1 v 2 + v 2 2 )
2
1
i1 - i2 = β(V C -v 2 -V T )(2v 1 ) - (v12-2v1v2+v22-v12-2v1v2-v22)
2
i1 - i 2 = 2β [ (VC - VT)v1 - 2v1v2 + 2v1v2 ]
VC
i1 r ac/2 i1
v1 v2 v1 v2
r ac/2 VCC
- v1 v2 - v1 v2
i2 R i2
VC
Voltage-Current Characteristics
1.0mA
VC= 7V
0.6mA 6V
5V
4V
0.2mA 3V
ID(M1)
- 0.2mA
- 0.6mA
- 1.0mA
-2 -1 0 1 2
V1
Single MOSFET Differential Resistor Realization
M1 1 2 3 4 MNMOS1 W=15U L=3U
M2 5 2 3 4 MNMOS1 W=15U L=3U
VC 2 0
VCC 4 0 DC -5V
V1 1 0
E1 5 0 1 0 -1
.MODEL MNMOS1 NMOS VTO=0.75 KP=25U
+LAMBDA=0.01 GAMMA=0.8 PHI=0.6
.DC V1 -2.0 2.0 0.2 VC 3 7 1
.PRINT DC ID(M1)
.PROBE
.END
Allen and Holberg - CMOS Analog Circuit Design Page V.2-9
v1-v2 v1-v2 1
Rin = = =
i1-i2 β(VC1-VC2)(v1-v2) KW
(VC1-VC2)
L
1
or R i n = KW v1 ,v 2 ≤ min [(V C1-VT),(VC2-VT)]
(VC1-VC2)
L
Allen and Holberg - CMOS Analog Circuit Design Page V.2-10
VC1
iD1 M1 i1
v1 v3
iD2 VSS
i1 r ac/2
v1 v3 M2
r ac/2 VC2
v2 v4
i2 R iD3 M3
iD4 VSS
v2 v4
M4 i2
VC1
Voltage-Current Characteristics
150uA
VC2 = 6V Double MOSFET Differential Resistor Realization
M1 1 2 3 4 MNMOS1 W=3U L=3U
5V
100uA M2 1 5 8 4 MNMOS1 W=3U L=3U
VBC =-5V
4V M3 6 5 3 4 MNMOS1 W=3U L=3U
V3 =0V M4 6 2 8 4 MNMOS1 W=3U L=3U
VC1 =7V 3V
50uA VSENSE 3 8 DC 0
2V
I(VSENSE)
VC1 2 0 DC 7V
VC2 5 0
0 VSS 4 0 DC -5V
V12 1 6
.MODEL MNMOS1 NMOS VTO=0.75 KP=25U
- 50uA
+LAMBDA=0.01 GAMMA=0.8 PHI=0.6
.DC V12 -3 3 0.2 VC2 2 6 1
.PRINT DC I(VSENSE))
- 100uA
.PROBE
.END
- 150uA
-3 -2 -1 0 1 2 3
V1-V2
Allen and Holberg - CMOS Analog Circuit Design Page V.2-11
|v1| < VC - VT
Single-MOSFET,
Good VC or W/L vBULK < -v1
differential resistor
Differential around v1
v1, v2 < min(VC1-VT,
Double-MOSFET, Very Good VC1 - V C2 or VC2-VT)
differential resistor W/L vBULK < min(v1,v2)
Transresistance only
Allen and Holberg - CMOS Analog Circuit Design Page V.3-1
1). Minimum voltage (vMIN) across sink or source for which the
current is no longer constant.
2). Output resistance which is a measure of the "flatness" of the
current sink or source.
VDD
iD VG = V GG
iD +
v
VGG
- vMIN
v
0
VDD iD VG = V GG
VGG
iD
+
v vMIN
0
- v
VDD
0
1
rOUT = λI
D
vMIN = vDS(SAT.) = vON where vON = vGS - VT
Allen and Holberg - CMOS Analog Circuit Design Page V.3-2
G B D
D
+ +
vgs vbs gmvgs gmbsvbs rds
G B
- -
S S S
2K'WID
gm = L
gm γ
gmbs =
2 2φ F + |V BS |
1 1
r ds ≈ g = λI
ds D
Allen and Holberg - CMOS Analog Circuit Design Page V.3-3
MOS
+
i OUT
M2 iout +
r ds2
gm2 vgs2
vOUT gmbs2 vbs2 vout
+
- r +
VGG v S2 r -
- -
Loop equation:
vout = [iout - (g m2vgs2 + gmbs2vbs2)]r ds2 + iout r
But, v gs2 = -vs2 and vbs2 = - vs2.
vout = [iout + gm2vs2 + gmbs2vs2]rds2 + iout r
Replace vs2 by i outr-
vout = iout [ rds2 + gm2 rds2r + gmbs2rds2r + r ]
Therefore,
rout = rds2 + r [1 + gm2 rds2 + gmbs2rds2]
Continuing
rout ≅ rgm2 rds2
MOS
M3 M1 vout
-
+
r ds1 vS2
gm1vgs1 - -
NMOS Cascode-
1mA
Slope = 1/R o
0.75mA iO
+
+
iO 0.5mA vGS2
-
vO
0.25mA +
vGS1
- -
VMIN
0mA
0V 2V 4V 6V 8V 10V
vO
Allen and Holberg - CMOS Analog Circuit Design Page V.3-5
iD2
+ M2
iD1 iD2 vGS2
-
M1 + + M2
vGS1 vGS2 iD1
- -
+
vGS1 M1
S = W/L
-
Assume that M1 and M2 are matched but may not have the same W/L ratios.
Strictly speaking, absolute matching requires that vDS be equal for two matched
devices.
Allen and Holberg - CMOS Analog Circuit Design Page V.3-6
High-Swing Cascode
IREF IOUT
2VT + 2VON IOUT
VOUT(sat)
+
M4 M2
+
VT + VON
VOUT
-
M1 +
M3 +
VT + VON
VT + VON -
- - VOUT
0 VT + 2VON
Part of v G S Part of v G S to
vGS = VON + VT = to achieve +
drain current enhance the channel
iD
ID
vGS
VT VT+VON
Circuit Which Reduces the Value of Vout(sat) of the Cascode Current Sink
iREF iout
iREF
M6 M4 +
1/4 1/1
+ + 1/1
M2
VT + 2VON VT + VON
- - +
2VT + 3VON VT + VON vOUT
-
M3 VT + 2VON M1
+
M5 VON
+ 1/1 -
1/1 VT + VON 1/1
- -
iD
iOUT W=1 W =1
vOUT(sat) L 1 L 4
ID
vOUT vGS
0 2V ON 0 VT VT + VON VT + 2VON
K'W K'W
iD = 2 (v - VT ) 2 = 2
L GS 2 L (V ON )
Allen and Holberg - CMOS Analog Circuit Design Page V.3-8
iREF iREF
iO
M5 1
M4
+
1/4 VT + VON
-
M1 M2
+
VON
+ -
1 VT + VON 1
-
Assume (W/L)1 = (W/L)2 = (W/L)4 = 4(W/L)5 values are identical and ignore
bulk effects.
Let I = IO
REF
2I REF
VGS1 = + VT = VON + VT
W1
K’ L
1
and
2I REF
V GS5 = + VT
W5
K’ L
5
2I REF 2I REF
V GS5 = + VT = 2 + V T = 2 VON + VT
W1 W1
K’ 4L K’ L
1 1
Allen and Holberg - CMOS Analog Circuit Design Page V.3-9
VDS1 = V DS2 = V ON
which gives a minimum output voltage while keeping all devices in saturation of
v M I N = 2 VO N
Output Plot:
1000µA
750µA
ID(M4)
500µA
250µA
0µA
0V 1V 2V 3V 4V 5V
VOUT
Allen and Holberg - CMOS Analog Circuit Design Page V.3-10
iREF iREF
V T + 2VON iO
+ M3 1 M5 1
M4
VT
- + +
V T + VON 1/4 VT + V ON
- -
M1 M2
+ +
VON V ON
- + -
1 V T + V ON 1
-
Circuit Diagram
VDD VDD
iOUT iD3
IB2 RB2
M3 +
vGS3
IB1
M4
vOUT Iout
M1 M2
- vDS3
VDS3 (min) VDS3 (sat)
Principle of operation:
As v OUT decreases, M3 will enter the non-saturation region and
iOUT will begin to decrease. However, this causes a decrease in the gate-
source voltage of M4 which causes an increase in the gate voltage of M3.
The minimum value of vOUT is determined by the gate-source voltage of
M4 and Vdsat of M3. Assume that all devices are in saturation.
2IB2 2Iout
vOUT(min) =
K'(W/L)4 + K'(W/L)3 + VT4
Allen and Holberg - CMOS Analog Circuit Design Page V.3-12
g m 2r3
r out = r ds3 g m3 r ds2 g m4 (r ds4 ||R B2 ) =
2
Example
K' N = 25µA/V2, λ = 0.01, IB1 = IB2 = 100µA, all transistors with
minimum geometry (W = 3µm, L=3µm), and RB2 = rds, we get
rds = 1MΩ and gm = 70.7µmho
rout ≈ (1MΩ)(70.7µmho)((1MΩ)(70.7µmho)(1MΩ||1MΩ)= 2.5GΩ!!!
Allen and Holberg - CMOS Analog Circuit Design Page V.3-13
160µA
140µA IB1=150µA
120µA
IB1=125µA
100µA
IB1=100µA
iOUT 80µA
60µA IB1=75µA
40µA IB1=50µA
20µA
0µA
0 1 2 3 4 5
vOUT
SPICE Input File
CMOS Regulated Cascode Current Sink
VDD 6 0 DC 5.0
IB1 6 4 DC 25U
VOUT 1 0 DC 5.0
M1 4 4 0 0 MNMOS1 W=15U L=3U
M2 3 4 0 0 MNMOS1 W=15U L=3U
M3 1 2 3 0 MNMOS1 W=30U L=3U
M4 2 3 0 0 MNMOS1 W=15U L=3U
M5 5 4 0 0 MNMOS1 W=15U L=3U
M6 5 5 6 6 MPMOS1 W=15U L=3U
M7 2 5 6 6 MPMOS1 W=6U L=3U
.MODEL MNMOS1 NMOS VTO=0.75 KP=25U
+LAMBDA=0.01 GAMMA=0.8 PHI=0.6
.MODEL MPMOS1 PMOS VTO=-0.75 KP=8U
+LAMBDA=0.02 GAMMA=0.4 PHI=0.6
.DC VOUT 5 0 0.1 IB1 50U 150U 25U
.OP
.PRINT DC ID(M3)
.PROBE
.END
Allen and Holberg - CMOS Analog Circuit Design Page V.3-14
R in Rout
CURRENT
iI iO
MIRROR/
+ +
AMPLIFIER
vI vO
- -
Ideally,
iO = A I iI
Rin ≈ 0 Rout ≈ ∞
Graphical Characterization
iI iO
slope = 1/Rin
slope = 1/Rout
II
IO
vI vO
vMIN vMIN
INPUT iO OUTPUT
AI
1
iI
TRANSFER
Allen and Holberg - CMOS Analog Circuit Design Page V.4-2
Sources of Errors
iI iO
CURRENT + +
iI iO
MIRROR/ vDS1 M1 M2
+ vDS2
AMPLIFIER vGS
- - -
In general,
iO W2L1 1+λvDS2
=
iI W1L2 1+λvDS1
If vDS1 = vDS2,
iO W 2L 1
iI = W1L2
Circuit -
- 1)x100%
10
λ = 0.02
iI iO 8
λ = 0.015
DS1
1 + λv DS2
6
+ M1 M2 + ( 1 + λv
vDS1 v DS2 4
+
- vGS - λ = 0.01
- 2
Ratio Error
v SS 0
0V 1V 2V 3V 4V 5V
VDS1-VDS2
Used to measure λ -
iO 1+ λ v D S 2 S1
=
iI 1+ λ v D S 1 S2
iO 1+10λ 0.5
∴ = 1.501 = ---> λ = 8.5 = 0.059
iI 1+ λ
Allen and Holberg - CMOS Analog Circuit Design Page V.4-4
Neglect λ effects
iD1 iD2
iO = iD2 = β2(vGS2-VT2)2
iI iD1 β1(vGS1-VT1)2
M1 + + M2
vGS1 vGS2 (vDS2 > vGS2 - VT1)
- -
β1 + β2
Define: ∆β = β 2 - β 1 and β= 2
VT1+VT2
∆VT = V T2 - V T1 and VT = 2
∆β ∆β ∆VT
∴ β1 = β - , β 2 = β + , V T1 = V T -
2 2 2
∆VT
and V T2 = V T + 2
Thus,
∆β
β+ v GS - vT -
∆V T2 ∆β 1-2(v∆V-V
T 2
iO 2 2
1 +
2β GS T)
iI = ∆β ∆β
∆V T 2 = ∆VT
β- v GS - v T +
2β 2(vGS-VT)
1 - 1+
2 2
iO ∆β 2∆VT
iI ≈ 1 + β - (v GS - V T ) ,
∆β ± ∆VT
≈ 5% , (v = ± 10%
β GS - V T )
iO
∴
iI ≈ 1 ± 0.05 - (± 0.2) = 1 ± 0.15
= 1 ± 0.25 if β and VT are correlated
Allen and Holberg - CMOS Analog Circuit Design Page V.4-5
Illustration
7
iO - 1)100%
6
II = 1uA
5
iI
RATIO ERROR (
3
II = 5uA
2
II = 10uA
1 II = 50uA
1 2 3 4 5 6 7 8 9 10
∆VT(mV)
Allen and Holberg - CMOS Analog Circuit Design Page V.4-6
iI iO
iI iO
M1 M2
M2
V SS
VSS Layou
t with correction technique -
iI iO
iI iO
M2 M2 M2 M2 M2
M1 M2 M2 M2 M2 M2 a b c d e
d M1
a b c e
VSS
VSS
Allen and Holberg - CMOS Analog Circuit Design Page V.4-7
• Simple mirror
• Cascode current mirror
• Wilson current mirror
iI = 60uA
60uA
iI = 50uA Current mirrors and amplifiers
.MODEL MNMOS1 NMOS VTO=0.75 KP=25U
+LAMBDA=0.01 GAMMA=0.8 PHI=0.6
iI = 40uA M1 1 1 0 0 MNMOS1 W=3U L=3U
40uA
M2 3 1 0 0 MNMOS1 W=3U L=3U
iI = 30uA IIN 0 1
iOUT VOUT 3 0
.DC VOUT 0 5 0.1
iI = 20uA +IIN 0 60U 10U
20uA
.PRINT DC ID(M2)
iI = 10uA .PROBE
.END
0
0 1 2 3 4 5
vOUT
iI iO
3u 3u
3u 3u +
vO
M1 M2 -
Allen and Holberg - CMOS Analog Circuit Design Page V.4-8
M3 M4 40uA
VOUT 4 0
.DC VOUT 0 5 0.1 iI = 40uA
+ IIN 10U 60U 10U
.PRINT DC ID(M4)
iOUT .PROBE
.END
iI = 30uA
iI = 20uA
20uA
M1 M2 iI = 10uA
0
VSS
0 1 2 3 4 5
vOUT
Example of Small Signal Output Resistance Calculation -
ii
io
+ + +
v3 rds3 v4 rds4
gm3 v3 gm4 (v3 +v1 -v2 )
- - gmbs v2
v1 =v3 =0 io vo
+ +
v1 rds1 v2 rds2
gm1 v1 gm2 v1
- - -
Principle of Operation:
Series negative feedback increase output resistance
1. Assume input current is constant and that there is high resistance to
ground from the gate of M3 or drain of M1.
2. A positive increase in output current causes an increase in vGS2 .
3. The increase in vGS2 causes an increase in vGS1 .
4. The increase in vGS1 causes an increase in iD1.
5. If the input current is constant, then the current through the resistance to
ground from the gate of M3 or the drain of M1 decreases resulting in a decrease
in vGS3.
6. A decrease in v GS3 causes a decrease in the output current opposing the
assumed increase in step 2.
Allen and Holberg - CMOS Analog Circuit Design Page V.4-10
iout
+ +
iin=0 v3 rds3
- gm3(v1-v2) gmbs3v2
vout
+ +
gm1v2 rds1 v1 rds2 v2
- gm2v2 - -
rds2
v2 = iout 1 + g m2 r d s 2
Iin Iout
M4 M1
Additional diode-connected
M3 M2 transistor equalizes the
drain-source voltage drops
of transistors M2 and M3
SPICE simulation
0 1 2 3 4 5
Vout
Allen and Holberg - CMOS Analog Circuit Design Page V.4-12
VDD iOUT
IB M4 +
IIN
M3
+ vOUT
vGS4
M1 - M2
-
VSS
Small Signal Equivalent Model (gmbs effects ignored) -
iout
+
rds4
gm4vgs4
v4
+ vout
rds3 rds2 v3
g m3 v3
- -
Output Minimum
Current Mirror Accuracy Resistance Voltage
Simple Poor (Lambda) r ds VON
Cascode
Allen and Holberg - CMOS Analog Circuit Design Page V.5-1
Introduction
i
Voltage Reference
Iref
Current Reference
v
Vref
Allen and Holberg - CMOS Analog Circuit Design Page V.5-2
Concept of Sensitivity
Definition
Sensitivity is a measure of dependence of Vref (Iref) upon a parameter or
variable x which influences Vref (Iref).
∂Vref
Vref
Vref x ∂Vref
S =
∂x =
Vref ∂x
x x
where
x = VDD or temperature
Application of Sensitivity
Vref = S
x
x
For example, if the sensitivity is 1, then a 10% change in x will cause a 10%
change in V ref.
Vref
Ideally, S →0
x
Allen and Holberg - CMOS Analog Circuit Design Page V.5-3
Objective is to minimize,
∂Vref
Vref
Vref
S = ∂VD D
V DD
VDD
Passive Divider
Accuracy is approximately equivalent to 6 bits (1/64).
VDD
RA
V1
I RB
V2
RC
VSS
Active Dividers
V3
VDD VDD
M3
V2
M2 M2 M2
V1
+ +
M1 M1 Vref M1 Vref
- -
Allen and Holberg - CMOS Analog Circuit Design Page V.5-5
VCC
+ V CC - V B E VCC
If I = ≈ R
VREF R
- VCC
V REF ≈ V t ln
RI
s
Sensitivity:
VREF
1
S =
VCC
V CC ln RI
s
VREF
If VCC = 10V, R = 10 kΩ, and Is = 10-15A, then S = 0.0362.
V CC
Modifying the Value of VREF
VCC
If β >> 1, then VREF ≈ IR1 (R 1+R2)
I VBE
R replacing IR1by
R1 gives,
+ R 1 +R 2
IR1 R1 VREF ≈ V BE
R1
VREF or
R2
-
R1+R2 VCC
V REF ≈ Vt ln
R1 RIs
Allen and Holberg - CMOS Analog Circuit Design Page V.5-6
VDD
2(VDD-V REF)
VREF = VGS = VT +
βR
R I
1 2(VDD-VT) 1
V REF = VT − + + 2 2
+ βR βR β R
VREF
Sensitivity:
-
V REF
VDD 1
S = V 1 + βR(V
REF
REF - V T )
VDD
If V DD = 10V, W/L = 10, R = 100kΩ and using the results of Table 3.1-2 gives
VREF
V DD
R 1 +R 2
R I
VREF ≈ V GS
R2
+
IR1 R1
V REF
R2
-
Allen and Holberg - CMOS Analog Circuit Design Page V.5-7
VDD
M4
RB M3 M5
iOUT
ID1 = I1 ID2 = I2
M6
M2
M8 M1
Principle: I2
If M3 = M4, then
I 1 = I2 (1)
also,
Eq. (2) Desired
2I1 operating
VGS1 = VT1 +
KNS1 = I2R point
therefore,
Eq. (1)
VT1 1 2I1
R + R
I2 = (2)
KNS1
Undesired operating point
Allen and Holberg - CMOS Analog Circuit Design Page V.5-8
2I1
I2R = VT1 +
β1
1 + λPV G S 4
I 2 = I1
1 + λ P (V D D - V DS1 )
2I1
I1R(1 + λPVGS4) = [1 + λP(V DD-V DS1)]
β1
Differentiating with respect to VDD and assuming the VDS1 and VGS4 are
constant gives (IOUT = I1),
2I1
IOUT 20VDD λPV T1 +
β1
S =
1 + λ P (V D D - V DS1 )
VDD IOUTR(1 + λ P V GS4 ) -
2β1I1
Allen and Holberg - CMOS Analog Circuit Design Page V.5-9
VGS4 = 1.50V, VT2 = 1.085V, VGS2 = 1.545V, and VDS1 = 2.795V which
gives
IOUT
∆IOUT/IOUT
S = 0.08 = ∆V /V
DD DD
VDD
∆V DD
If ∆VDD = 6V - 4V = 2V, then ∆IOUT = 0.08 I OUT V = 3.2µA
DD
SPICE Results:
120µA
100µA
∆IOUT ≈ 2.8µA for ∆VDD 4V →6V
80µA
60µA
IOUT
40µA
20µA
0µA
0V 2V 4V 6V 8V 10V
VDD
Allen and Holberg - CMOS Analog Circuit Design Page V.5-10
VDD
M4
RB M3 M5
iOUT
ID1 = I1 ID2 = I2
M6
M1 M2
M8 Q1
R
VBE1
I2 ≈ R = I5
V = I2R ≈ V BE1
Allen and Holberg - CMOS Analog Circuit Design Page V.5-11
Objective
Minimize the fractional temperature coefficient which is defined as
1 ∂Vref
T CF = V ∂T parts per million per °C or ppm/°C
ref
PN Junction:
i ≈ I s exp
v
Vt
∂I ∂(ln I s ) 3 V GO V GO
-V GO I1s ∂Ts =
∂T
= T + TV ≈ TV
t t
I s = KT 3 exp V
t
dvBE V BE - V G O
dT ≈ = -2mV/°C at room temperature
T
(VGO = 1.205 V and is called the bandgap voltage)
dVGS dVT ID
2L d
dT = dT + WCox dT µ o
dV G S 3 V GS - V T
= - α +
dT 4 T
Allen and Holberg - CMOS Analog Circuit Design Page V.5-12
VDD
I
R
VREF = VBE = kT ln I = Vt ln I
q Is Is
V DD - v B E V DD VDD
I= ≈ R -------> V REF = V t ln RI
R s
1 dV REF V REF - V G O Vt dR
TCF =
VREF dT = - V
TVREF REF RdT
VDD
R I
VREF
1 2(VDD−VT) 1
V R E F = V T − βR + + 2 2
βR β R
V DD − V REF 1.5 1 d R
−α + − R dT
1 dV REF 1 2βR T
TCF = V =
REF dT VREF
1 +
1
2βR (V DD − V REF )
Allen and Holberg - CMOS Analog Circuit Design Page V.5-14
Example
VREF = 1.281 V
dR
= +1500 ppm/°C
RdT
M4
RB M3 M5
iOUT
I D1 = I1 I D2 = I2
M6
M2
M8 M1
2ID1 L
VGS1 + VT V ON + V T
K'W
ID2 = R = = = ID1 = IOUT
R R
Assuming that VON is constant as a function of temperature because of the
bootstrapped current reference, then
1 dVT 1 dR -α 1 dR
∴ TCF = - R dT VT - R dT
=
VT dT
If R is a polysilicon resistor, then
-2.3 x 10 -3
TC F = 1 - 1.5x10 -3 = -3800 ppm/°C
If R is an implanted resistor, then
-2.3 x 10 -3
TC F = - 0.4x10-3 = -2700 ppm/°C
1
Allen and Holberg - CMOS Analog Circuit Design Page V.5-16
VDD
M4
RB M3 M5
iOUT
ID1 = I1 ID2 = I2
M6
M1 M2
M8 Q1
R
vBE1 1 dv BE 1 dR
I2 ≈ R -----> TCF = v - R dT
BE dT
V.6 - SUMMARY
• The circuits in this chapter represent the first level of building blocks in
analog circuit design.
• The MOS transistor makes a good switch and a variable resistor with
reasonable ranges of linearity in certain applications.
• Primary switch imperfection is clock feedthrough. In order for switches to
be used with lower power supplies, VT must be decreased.
• The primary characteristics defining a current sink or source are VMIN and
Rout. V MIN → 0 and Rout → ∞. Typically the product of VMIN times Rout
is a constant in most designs.
• Current mirrors are characterized by:
Gain accuracy
Gain linearity
VMIN on output
Rout
Rin
Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS
CIRCUITS
Chapter 5 Chapter 6
CMOS CMOS
Subcircuits Amplifiers
SIMPLE
Chapter 2 Chapter 3
CMOS Device Chapter 4 Device
CMOS
Technology Modeling Characterization
DEVICES
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-1
CHARACTERIZATION OF AMPLIFIERS
VDD
VGG2
M2 M2 M2
+
+ + +
M1 M1 M1
vOUT + vOUT vIN vOUT
+
vIN vIN
- - - - - -
Active Current
Load Push-pull
Source
Inverter inverter
Inverter
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-3
5V
1.2
v IN=5V
W1 15µm +
0.6 vIN =3.5V
=
L1 3µm
M1
0.4 vIN=3V
+ vOUT
vIN=2.5V
0.2 vIN=1V v IN=2V v IN
vIN =1.5V - -
0
0 1 2 3 4 5
v OUT 5
3
vOUT
2
0
0 1 2 3 4 5
v IN
Minimum: vIN M1
Assume v IN = VDD, M1 active,
VSS
M2 saturated, and VT1 = VT2 = VT.
vDS1 2
M1: iD = β1(vGS1 −VT)vDS1 −
2
(v OUT−VSS)2
= β1 (VDD−VSS−VT)(vOUT−VSS)−
2
β2 β2 β2
M2: iD = 2 (vGS −VT) = 2 (VDD−vOUT−VT) = 2 (vOUT+VT−VDD)2
2 2
β2
iD = 2 (vOUT −VSS+VSS+VT−VDD)2
β2
= 2 (vOUT−VSS)−(VDD −VSS−VT)2
β2 β2 β2
1 + vOUT '2 − 2VX 1 + vOUT ' + V X2 = 0
β 1 β 1 β 1
β2/β1
vOUT' − 2VX vOUT' + 1+β /β VX2 = 0
2
2 1
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-5
β2/β1
1 − 1+β2/β1 = VX 1 −
1
∴ vOUT' = VX1 ±
1 + β 2 /β 1
V D D − V SS − V T
v O U T (min.) = V D D − V T −
1 + β 2 /β 1
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-6
Interpretation of vOUT(min.)
1 + β
1
VDD = −VSS = 5V
VT = 1V
vOUT
5
3 v MAX
1
β1
0
0.1 1 10 β2
-1
v MIN
-3
-5
β1
Gain ~ β2
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-7
S2=B2
W 1/L1 vout
If vin = −6.67 using the parameters of Table 3.1-2
= 20, then
W2/L2
1 1
rout = g ≈
ds1 + g ds2 + g m 2 gm2
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-8
VDD VDD
VGG M2 M2
I I
vOUT vIN vOUT
vIN M1 M1
V SS V SS
Inverter with current source load Push-pull, inverter
M2 I
M1
vIN = V SS
vIN = VDD
.8V SS
.8V DD
.6V SS
.6V DD
.4VSS .4V DD
I
.2VSS J .2VDD
K H G
0 F=F' 0
E' D'
.2VDD C=C' .2V SS
.4VDD E B=B'.4V SS
D .6V SS vOUT
VSS A=A'
K' J' I' H'
G' .5VSS 0 .5VDD V DD
Large signal transfer characteristics of inverter with a current source and
push pull inverter
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-9
vOUT
.4VSS G
H
.6VSS I J
K
.8VSS G'
Advantages:
1. High gain.
2. Large output signal swing.
3. Large current sink and source capability in push pull inverter.
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-10
Circuit:
VDD
M2
I
vIN vOUT
M1
VSS
PSPICE Characteristics:
6
M2 linear
4
Current in M2 saturated
M1 or M2
2 M1 linear 100 µA
voltage
transfer
curve
v OUT
-6
-5 -3 -1 0 1 3 5
vIN
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-11
VDD
VGG M2
I
vOUT
vIN M1
v OUT(max.) ≈ V D D VSS
β2 VDD−VGG−VT2
vOUT(min.) = VDD −V T1−(V DD −V SS−V T1) 1 − β V −V −V
1 DD SS T1
VDD
M2
I
vIN vOUT
M1
v OUT(max.) ≈ V D D VSS
v OUT(min.) ≈ V SS
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-12
Model
+ +
- -
vOUT
vin = −328 for the push-pull inverter (L=10 µm)
1
rout =
g ds1 + g ds2
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-13
log AV
1000
100
weak
inversion
10 strong
inversion
1 ID
0.1µA 1µA 10µA 100µA 1000µA
Push-Pull: -1036 W
L = 1, L=10 µm
Current source load: -615
Current sink load: -422
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-14
General Configuration
VDD
C GS2
C GD1
X M2 C BD2
C GD2 + +
vin g m vin R CT v out
CGD1 C BD1 CL - -
v in M1
VSS
(a) (b)
(a) General configuration of an inverter illustrating parasitic capacitances.
(b) Small signal model of (a)
CGD1 and CGD2 are overlap capacitances
CBD1 and C BD2 are the bulk-drain capacitances
CL is the load capacitance seen by the inverter
Frequency Response
vOUT −g m Rω 1(1− s/z) 1 gm
, ω 1 = RC and z = C
vIN = s + ω 1 GD1
1
R = g +g +g (gm2 = 0 for push pull and current source inverters)
ds1 ds2 m2
C ≈ CGD1+CGS2+CBD1+CBD2+CL (Active load inverter)
C ≈ CGD1+CGD2+CBD1+CBD2+CL (Current source & push-pull inverter)
if g mR >> 1
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-15
Example:
Find the −3dB frequency for the CMOS inverter using a current
source load and the CMOS push pull inverter assuming that iD = 1µA,
CGD1=CGD2=0.2pF and CBD1=CBD2=0.5pF
W1 W2
Using the parameters of Table 3.1-2 and assuming that
L1 = L2 =1
Gives,
For the active load CMOS inverter,
gm2
ω-3dB = C = 3.124x10 -6 rads/sec or 512KHz
For the push pull or current source CMOS inverter,
g gd1 + g ds2
ω -3dB = = 14.3x10 3 rads/sec or 2.27 KHz
C
gm1
z=C = 29.155 Mrads/sec or 4.64 MHz
GD1
The reason for the difference is the higher output resistance of the
push pull or current source CMOS inverters
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-16
Noise Calculation
RL
RS
i 2d RL i 2L
v IN + RS
-
2
We wish to determine the equivalent input noise voltage, vn as shown
below:
RL
v2n
RS
2 8
id = KTg m (A2/Hz)
3
2 4KT 2
iL =
RL (A /Hz)
Comments:
1.) 1/f noise has been ignored.
2.) Resistors are noise-free, they are used to show topological aspects.
Can repeat the noise analysis for the resistors if desired.
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-17
vIN M1 2
eout gm2 2
2 2 2
e2n1 eeq = g = en1 +g en2
m1 2 m1
VSS
gm2
2
2 2 gm2 2 en2
eeq = en1 1 + g
m1 e2
n1
Sec 3.2, Eq (15)
2 B
1/f noise: en =
fWL ; B=constant for a process
Sec. 3.3, Eq (6)
2K' W
gm = ID
L
' W2
2KP ID
2 2 L2 BP fW1L1
So eeq = en1 1 +
' W 1 fW 2 L 2 BN
2KN
I D
L1
KP' BP L12
eeq = en1 1 +
2 2
K ' BNL2
N
2 8kT(1+η)
en =
3gm
2 8kT(1+η1) gm2 2 (1+η2)gm1
eeq = 1 + 2
3gm1 gm1 (1+η1)gm2
W 2 1/2
1 2 2
8kT(1+η K '
P L
2 ) (1+η )
(1+η1)KN'W1
eeq = 1+
3gm1
L1
or
2 8kT(1+η 1) 1+η2 gm2
eeq = 1 +
3gm1 1+η1 gm1
Push-Pull Inverter-
VDD
e2n2
M2
vIN vOUT
M1
e2n1
VSS
1
rout = g
ds1 + g ds2
2 2 2
eout = (gm1rout)2 en1 + (gm2rout)2 en2
vout = −(gm1 + gm2 )rout vin
2 gm1 2 2 gm2 2 2
eeq = g en1 + en2
m1 + g m 2 g m1 + g m 2
gm2 2 en2 2
1 + KP' BP L1 2
m1 en1
g 2 1 + ' L2
2 K NBN
en1
2 2
KP' W 2L 1 2
eeq = = en1
1 + m 2
2
g
gm1 1 + K ' W L
N 1 2
2 2
To minimize noise - Reduce en1 and en2 .
Allen and Holberg - CMOS Analog Circuit Design Page VI.1-20
Equivalent,
Inverter Type AC Voltage AC Output Bandwidth (CGB=0)
Gain Resistance input-referred,mean-
square noise voltage
p-channel
active load -gm1 1 gm2 g 2
v2n1 gm1 +v2n2
sinking gm2 gm2 CBD1 +C GS1 +C GS2 +C BD2 m2
inverter
n-channel
active load -gm1 1 gm2+gmb2 g 2
v2n1 gm1 +v2n2
sinking gm2+gmb2 gm2 +g mb2 CBD1 +CGD1 +CGS2 +CBD2 m2
inverter
Current
source load -gm1 1 gds1+gds2 g 2
v2n1 gm1 +v2n2
sinking gds1+gds2 gds1+gds2 CBD1 +CGD1 +CGS2 +CBD2 m2
inverter
KW 2iD
1.) iD = 2L (vGS − VT ) 2 or vGS = KW/L − VT
2iD KW
2.) vDS (sat) = or iD(sat) = 2L vDS (sat)2
KW/L
2IDKW KW
3.) gm = or gm = L (VGS − V T)
L
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-1
v1 +
Differential
Amplifier vOUT
v2 -
v 1 + v 2
vOUT = AVD(v1 − v2) ± A VC
2
VDD
M3 M4
iD3 iD4 iOUT
vOUT
iD1 iD2
vG1 + M1 M2 vG2
+
vGS1 vGS2
- -
VSS
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-3
VDD
IDD
+ +
vGS1 vGS2
- -
vG1 M1 M2 vG2
iD1=iD3 iD2 iOUT
vOUT
iD4
M3 M4
VSS
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-4
iD1 iD2
M1 M2
+ +
vGS1 vGS2
- -
ISS
2iD1 2iD2
(1). vID = vGS1 − v GS2 = β − β
(2). ISS = iD1 + iD2
Solving for iD1 and iD2 gives,
2
ISS ISS β β 2 v ID
(3). iD1 = 2 + 2 vID
−
ISS 4ISS 2
And
2
ISS ISS β β 2 v ID
(4). iD2 = − vID −
2 2 ISS 4ISS 2
IS S ∂iD1 βISS
Where vID < 2 gm = ∂v =
β ID 4
I
ISS
.8
iD2
.6
.4
iD1 .2 vID
ISS
-2 - 2 2 2
ß
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-5
9u/3u 9u/3u
vOUT 50K
iD1 iD2
3u/3u 3u/3u v-
+
v+
-
3u/3u 3u/3u
VSS = -5V
Simulation Results
140uA
120uA
100uA
iD1
80uA
60uA
40uA
i D2
20uA
0uA
-5V -3V -1V 1V 3V 5V
v+
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-6
VDD
9u/3u 9u/3u
50kΩ
vOUT
v+ 3u/3u 3u/3u v-
3u/3u 3u/3u
VSS
v- = 0V v- = -1V
3
v- = 1V
Output Voltage
-1
v- = -1V
v- = 0V
v- = 1V
-3
-5
-5 -3 -1 1 3 5
Positive Input Voltage
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-7
VDD
9u/3u 9u/3u
v+ 9u/3u 9u/3u v-
vOUT
50kΩ
3u/3u 3u/3u
VSS
v- = 1V
3
v- = 0V
v- = -1V
Output Voltage
-1
-3 v- = 1V
v- = 0V
v- = -1V
-5
-5 -3 -1 1 3 5
VDD
+
M5 vSD5
-
+ +
+
vSG1 vSG2
- v -
vG1 M1 SD1 M2 vG2
-
vOUT
M3 M4
+
vGS3
- VSS
Example
Assume that VDD varies from 8 to 12 volts and that VSS = 0. Using
the values of Table 3.1-2, find the common mode range for worst case
conditions. Assume that ISS = 100µA, W1/L1 = W2/L2 = 5, W3/L3 =
W4/L4 = 1, and vSD5 = 0.2V. Include the worst case value of K' in the
calculations.
100
= 8 − 0.2 − − 1.2 = 6.6 − 1.67 = 4.99V
5x7.2
ISS
β3 + VTO3 − |V T1|
vG1(min) = VSS +
100
=0+ + 1.2 − 0.8 = 0.4 + 2.31 = 2.71V
1x18.7
8V
4.99V
2.71V
0V
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-11
VDD
M3 M4
vOUT
vG1 M1 M2 vG2
VGG M5
VSS
Exact small signal model -
G1 G2 S1=S2 D2=D4
+v id - g m1 v gs1 gm2 v gs2
+ + + + +
1 vout
vg1 v g2 g
m3
v gs4 rds5 vs1 =vs2 ≈ 0
rds3 rds4
_ _ _ _ g m4 vgs4
-
S3 v gs1 = -v gs2 ⇒v ≈ vs2 ≈ 0 S4
s1
D1=G3=D3=G4
i'out
G1 G2 D2=D4
+v id - +
+ + gm1 v gs1 rds2 +
g m2 vgs2 gm4 v gs4
1 vout
vg1 v g2 g m3 v gs4
rds3 rds4
_ rds1
_ _ -
S1=S2=S3=S4
vgs1 = 0.5vid and v gs2 = −0.5vid
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-12
g m1 g m4 (r ds1 || rds3 )
iout' = −gm4vgs4 − g m2vgs2 = v − gm2vgs2
1 + g m 3 (r ds1 || r ds3 ) gs1
If gm3(r ds1 || rds3) >> 1, gm3 = gm4 , and g m1 = gm2 = gmd, then
iout' ≈ g m1vgs1 − gm2vgs2 = gmd(v gs1 − vgs2) = gmdvid
or
K N'WISS
i out ' ≈ g m d v id = L vi d
gmd 2 K N'W
v out ≈ g v i d = (λ N + λ P ) v
ISSL i d
ds2 + g ds4
Example
vOUT
gm1vin gm2vin
2 2
+ M1 M2 -
vin v
2 - + 2in
v
+ in -
VGG M5
VSS
Current flowing into the output node (drains of M2 and M4) is
gm1vin gm2vin
iout = 2 + 2
Output resistance, R out, seen at this node is
1
R out = rds2||rds4 = g +g
ds2 ds4
Therefore, the open circuit voltage gain is
For example:
VDD
M1-M3-M4
M3 M4
vOUT
vG1 M1 M2 vG2
M1-M2
VSS
VDD
M3 M4
vO1 vO2
vIC M1 M2 vIC
VGG5 M5
VSS
VDD
M3 M4
vO1 vO2
vIC M1 M2 vIC
VSS
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-16
gmbs1 vbs1
+ rds1 +
+
vIC=vg1 vs1 2rds5 rds3 vo1
gm1 vgs1 gm3 vo1
-
- - gm1 +gmbs1 vs1
gm1 vg1
r ds1 rds1
+ +
gm1 +gmbs1 vs1 gm1 vg1
+
vIC=vg1 2rds5 vs1 r ds3 1 vo1
gm3
- 1
- gm1 +gmbs1 -
−g ds1 + g m1 + g m b s 1 v o1 + g ds1 + g ds3 + g m 3 vo1 = −gm1 vIC
vo1
Solving for v gives,
IC
vo1 −0.5gm1gds5
=
vIC gds3+gm30.5g ds + g m1 + g mbs1 + g ds1 + 0.5g ds1 g ds5
or
vo1 −0.5gm1gds5 −gds5
vIC ≈ gm3g m1 + g mbs1 ≈ 2gm3
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-17
gm1
gm3 2(g m1 + g mbs1) 2gm1
|CMRR| = = ≈g
gm1gds5 gds5 ds5
2g m3 g m1 + g mbs1
Example
Let all W/L ratios be unity, ISS = 100µA, and use the values of
Table 3.1-2 to find the CMRR of a CMOS differential amplifier.
Parasitic Capacitances
VDD
M3 M4
Cgd4 Cout
CM vOUT
vG1 M1 M2 vG2
CT
ISS
VSS
+ + g m1vgs1 + +
rds3 C gd4
v gs1 = vgs2 = v gs3
vid /2 -v id /2 rds2 rds4 v out
1 C OUT
rds1 CM gm4v gs3 g m2v gs2
g m3 - -
- -
We will examine the frequency response of the differential amplifier
in more detail later.
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-19
SLEW RATE
dV
i.e. i = C
dT
For the CMOS differential amplifier shown,
VDD
M3 M4
+
CL v
- O
+ M1 M2
vIN
-
ISS
VSS
ISS
Slew rate = C
L
where CL is the total capacitance seen from the output node to ground.
NOISE
Assumption:
Therefore:
ind =
2 KF
iD AF (AF = 0.8 and KF = 10-28 )
fCoxL2
or
2
ind
2 KF
vnd = 2 = 2 i D(AF-1)
gm 2fµoCox WL
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-21
VDD
IDD
v2eq1 v2eq2
M1 M2
i2o
+
M3 M4 vOUT
-
v2eq3 v2eq4
VSS
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-22
NOISE
Total output noise current is found as,
2 2 2 2 2
iod = gm1 2 v1 + g m2 2 v2 + gm32 v3 + g m4 2 v4
2
Define vneq as the equivalent input noise voltage of the differential
amplifier. Therefore,
2 2
iod = gm12 vneq
or
2 2 2 gm3 2 2 2
vneq = veq1 + veq2 + veq3 + veq4
gm1
Where gm1 = gm2 and gm3 = gm4
VDD It is desirable to
increase the
I DD transconductance
of M1 and M2 and
decrease the
v2neq transconductance
M1 M2
of M3 and M4.
(Empirical studies
i2o suggest p-channel
devices have less
+
M3 M4 vOUT noise)
-
VSS
Allen and Holberg - CMOS Analog Circuit Design Page VI.2-23
Minimization of Noise
2 2 2 gm3 2 2 2
vneq = veq1 + veq2 + g veq3 + veq4
m1
In terms of voltage spectral-noise densities we get,
2 2 2 gm3 2 2 2
eeq = en1 + en2 + g en3 + en4
m1
1/f noise
2 KF B
Let en = =
2fCoxWLK' fWL
2 2 2 2
assume en1 = en2 and en3 = en4
L1 K P'BP 1 2 2BP
2) Make L < K 'B ≈ 12.5 so that eeq (1/f) ≈
3 N N fW1L1
Thermal Noise
K N ' WL 3
2 16KT(1+η1) 1 + 3
K P'W1
eeq (th) =
W1
3 2K P'I 1 L
1 L1
Objective
Prevent Cgd of the inverter from loading the previous stage. Gives
very high gain.
Cascode Amplifier Circuit
VDD
Miller effect:
VGG2 M3
Inverter
vout Cin ≈ Gain x Cgd1
VGG1 M2
Cascode
Cgd1 Cin ≈ 3Cgd1
+ v1
≈ 2
vin M1 v 1 vin
-
VSS
CASCODE AMPLIFIER-CONTINUED
+
gm2 v1 rds2
gmbs2 v1
vout
rds3
+ +
vin v1 rds1
gm1 vin
- - -
(gm2 +gmbs2 )v1
C1 rds2
+ + +
1
vin C2 rds1 gm2 (1+η2 ) C3 rds3
v1 vout
gm1vin
gm2( 1+η2 )v1
- - -
Nodal Equations:
(gm1 − sC1)vin + (g m2 + g mbs2 + g ds1 + g ds2 + sC1 + sC2)v1 − (gds2)vout = 0
(sC1-gm1)gm2(1+η)
≅ 2
s (C3C1+C3C2)+s(C 1+C2)(g ds2+g ds3) +C3gm2 (1+η)+gds3gm2(1+η)
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-3
Low-frequency Gains:
−g m 1 2K'(W1/L 1)ID1
≈
gds3 = λ3ID3
v1 −2gm1
=
vin g m2 (1 + η 2 )
Gain Enhancement:
VDD
VGG2 M4
M3
vout −gm1
vin ≈ gds3
vout
VGG1 M2 2K'W1
vout I1
I2 I4 L1
I1
vin ≈ λI2
But I1 = I2 + I4
v in M1
VSS
v1 −gm1
=
vin gm2 ?
What is the small signal resistance looking into the source of M2?
Consider the model below:
i1
gm2 vgs2
+
v1 = vs2 r ds2 r ds3
-
Therefore,
CASCODE AMPLIFIER-CONTINUED
VDD
M2
VGG2
M4
Cgd1
vout
ro = g 1 iin
ds3 +gds4
+
M1
v1 CΜ
M3
-
VSS
C2
+
+
iin R1 C1 v1 gmv1 C3 R3 vout
- -
Note:
s2
d(s) = 1 + as + bs2 = 1 − 1 − = 1 − s + +
s s 1 1
p 1 p2 p1 p2 p1p2
s s2 1 a
d(s) ≈ 1 − p + p p or p1 = − a and p2 = − b
1 1 2
−1 −1
p1 ≈ ≈
R1(C1+C3)+R3(C2+C3)+gm1R1R3C2 gm1R1R3C2
−gm1C2
p2 ≈ C C +C C +C C
1 2 1 3 2 3
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-7
VDD
M5
VGG5
M2 vout
VGG2
M4
Cgd1
ro =g +g1
ds3 ds4 iin
M1
M3
VSS
Cgd1 rds2
+
+ +
iin r1 v1 C2 v2 r2 vout
gmv1 C3 r3
- - gm2(1+η)v2 -
r1 = ro = (gds3 + gds4)-1
C2 = Cgs2 + Csb2 + Cdb1 + Cgd1
-1 1
r 2 = g ds1 + g m 2 (1 + η ) ≈ g
m2
gm2 -1 1
r3 ≈ g + g d s 5 ≈
ds1 g ds2 gds5
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-8
VDD io
VGG4 +
D2
M4
VGG3
gm2 v1 r ds2
M3 Vout gmbs2 v1 g m3 v4
gmbs3 v4 r ds3
vout
VGG2 G1 D1=S2
M2 + + + '
=rds3
Vin vin r ds1 r ds4 v4
v1
gm1 v in -
M1 - -
VSS -
Allen and Holberg - CMOS Analog Circuit Design Page VI.4-1
Requirements
3. Be efficient.
1. Class A amplifier.
2. Source follower.
4. Substrate BJT.
CLASS A AMPLIFIER
VDD
VGG2 M2
IQ Iout
Vout
Vin M1
CL RL
VSS
KnW1
2L1 (VDD − VSS − VT1) − IQ
+=
Iout 2
KpW2
Iout = 2L (VDD − V GG2 − |VT2|) 2 < Iout+
-
2
dvout
1. |Iout| = C L
dt = CL (slew rate)
vout(peak)
2. |I out| =
RL
PRL Vout(peak) 2
Efficiency =
Psupply = (V DD + V SS ) ≤ 25%
1 1
rout = g = (typically large)
ds1 + g ds2 2λID
Allen and Holberg - CMOS Analog Circuit Design Page VI.4-3
SOURCE FOLLOWER
VDD VDD
vIN M1 M1
vOUT vIN vOUT
VGG M2 M2
VSS VSS
SOURCE FOLLOWERS
C1
+ gm1 vin +
vin rds1 rds2 C2 vout
gm1 vout
gmbs1 vout gm2 vgs2
- -
vout gm1
=
vin gds1+gds2+gm1+gmbs1+gm2 where g m2 = 0 if v GS2 = V G G
Example:
W 10 µm
If VDD= −VSS =5V, vOUT = 0V, iD = 100µA, and L =10 µm ,
then;
vout 41.23
=
vin 1+1+41.23(1+0.2723)+41.23 = 0.4309 when vGS2 = vOUT
vout 41.23
=
vin 1+1+41.23(1+0.2723) = 0.751 when vGS2 = VGG
vout
Approximation gives v ≈ 0.786 (gds1= gds2 ≈ 0)
in
Output Resistance:
1
r out =
gds1+gds2+gm1+gmbs1+gm2 where g m2 = 0 if v GS2 = V G G
SOURCE FOLLOWERS
Model:
C1
+ M1 M2
gm1vin gm2 vin +
1 1 C2 v
vin rds1 gmbs1 rds2 out
gm1vout gm2vout gmbs2
- -
vout g m1 + g m 2
vin = g ds1 + g ds2 + g m1 + g mbs1 + g m2 + g m b s 2
Example:
W 10µm
If VDD = −VSS = 5V, vOUT = 0V, iD = 100µA, and L = 10µm
then,
vout 41.23 + 28.28
=
vin 1 + 0.5 + 41.23(1 + 0.2723) + 28.28(1 + 0.1268) = 0.81
Output Resistance:
1
r out =
g ds1 + g ds2 + g m 1 + g mbs1 + g m 2 + g m b s 2 = 11.7KΩ
Allen and Holberg - CMOS Analog Circuit Design Page VI.4-6
Concept-
VDD
M2
+
VTR2 Iout
vIN - Vout
+
VTR1
-
M1
CL RL
VSS
Implementation-
VDD
M5 M6
VGG3 Iout
M1 M3 Vout
vIN
M2 M4 VGG4 CL RL
M7 M8
VSS
Allen and Holberg - CMOS Analog Circuit Design Page VI.4-7
VDD
M2 Iout
VTR
Vout
vIN
M1 CL RL
VSS
VDD
VGG6 M6
M2
M5 Iout
Vout
M4
M1 CL RL
vIN M3
VSS
Allen and Holberg - CMOS Analog Circuit Design Page VI.4-8
VDD
error M2
amplifier
- + Iout
vIN Vout
- +
CL RL
M1
VSS
VDD
M2
R1 R2 Iout
vIN Vout
CL RL
M1
VSS
VI.5 - SUMMARY
SECTION 7 - COMPARATORS
Allen and Holberg - CMOS Analog Circuit Design Page VII.0-1
VII. COMPARATORS
Contents
Organization
Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS
COMPLEX
CIRCUITS
Chapter 5 Chapter 6
CMOS CMOS Amplifiers
Subcircuits
SIMPLE
Chapter 2 Chapter 3
CMOS Device Chapter 4 Device
CMOS
Modeling Characterization
Technology
DEVICES
Allen and Holberg - CMOS Analog Circuit Design Page VII.1-1
VII.1 - CHARACTERIZATION OF
COMPARATORS
What is a Comparator?
Characterization of Comparators
VOLTAGE COMPARATORS
Definition of a Comparator
VA +
VOUT
VB -
Noninverting
VOUT
VOH
V O H when VA ≥ VB
VOUT = VA - VB
V OL when V A < V B
VOL
Inverting
VOUT
V O L when VA ≥ VB VOH
VOUT =
V OH when V A ≤ V B VA - VB
VOL
Allen and Holberg - CMOS Analog Circuit Design Page VII.1-3
COMPARATOR PERFORMANCE
2. Resolving capability.
The input change necessary to cause the output to make a transition
between its two stable states.
Open Loop
Regenerative
Charge Balancing
VOUT
VOH
- +
VP - VN
VOL
Model
VP
+
+ +
fo VP - VN VO
-
-
VN -
for ( V P - V N ) ≥ 0
V O H
fo( V P - VN ) =
V OL for ( V P - V N ) ≤ 0
Allen and Holberg - CMOS Analog Circuit Design Page VII.1-6
Transfer Curve
VOUT
VOH
VIL
VP - VN
VIH
VOL
Model
VP
+
+ +
f1 VP - VN VO
-
-
VN -
V O H for ( V P - V N ) ≥ VIH
f1( V P - V N ) = AV( V P - V N ) f o r V I L ≤ ( V P - V N ) ≤ V I H
V OL for ( V P - V N ) ≤ VIL
Allen and Holberg - CMOS Analog Circuit Design Page VII.1-7
Transfer Curve
VOUT
VOS VOH
VIL
VP - VN
VIH
VOL
+-VOS
VP + - V'P +
+ +
f1 V'P - V'N VO
-
- -
VN V'N
VOH
VOUT v = VOH + VOL
2
VOL
VIH
VP - VN tP v = VIH + VIL
2
VIL
Time
Allen and Holberg - CMOS Analog Circuit Design Page VII.2-1
VDD
vN M2
I2
vO
IB
VBIAS M1
VSS
VDD ∆VIN
vO
VTRP
vN
vO
M1 sat.
VBIAS M1 VBIAS - VT1
M1 act.
VSS VIN
VSS VSS VDD
vN VTRP
Operating Regions-
vDS1 ≥ v GS1 - VT ‘ vO - VSS ≥ V BIAS - VSS - VT1
v O ≥ V BIAS - V T 1
v O ≤ v I N + VT2
Trip Point-
Assume both M1 and M2 are saturated, solve and equate drain
currents for VTRP. Assume λ ≈ 0.
K N W1 2
iD1 = 2 L V BIAS - V SS - V T 1
1
K P W2 2
iD2 = 2 L V D D - v I N - VT2
2
KN( W1/L1)
iD1=iD2 ‘ vIN = VTRP = VDD- VT2 - KP( W2/L2) ( V BIAS - V SS - V T 1)
W1 W2
I.e. V DD = -VSS = 5V, VBIAS = -2V and KN L = KP L
1 2
VTRP = 5-1-(-2+5-1) = 4-2 = 2V
Allen and Holberg - CMOS Analog Circuit Design Page VII.2-3
VDD
M3 M4
vO
M1 M2
vP vN
VBIAS M5
vO
VOH = VDD
VOH'
M1 & M2 in
saturation
VOL'
VOL
VSS
vP - vN
-1 +1 Av
VDD vP > vN
M3 M4
1. Current in M1 increases and
vO current in M2 decreases.
I1 I2 2. Mirroring of M3-M4 will
M1 M2
vP vN cause vO to approach VDD .
3. VOH' = VDD - VDS4(sat)
ISS I4
VOH ' = VDD -
VBIAS β4
M5
I5
VOH ' = VDD -
VSS Kp'( W4/L4)
vP < vN I5
V O H ' = VD D -
Kp'( W3/L3)
Assume vN is a fixed DC voltage
4. Finally, vO ‘ V DD causing the
1. vO starts to decrease, M3-M4 mirror mirror M3-M4 to no longer be
is valid so that I1 = I2 = ISS/2 .
valid and V OH ≈ V DD.
2. VOL ' = vN - VGS2 + VDS2
when M2 becomes non-sat. we have (I2 = I4 = 0 , I3 = I1 = I5)
VDS2(sat) = VGS2 - VT so that
V OL ' = v N - V T 2
3. For further decrease in vO, M2 is non-
sat
and therefore the VGS2 can increase I 1 still equals I2 due to mirror
allowing the sources of M1 and M2 to
fall(as v P falls).
4. Eventually M5 becomes non-sat and I5
starts to decrease to zero. M2 becomes a
switch and v O tracks V S2(VDS5) all the
way to VSS.
∴ V OL = V SS .
Allen and Holberg - CMOS Analog Circuit Design Page VII.2-5
TWO-STAGE COMPARATOR
• Sufficient gain.
• Good signal swing.
VDD
M3 M4
M6
vN M1 M2
vP vO
I8
M5
M8 M7
VSS
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-1
• Try to keep all devices in saturation - more gain and wider signal
swings.
W1
Let S1 = L ,
1
M1 and M2 matched gives S 1 = S2.
M3 and M4 matched gives S 3 = S4.
also, I 1 = I2 = 0.5I5.
From gate-source matching, we have
S7 S6
VGS5 = VGS7 ‘ I7 = I5 and I 6 = I4 ← Assume
S5 S4
VGS4 =VGS6
For balance conditions, I6 must be equal to I7, thus
I 5 S7 S6
.
I4 S5 = S4
I5
Since
I4 = 2, then DC balance is achieved under the following:
S6 S
= 2 . 7 ‘ VDG4 = 0 ‘ M4 is saturated.
S4 S5
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-2
VDD =10V
+ +
2V
KN = 24.75 µA/V2 20 - 20 2V
10 10
KP = 10.125 µA/V2 M3 - M6 40
M4
VTN = -VTP = 1V 10
λN = 0.015V -1 20 20
10 10 i6
λP = 0.020V -1 vN vP vO =5V
I8 i7
M1 M2
20µA +
10
10 3V 10
M8
M5 M7 10
-
Find VOS to make i6 = i 7 VSS =0V
VDD
+
VSG3
- M3 vG1 (min) = VSS + VDS5 + VGS1
I5/2 I5
+ v G1 (min) = V SS + V DS5 + V T1 (max) +
VDG1 2β1
- +
VG1 VDS1
+ M1 - vG1 (max) = VDD - VSG3 - VDG1(sat)
VGS1 + I5
- v G1 (max) = V D D -
I5 2β3 - VT3(max) + V T1 (min)
VBIAS VDS5
where V DG1(sat) = -VT1
M5 -
VSS
Example
KNW 1 W1 W 2
β1 = L1 = 250 µA/V ‘
2
L1 = L2 = 14.70
I5
vG1(max) = VDD - β3 - |VT3(max)| + VT1(min)
K PW 3 W3 W 4
β3 =
L3 = 250 µA/V ‘
2
L3 = L4 = 31.25
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-4
+ +
gm1vid r ds2 r ds4 v1 gm6v1 r ds6 r ds7 vout
- -
vid = vP - vN
gm1 gm6
Av = g
ds2 + g ds4 g ds6 + g ds7
W1 W6
2 KNKP L L
1 6
Av =
( λ2 + λ4) ( λ6 + λ7) I1I6
W1 W6
Using L = 5, L = 5, λN = 0.015V-1 , λP = 0.02V-1
1 6
and Table 3.1-2 values;
2 (17)(8)(5)(5) . -6 95199.10-6
Av = 10 =
(0.015+0.02)2 I1I6 I1I6
Av = 3010
V OH - VOL
= Resolution = 5 mV (assume)
Av
5 .
then VOH - V OL =
1000 3000 = 15 Volts
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-5
VDD
signal swing
less than the
M3 M4 output
VGS6 +
-
M6
vN vP i6 key node
M1 M2
CL1 vO
i7
CL2
M5
VBIAS M7
i5
VSS
dv
iC = C dt , ∆t =
∆v
∆t2+ = C L2
CI V TRP3 - V S S
K P W6 V - v P - V D G 2 - |V T6 | ) 2 -
2 L6 ( D D I7
∆t+2
VTRP3
∆t2- = CL2 W L
V
VDD
SS
V DD - V TRP3
7 5 i
VTRP3
L7 W5 5
∆t-2
isource/sink
Slew rate =
CLi
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-6
I5
VDO(min) ≈ vDS2(≈0) - vGS1 + vN = -VT1 - = -1.77
KN.2
8.10-6
2 (4)(5 - (-1.77) -1) = 533 µA
I6 = 2
10 pF
∴ ∆t2 = 5 (533 - 40) µA = 101 ns
-5V V(9)
1v vP
0v tprop=167 ns
Actual
-1 v
-1.54v V(6)
-5 v
0ns 50ns 100ns 150ns 200ns 250ns 300ns
Time
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-8
+ +
vin gm1 gm2
- - +
R1 C1 R2 C2 vout
-
vout(s) A oω p1ω p2
=
vin(s) ( s + ω p 1) ( s + ω p 2)
1
ω p1 = R C
1 1
1
ω p2 =
R2C2
Ao = gm1gm2R1R2
1 1
I7 = 40µA ‘ R2 = g =
ds6 + g ds7 40µA(.03) = 833KΩ
1
ω p2 =
(10pF)(833KΩ) = 120Krps
General Schematic
VDD
M3 M4
M6
vN M1 M2
vP vO
I8
M5
M8 M7
VSS
β β
i D = (v G S - V T ) 2 ⇒ iD (sat) = 2 [vDS(sat)]2
2
or
2iD(sat)
v DS (sat) = β
Also,
gm = 2βI D
where
KW
β= L
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-10
2. Determine the minimum sizes for M6 and M7 for the proper ouput
voltage swing.
2ID
vDS (sat) = β
3. Knowing the second stage current and minimum device size for M6,
calculate the second stage gain.
-g m6
A2 =
g ds6 + g ds7
4. Calculate the required first stage gain from A2 and gain specifications.
5. Determine the current in the first stage based upon proper mirroring
and minimum values for M6 and M7. Verify that Pdiss is met.
6. Calculate the device size of M1 from A1 and I DS1.
-g m1 2K'W/L
A1 = g and gm1 =
ds1 + g ds3 IDS1
7. Design minimum device size for M5 based on negative CMR require-
ment using the following (IDS1 = 0.5IDS5):
IDS5
vG1(min) = VSS + VDS5 + β1 + VT1(max)
2IDS5
where VDS5 =
β5 = VDS5(sat)
8. Increase either M5 or M7 for proper mirroring.
9. Design M4 for proper positive CMR using:
IDS5
vG1(max) = VDD -
β3 - VTO3 (max) + VT1
10. Increase M3 or M6 for proper mirroring.
11. Simulate circuit.
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-11
Specifications:
CMR = 4-6 V
Output swing is VDD - 2V and VSS + 2V
dvOUT
∴ I7 = CL
dt = ( 2 10 ) ( 100 10 ) = 200 µA
. -12 . -6
M6:
2( IOUT+I7) 2(400µA) W6
2V > vDS6(sat) = = →
β6 8.0µA/V 2( W6/L6) L6 > 12.5
-g m6 -1 2KP'W6
3). A 2 = g I6L6 ≈ -10
=
ds6 + g ds7 λ N + λ P
S4
5). Assuming vGS4 = v GS6, then I4 =
S6 I6
1
choose S 4 = 1 which gives I4 = 12.5 (200µA) = 16.0 µA
S5 200µA
5.88 = 34 µA
Assume S5 = 1 which gives I 5 = I 7 =
S7
1
and I4 = I5 = 17 µA
2
W
Choose I 4 = 17 µA to keep L ratios greater than 1.
W4 W 6 17
∴ I5 = 34 µA
L4 = L6 200 = 1.06 ≈ 1.0
Pdiss = 10( I 7 + I 5 ) = 2.34 mW < 10 mW
1 2KN'W1 W1 I
6). A1 = λ + λ → = [ (λ 1 + λ 4 )A 1 ] 2 4 = 200
1 4 I4L 1 L1 2KN'
W1
∴ L = 200 (Good for noise)
1
I5
7). V DS5 = vG1(min) - VSS - β1 - VT1(max)
(34)
V DS5 = 4 - 0 - -1 = 2.90 V
2(17.0)(200)
2I5 2(34µ) W5
VDS5 = → L > 0.48
β5 = (17µ)S5 5
I5 34 W5
8). S5 = S = (5.88) = 1.0 →
I7 7 200 L5 = 1 . 0
Allen and Holberg - CMOS Analog Circuit Design Page VI.3-13
I5
9). VG1(max) = VDD - β3 - VTO3 (max) + VT1(min)
I5
β3 =
V D D - V G1 (max) - VTO3 (max) + V T1 (min) 2
34 µA
= = 2.76.10 -6
( 1 0 - 6 - 1 + 0 . 5) 2
W3 (2.76)(2) W3 W 4
∴L = = 0.69
3 8 L3 = L4 > 0.69
W4
(Previously showed L > 1.06 so no modification is necessary)
4
10). Summary
W
Wdrawn = (L - 1.6)
L
MP3 MP4
MP8
MP6
MP12 MP13
vOUT
MN1 MN2
MN25 MN10 MN11
v2 v1
V SS
1 1 +
gm12 i1 gm13 i2
rout vout
i2 i1
gm1 v2 gm2 v1
-
where
R out ≈ (rds5gm11rds11)||((rds4||rds2)gm13rds13) =
1
=g
ds5gds11 (gds2+gds4)gds13
gm11 + gm13
The small signal voltage gain is
vout = r out (i2-i1) = (gm2 +gm1 )Rout vin = g vin
gm1 +gm2
ds5gds11 (gds2+gds4)gds13
gm11 + gm13
where vin = v1 - v2.
Allen and Holberg - CMOS Analog Circuit Design Page VII.4-2
i2 +
C1 i1 C2 C3
1 vout
i2 i1 rout
gm1 v2 gm12 gm2 v1 1
gm13 -
where
C1 = C GS12 + C BS12 + C DG3 + C BD3
AVD0ω3
AVD(s) ≈ s + ω
3
where
1
ω3 =
routC3
Typical performance-
W 1 W 2 W 11 W 13
ID1 = ID2 = 50µA and ID3= I D4 = 100µA,
L1 = L2 = L11 = L13
=1, assume C 3 ≈ 0.5pF, and using the values of Table 3.1-2 gives:
BIAS M1 M6
M8 M10
vO
- M2 M3 +
M9 M11
M7
M4 M5
Rise time
= 100 ns into 50 pF
Fall time
Propagation delay = 1 µs
Slew rate = 2.7 Volts/µs
Loop Gain = 32,000
Comments
The inverter pair of M8-M9 and M10-M11 are for the purpose of
providing an output drive capability and minimizing the propagation delay.
Allen and Holberg - CMOS Analog Circuit Design Page VII.4-4
VDD VDD
M8 M6
BIAS M1 VPB
vO
- +
M2 M3 VNB
M9 M4 M5 M7
VSS
Why Hysteresis?
Eliminates "chattering" when the input is noisy.
vin
Comparator
threshold
Time
Comparator
output
vin
vout
VTRP+
VTRP-
Time
vin
VTRP-
VTRP+ comparator
output
Allen and Holberg - CMOS Analog Circuit Design Page VII.6-2
Inverting
vOUT
VOH
vB -
vOUT VREFR2
vA + R1 +R2
vB
R2 VOHR1
R1 R1 +R2
+
V
- REF VOL
VOLR1
R1 +R2
Noninverting
vOUT
R2
VOH
R1 vA +
vIN VREF R1 +R2
vOUT R2
vB -
vIN
+
R1 V
- VREF R2 OL
VOL
R1 V
R2 OH
Allen and Holberg - CMOS Analog Circuit Design Page VII.6-3
Cross-Coupled Bistable
VDD
M3 M10 M11 M4
M8 M6
M1 M2
vO
BIAS M5
M9 M7
VSS
5.0V
4.0V
Allen and Holberg - CMOS Analog Circuit Design
3.0V
2.0V
1.0V
Page VII.6-4
+
IDEAL
- + -
VOS
+
IDEAL
- + - +
VOS CAZ V
- OS
VIN +
IDEAL
- + -
- +
VOS VOS
+ 0V
-
Allen and Holberg - CMOS Analog Circuit Design Page VII.6-6
φ1
φ2
vIN+ +
φ1 VOS IDEAL vOUT
+ - - + -
vIN-
CAZ VOS
φ2
φ1
φ1
φ2
-
φ1 vOUT
vIN +
CAZ
φ2 φ1
φ1
φ2
CAZ
vIN -
vOUT
φ1 +
+ Q
vIN C1 C2 C3 Cn Latch
- Q
High
Output
Level ∆ = input voltage
change Latch
n tn-1 )e-t/τ ]
vout = e t/τ ∆ v out = A [1 - (1 + (n-1)! ∆
A5∆ 5
A4∆ 4
A3 ∆ 3
v out = A2[1 - (1 + t)e -t/τ )] ∆
A2∆ 2
v out = A(1-e-t/τ )∆
A∆ n=1
t3 tL Time
Implementation:
n=3 and A≈6 gave nearly the same result with less area.
[Ref: Doernberg et al., “A 10-bit 5 MSPS CMOS Two-Step FLASH ADC”JSSC April 1989 pp 241-
249]
Allen and Holberg - CMOS Analog Circuit Design Page VII.6-2
Conceptual Implementation-
+ + - + - + - Q
vIN Latch
- - + - + - + Q
VDD
Q
FB Reset
Q
FB
VB1 LATCH
vIN-VOS VSS
+ - _
vIN
+
+
VOS
-
Allen and Holberg - CMOS Analog Circuit Design Page VII.7-1
Contents
Organization
Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS
COMPLEX
CIRCUITS
Chapter 5 Chapter 6
CMOS CMOS Amplifiers
Subcircuits
SIMPLE
Chapter 2 Chapter 3
Chapter 4 Device
CMOS CMOS Device
Characterization
Technology Modeling
DEVICES
Allen and Holberg - CMOS Analog Circuit Design
Op Amp Characteristics
V
1 R
icm I
b2
CMRR 2
e
n
V R
2 - out
V 2
I R C
os id id Ideal
n
V +
1
R I
icm b1
Frequency Response
Av0
A v (s) = s s s
(p − 1 ) (p − 1 ) (p − 1 ) . . .
1 2 3
-6dB/oct
Gain, dB
GB
ω2
ω3
0 dB
ω1
Frequency
180
Phase (degrees)
90
Phase margin
Frequency
-90
Allen and Holberg - CMOS Analog Circuit Design
vout
∆VDD A vd(s) vin (v ps =0)
PSRR = · Avd(s) =
∆vOUT Aps(s) = vout
vps (v in=0)
Common-mode input range (ICMR).
Maximum common mode signal range over which the differential
voltage gain of the op amp remains constant.
Maximum and minimum output voltage swing.
Slew rate:
∆vOUT
Slew rate = max ∆t
10V
5V
Output
Voltage
0V
-5V
Input
Voltage
-10V
0µs 2µs 4µs 6µs 8µs 10µs
Time
Allen and Holberg - CMOS Analog Circuit Design
Settling Time
1.4
1.2
Upper tolerance
1
0.8
Lower tolerance
Vout(t)
0.6
Settling
0.4
time
0.2
0
0 2 4 6 8 10 12 14
Time (sec)
Allen and Holberg - CMOS Analog Circuit Design
Design Approach
Design
Analysis
Specifications Iterate
Simulation
Modify
Specifications:
• Gain • Bandwidth
• Output voltage swing • PSRR
• Settling time • CMRR
• Power dissipation • Noise
• Supply voltage • Common-mode input range
• Silicon area
Allen and Holberg - CMOS Analog Circuit Design
Design Strategy
Op Amp Architecture
VDD
M3 M4
M6
M1 M2
- + Compensation vOUT
IBias
M5 M7
Allen and Holberg - CMOS Analog Circuit Design
Compensation
-
+
IN Σ A OUT
OUT A
=
IN 1 + Aβ
Goal: 1 + Aβ > 0
Rule of thumb: arg[Aβ] < 135˚ at mag[Aβ] = 1
Allen and Holberg - CMOS Analog Circuit Design
β=1
|Aβ| (dB)
-6dB/oct
GB
0 dB
ω1 ω2
Frequency -12dB/oct
180o
Arg[Aβ]
90o
0o
Frequency
Allen and Holberg - CMOS Analog Circuit Design
stability
Date/Time run: 04/08/97 19:45:36 Temperature: 27.0
1.5V
3
2
1
1.0V
ω1 = 1000 rps
0V
0s 5us 10us 15us 20us
v(5)
Time
Allen and Holberg - CMOS Analog Circuit Design
Types of Compensation
Miller Compensation
VDD
M3 M4
CM Cc M6
M1 M2
- + v OUT
IBias C1
M5 M7 CL
Small-signal model
1 1
gds2+g ds4 Cc gds6 +gds7
+ gm4v 1 + +
-v CM
gm1 in v1 v2
2 r ds1
1 v
g m2 in C1 CL vout
gm3 gm6 v2
- 2 - -
1 1
gds2+gds4 Cc gds6+gds7
+ + +
vin v2
gm1vin C1 CL vout
gm6v2
- - -
Allen and Holberg - CMOS Analog Circuit Design
Analysis
-1
p1 ≅ g
mII RI RII Cc
-gmIICc
p2 ≅ C C + C C + C C
1 L L c 1 c
-gmII
p2 ≅
CL
gmII
z1 =
Cc
where
gmI = gm1 = gm2 gmII = gm6
1 1
RI = g RII = g
ds2+gds4 ds6+gds7
Allen and Holberg - CMOS Analog Circuit Design
Miller Compensation
β=1
|Aβ| (dB) -6dB/oct
Before compensation
GB
After compensation
ω1 ω2
Frequency -12dB/oct
180o
Before compensation
Arg[Aβ]
90o
After compensation
Phase margin
0o
Frequency
Allen and Holberg - CMOS Analog Circuit Design
ω ω ω
Arg[Aß] = ±180° - tan-1 - tan-1 - tan-1 = 45°
|p1| |p2| z
| p 2 | ≥ 2.2GB if z ≥ 10GB
Allen and Holberg - CMOS Analog Circuit Design
gmII 10gmI
⇒
Cc > Cc g m II > 10g m I
Furthermore,
gmII 2.2gmI
C2 > Cc
which after substitution gives:
C c > 0.22C 2
Note:
gmI = gm1 = gm2 and gmII = gm6
Allen and Holberg - CMOS Analog Circuit Design
M3 M4 M6
M1 M2 Cc
RZ V OUT
CII
Vbias
M7
M5
RZ Cc
+ + +
vin v2
gmI vin RI CI RII CII vout
gmII v2
- - -
VI sCc
gmIVin + R + sCIVI + (VI − Vo) = 0
I 1 + sCcRz
Vo sCc
gmIIVI + R + sCIIVo + (Vo − VI) = 0
II 1 + sCcRz
These equations can be solved to give
Vo(s) a{1 − s[(Cc/gmII) − RzCc]}
Vin(s) = 1 + bs + cs2 + ds3
where
a = gmIgmIIRIRII
d = RIRIIRzCICIICc
If Rz is assumed to be less than RI or RII and the poles widely spaced, then the roots are
−1 −1
p1 ≅ ≅g R RC
(1 + gmIIRII)RICc mII II I c
−gmIICc −gmII
p2 ≅ ≅ C
CICII + CcCI + CcCII II
−1
p3 = R C
z I
and
1
z1 =
Cc(1/gmII − Rz)
By setting
Rz = 1/gmII
The RHP zero moves to infinity
Allen and Holberg - CMOS Analog Circuit Design
M3 M4 M6
M1 M2 MZ Cc
V OUT
CII
Vbias
M7
M5
Allen and Holberg - CMOS Analog Circuit Design
VDD
M6
M3 M4 Cc
vout
- M1 M2 CL
vin
+
+ M7
VBias M5
-
VSS
Figure 6.3-1 Schematic of an unbuffered, two-stage CMOS op amp
Important with
relationships:
an n-channel input pair.
gm1 = gm2 = gmI, gm6 = gmII, gds2 + gds4 = GI, and gds6 + gds7 = GII.
I5
Slew rate SR = (1)
Cc
gm1 2gm1
First-stage gain Av1 = = (2)
gds2 + gds4 I5(λ 2 + λ 4)
gm6 gm6
Second-stage gain Av2 = = (3)
gds6 + gds7 I6(λ 6 + λ 7)
gm1
Gain-bandwidth GB = (4)
Cc
−gm6
Output pole p2 = (5)
CL
gm6
RHP zero z1 = (6)
Cc
I5
Positive CMR Vin(max) = VDD − − |VT03|(max) + VT1(min)) (7)
β3
Allen and Holberg - CMOS Analog Circuit Design
I5
Negative CMR Vin(min) = VSS + + VT1(max) + VDS5(sat) (8)
β1
2IDS
Saturation voltageVDS(sat) = (9)
β
All transistors are in saturation for the above relationships.
The following design procedure assumes that specifications for the following parameters
are given.
Design the compensation capacitor Cc. It was shown that placing the loading pole p2 2.2
times higher than the GB permitted a 60° phase margin (assuming that the RHP zero z1 is
placed at or beyond ten times GB). This results in the following requirement for the
minimum value for Cc.
Cc > (2.2/10)CL
Next, determine the minimum value for the tail current I5, based upon slew-rate
requirements. Using Eq. (1), the value for I5 is determined to be
I5 = SR (Cc)
If the slew-rate specification is not given, then one can choose a value based upon settling-
time requirements. Determine a value that is roughly ten times faster than the settling-time
specification, assuming that the output slews approximately one-half of the supply rail. The
value of I5 resulting from this calculation can be changed later if need be.
The aspect ratio of M3 can now be determined by using the requirement for positive input
common-mode range. The following design equation for (W/L)3 was derived from
Eq. (7).
I5
S3 = (W/L)3 =
(K'3) [VDD − Vin(max) − |VT03|(max) + VT1(min)]2
If the value determined for (W/L)3 is less than one, then it should be increased to a value
that minimizes the product of W and L. This minimizes the area of the gate region, which
Allen and Holberg - CMOS Analog Circuit Design
in turn reduces the gate capacitance. This gate capacitance will affect a pole-zero pair which
causes a small degradation in phase margin.
Requirements for the transconductance of the input transistors can be determined from
knowledge of Cc and GB. The transconductance gm2 can be calculated using the following
equation
gm1 = GB(Cc)
The aspect ratio (W/L)1 is directly obtainable from gm1 as shown below
g2m1
S1 = (W/L)1 = (K' )(I )
2 5
Enough information is now available to calculate the saturation voltage of transistor
M5. Using the negative ICMR equation, calculate VDS5 using the following relationship
derived from Eq. (8).
1/2
I5
VDS5 = Vin(min) − VSS − − VT1(max)
β 1
If the value for VDS5 is less than about 100 mV then the possibility of a rather large (W/L)5
may result. This may not be acceptable. If the value for VDS5 is less than zero, then the
ICMR specification may be too stringent. To solve this problem, I5 can be reduced or
(W/L)1 increased. The effects of these changes must be accounted for in previous design
steps. One must iterate until the desired result is achieved. With VDS5 determined, (W/L)5
can be extracted using Eq. (9) in the following way
2(I5)
S5 = (W/L)5 =
K'5(VDS5)2
For a phase margin of 60°, the location of the loading pole was assumed to be
placed at 2.2 times GB. Based upon this assumption and the relationship for |p2| in Eq. (5),
the transconductance gm6 can be determined using the following relationship
gm6 = 2.2(gm2)(CL/Cc)
gm6
S6 = S3 g
m3
I6 can be calculated from the consideration of the “proper mirroring” of first-stage the
current mirror load of Fig. 6.3-1. For accurate current mirroring, we want VSD3 to be equal
to VSD4. This will occur if VSG4 is equal to VSG6. VSG4 will be equal to VSG6 if
Allen and Holberg - CMOS Analog Circuit Design
(W/L)6 S 6
I6 = (W/L) I1 = S I1
4 4
Choose the larger of these two values for I6 (Eq. 19 or Eq. 20). If the larger value is found
in Eq (19), then (W/L)6 must be increased to satisfy Eq. (20). If the larger value is found in
Eq. (20), then no other adjustments must be made. One also should check the power
dissipation requirements since I6 will most likely determine the majority of the power
dissipation.
The device size of M7 can be determined from the balance equation given below
I6 I6
S7 = (W/L)7 = (W/L)5 = S5
I5 I5
The first-cut design of all W/L ratios are now complete. Fig. 6.3-2 illustrates the above
design procedure showing the various design relationships and where they apply in the
two-stage CMOS op amp.
Max. ICMR
and/or p3
VDD Vout(max)
+ +
VSG4 VSG6
- -
M6 gm6 or
M3 M4 Cc I6 Proper Mirroring
g VSG4=VSG6
GB = m1
Cc vout
-
vin Cc ≈ 0.2CL CL
M1 M2
(PM = 60°)
+
Min. ICMR I5 I5 = SR·Cc
Vout(min)
+
VBias M5 M7
-
VSS
Figure 6.3-2 Illustration of the design relationships and the circuit for
a two-stage CMOS op amp.
At this point in the design procedure, the total amplifier gain must be checked against the
specifications.
(2)(gm2)(gm6)
Av =
I5(λ2 + λ3)I6(λ6 + λ7)
If the gain is too low, a number of things can be adjusted. The best way to do this is to use
the table below, which shows the effects of various device sizes and currents on the
Allen and Holberg - CMOS Analog Circuit Design
different parameters generally specified. Each adjustment may require another pass
through this design procedure in order to insure that all specifications have been met. Table
6.3-2 summarizes the above design procedure.
Design Procedure:
This design procedure assumes that the gain at dc (Av), unity gain bandwidth (GB), input
common mode range (Vin(min) and Vin(max)), load capacitance (CL), slew rate (SR),
settling time (Ts), output voltage swing (Vout(max) and Vout(min)), and power dissipation
(Pdiss) are given.
1. Choose the smallest device length which will keep the channel modulation parameter
constant and give good matching for current mirrors.
2. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60°
phase margin we use the following relationship. This assumes that z ≥ 10GB.
Cc > 0.22CL
3. Determine the minimum value for the “tail current” (I5) from the largest of the two
values.
I5 = SR .Cc
VDD + |VSS|
I5 ≅ 10
.
2 Ts
5. Verify that the pole of M3 due to Cgs3 and Cgs4 (=0.67W3L3Cox) will not be
dominant by assuming it to be greater than 10 GB
gm3
2Cgs3 > 10GB.
I5
VDS5(sat) = Vin(min) − VSS − − VT1(max) ≥ 100 mV
β1
2I5
S5 =
K'5[VDS5(sat)]2
Allen and Holberg - CMOS Analog Circuit Design
8. Find gm6 and S6 by the relationship relating to phase margin, load, and compensation
capacitors, and the balance condition.
gm6 = 2.2gm2(CL/Cc)
gm6
S6 = S3 g
m3
9. Calculate I6 :
I6 = (S6/S4)I4 = (S6/S4)(I5/2)
10. Design S7 to achieve the desired current ratios between I5 and I6.
S7 = (I6/I5)S5
11. Check gain and power dissipation specifications.
2gm2gm6
Av =
I5(λ2 + λ3)I6(λ6 + λ7)
12. If the gain specification is not met, then the currents, I5 and I6, can be decreased or the
W/L ratios of M2 and/or M6 increased. The previous calculations must be rechecked
to insure that they have been satisfied. If the power dissipation is too high, then one
can only reduce the currents I5 and I6. Reduction of currents will probably necessitate
increase of some of the W/L ratios in order to satisfy input and output swings.
13. Simulate the circuit to check to see that all specifications are met.
Allen and Holberg - CMOS Analog Circuit Design
I5 = (3 × 10-12)(10 × 106) = 30 µA
Next calculate (W/L)3 using ICMR requirements.
30 × 10-6
(W/L)3 = = 15
(50 × 10-6)[2.5 − 2 − .85 + 0.55]2
-gm3 - 2K’pS3I3
p3 ≈ 2C = 2(0.667)W L C = 15.75x109(rads/sec)
gs3 3 3 ox
or 2.98 GHz. Thus, p3, is not of concern in this design because p3 >> 10GB.
The next step in the design is to calculate gm1
gm12 (94.25)2
(W/L)1 = (W/L)2 = 2K’ I = 2·110·15 = 2.79 ≈ 3.0
N 1
Next calculate VDS5
Allen and Holberg - CMOS Analog Circuit Design
30 × 10-6
VDS5 = (−1) − (−2.5) − - .85 = 0.35V
110 × 10-6·3
Using VDS5 calculate (W/L)5 from Eq. (16)
2(30 × 10-6)
(W/L)5 = = 4.49 ≈ 4.5
(50 × 10-6)(0.35)2
From Eq. (20) of Sec. 6.2, we know that
gm6 ≥ 10gm1 ≥ 942.5µS
Assuming that gm6 = 942.5µS
942.5 × 10-6
(W/L)6 = 15 = 94.25
150 × 10-6
Using the equations for proper mirroring, I6 is determined to be
I6 = (15 × 10-6)(94.25/15) = 94.25 µA
Finally, calculate (W/L)7
94.25 × 10-6
(W/L)7 = 4.5 ≈ 14.14
30 × 10-6
Check the Vout(min) specification although the W/L of M7 is so large that this is
probably not necessary. The value of Vout(min) is
2 × 94.25
Vmin(out) = VDS7(sat) = = 0.348V
110 × 14.14
which is much less than required. At this point, the first-cut design is complete.
Examining the results shows that the large value of M7 is due to the large value of
M5 which in turn is due to a tight specification on the negative input common
mode range. To reduce these values the specification should be loosened or a
different architecture (i.e. p-channel input pair) examined.
Now check to see that the gain specification has been met
(2)(94.25 × 10-6)(942.5 × 10-6)
Av = = 19,240
30 × 10-6(.04 + .05)38 × 10-6(.04 + .05)
which meets specifications.
Allen and Holberg - CMOS Analog Circuit Design
Organization
Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS
COMPLEX
CIRCUITS
Chapter 5 Chapter 6
CMOS CMOS Amplifiers
Subcircuits
SIMPLE
Chapter 2 Chapter 3
Chapter 4 Device
CMOS CMOS Device
Characterization
Technology Modeling
DEVICES
Allen and Holberg - CMOS Analog Circuit Design
M9 M7
VDD VDD
vOUT
M1 M2
- VDD +
Cc
M8 CL
M6
M3 M4
Cc
vout
+
C1 r1 v1 CL r2 gm1 Ai
gm1 vi gm6 v1 vi
2
-
1 1
where gm1 = gm2, r1 = g , r 2 =
ds2 + g ds4 g ds6 + g ds7
Allen and Holberg - CMOS Analog Circuit Design
Network equations:
[g1 + s(C1 + CL)]v1 - sCcv2 = gm1vi
gm1AIvi
[g5 + sCc]v1 + [g2 + s(Cc + CL)]v2 = 2
i7
AI is the current gain from M1 to M7: AI = i
1
-g m6
z=
AI
- 1 Cc
2
-g1g2
p1 ≈
gm6Cc
-g m6
p2 ≈ C
L
gm1gm6
AV ≈ g g
1 2
Example:
VDD VDD
M9 M7 M9 M7
VDD VDD VDD VDD
-
M1
VDD
M2 + - M1 M2 +
Cc Cc
CL CL
M8
M6 M6
M3 M4 M3 M4
140
120
100
80
Gain(db)
Push-Pull phase
60
Standard gain
40
20 Push-Pull
gain
Standard phase
0
-20
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
Frequency
Allen and Holberg - CMOS Analog Circuit Design
Definition:
+ +
vdd VDD
- -
+
vout
vin + +
- VSS
vss
-
-
vout
Av(vdd=0) vin (vdd=0)
+
PSRR = A (v =0) = v
dd in out
vdd (vin=0)
Calculation of PSRR:
+ + Addvdd
vdd VDD
v1 vout
- -
vout v2 Av (v1 -v2 )
+ =>
VSS
-
+
+ VDD
vdd
- 1.) The M7 current sink
-
causes VGS6 to act like a
battery.
2.) Therefore, vdd
M3 M4
couples from the source
M6
M1 M2 Cc to gate of M6.
- + vout 3.) The path to the output
is through any capacitance
M5 M7 from gate to drain of M6.
+
VBias
-
+
VSS
-
4.) Resultant circuit
model- vout
+
vdd Cc Rout
-
+
VDD
-
M3 M4
M6
M1 M2 Cc
- + vout
M5 M7
+
VBias
-
? +
vss
+-
VSS
-
M5 or M7 iss M5
+
+ + VBias
VBias -
- vss
+
+- vss
VSS -+
- VSS
-
Capacitance injection:
vout
+
Cgd7 Rout
vss
-
Vout
Vss
1
Rout C gd7
0dB ω
Reduce Cgd7!
Allen and Holberg - CMOS Analog Circuit Design
• Insufficient gain
• Poor PSRR
• Folded cascode
Allen and Holberg - CMOS Analog Circuit Design
M3 M4
VDD VDD
VBP MC2
VDD
VO1
VBN
MC3 MC1
+ -
M1 M2
VBIAS
VSS
Gain ≈ gm2ro1
gmcrdsc
• Overall gain increased by ≈ 2
Common-mode improvement:
VDD
M3 M4
VDD VDD
ICM
VBP MC2
VDD
VO1
MC3 MC1
+ M9 -
M1 M2
VBIAS
VSS
A V = gm1ro1
-1
p1 ≈ C r
L o1
gm1
GB ≈ A V|p1| ≈
CL
VDD
M3 M4
ICM
ICM
VBP VDD
MC2
VSS
VSS VSS
MC1
MC3
I5 +ICM
VSS
Allen and Holberg - CMOS Analog Circuit Design
VDD
M4
MT2
M6
MC2
MT1
MC1
Vo
VSS
M2
M7
VBIAS
M5
VSS
Allen and Holberg - CMOS Analog Circuit Design
M3 M4
M6
M8
VB1
M9 Cc
vOUT
- M1 M2 +
M5
VB2 M7
VSS
+PSRR is reduced by M9
Disadvantage -
1
Miller pole is larger because R1 ≈
gm9
VDD
M3 M4
MT2
M6
VBP MC2
MT1
ICM
MC1
MC3 Vo
VSS
M9
M1 M2
M7
VBIAS
M5
VSS
Allen and Holberg - CMOS Analog Circuit Design
VDD
M3 M4
M6
VBP MC6
Comp Vo
VBN MC5
M1 M2
M7
VBIAS
M5
VSS
Allen and Holberg - CMOS Analog Circuit Design
VDD
M3 M4
M9 VDD VDD
M6
VDD VDD
MC3 MC2
VBP
VBP VDD
VDD - +
M1 M2 MC1
I5
M5 VBN VSS
VBIAS CL
M8 M7
VSS
A V1 = g
gm 2
gm2
m4
AV = 2(g ) (g m6 + gm9) Ro
A V2 = 2 (g m6 + g m9 )R o
1 m4
where
Ro ≈ (g mc2rdsc2)rds6 || (gmc1rdsc1)rds7 and M7 = M8
Or,
gm1 +g m2
AV = KR o
2
where
W6/L6 W 9/L 9
K=
W4/L4 = W3/L3
Allen and Holberg - CMOS Analog Circuit Design
Design Example
gm2
AV =
2(gm4) (gm6 + gm7 ) ro
g m2 (g m6 + g m7 )
GB = 2(gm4)CL
I5
Vin(max) = VDD - ß3 - |VT3|(max) + V T1(min)
I5
Vin(min) = VSS + VDS5 + ß1 + VT1(max)
Specifications:
VDD = -VSS = 5V
GB = 5 MHz
AV > 5000
CMR = ±3V
Design Procedure
S9 = S6 and S7 = S 8
∴ S 9 = S 6 = 2.5 S 4 = 2.5 S 3
Divide 2V equally,
∴ S 6 = S C2 = 62.5 --> S 3 = S 4 = 25
IOUT(sink) = 250 µA
MC1 -3
VBN -5V
VDSC1 = VGSC1 - V TC1 (ignoring bulk effects)
-4
1 = VGSC1 -1 --> VGSC1 = 2V
M7
∴ V BN = -2V
-5
I5
Vin (max) = VDD - ß3 - |VT03|max + VT1(min)
100 µA
+3 = +5 - - 1.2 + 0.8
KP'S3
100 µA
S3 = µA = 4.88 (Use S 3 = S4 = 25)
8 2 (1.6V) 2
V
b.) GB specification
g m1 (g m6 + g m7 )
GB = 2gm4 (50pF) = 10π.10 6 rps
(10π.106)(141.1.10-6)(50.10-12)
gm1 = = 627 µS
707.10-6/2
gm 2
∴ S 1 = S2 = = 231
I5K N '
I5
Vin (min) = VSS + VDS5 + ß1 + VT1(max)
100 µA
-3 = -5 + VDS5 + µA + 1.2
17 2 S 1
V
100
V DS5 = 0.8 - = 0.8 - 0.1596 = 0.641
(17)(231)
2(100 µA)
VDS5 (sat) = 0.641 = µA
(17 2 )S5
V
2(100µA)
S5 = = 28.6
17µA/V 2(0.641)2
9.) VBIAS -
KN'.28.6
I5 = 2 ( V BIAS + 5 -1) 2 = 100 µA
= 3.5mW
Principle
VDD
1.5 I 1.5 I
VBP M4
M3
I
v+IN vout =gm1 Rout vin
M1 M2 v-IN
I
M5 M6
M7 M8
VSS
Advantages
Self compensating.
Allen and Holberg - CMOS Analog Circuit Design
VB3
M4
M3
- + VB3 M14
M1 M2 V OUT
M9 Cc
M8
M16
VB1 M5
M15
VB2 M11
M10
M13
M12
VSS
+
- - R R
-
+ +
-
+
VDD
Vin
- +
- Vout
CL CL
Common
mode
feedback
VSS
Allen and Holberg - CMOS Analog Circuit Design
VDD = +5V
MP1A
MP1 VBIAS1
MP2A
VDD VDD VBIAS2
MP2
-
vOUT
CL +
+ CL
MN2A
vIN
VSS VSS VBIAS3
-
MN2
MN1 MN1A
VSS VSS VBIAS4
VSS
MN3
MN3A
VSS = -5V
Allen and Holberg - CMOS Analog Circuit Design
VDD VDD
VB2
v+IN v-IN
vOUT vOUT
v-IN v+IN
VB1
VSS VSS
combine
v+IN M1 M2 v-IN
v+IN M3 M4 v-IN
M5 M6
v+OUT v+IN M1 M2 v-IN v-OUT
M7 M8
M3 M4
I I
M18 M10 M9 M13
VB1 VB3
M16
M5 M6
v+OUT v+IN M1 M2 v-IN v-OUT
VB2 VB4
M8 M15
M3 M4
M7
I I
M18 M10 M9 M13
General
Objective is to minimize the dc power dissipation.
Typical applications are:
1. Battery powered circuits.
2. Biomedical instrumentation.
3. Low power analog "VLSI."
W qvGS
iD = I D exp nkT ( 1 + lv D S)
L
Device characteristics -
iD iD
square
law
100nA
100nA
weak exponential
inversion vGS < VT
vDS vGS
1 2 VT
Allen and Holberg - CMOS Analog Circuit Design
where,
VDD
M3 M4
M6
C
M1 M2
M7
M5
VSS
Allen and Holberg - CMOS Analog Circuit Design
Design Example
Calculate the gain, unity-gain bandwidth, and slew rate of the previous
two-stage op amp used in weak inversion if:
L = 10 µm nN = 2.5 λN = 0.01V-1
C = 5pF T = 27˚C
1
AV = (1.5)(2.5)(0.026)(2)(0.1+0.02)(0.01+0.02) = 5698
100.10-9
GB = = 307.69Krps or 48.97KHz
(2.5)(0.026)(5.10-12)
SR = 2(153.85.103)(2.5)(0.026) = 0.04V/µs
If V DD = -V SS = 2.5, the power dissipation is 0.2µW assuming ID7 = I D5.
Allen and Holberg - CMOS Analog Circuit Design
VDD
M3 M4
M8 M6
M1 M2
CC
VB M5
M9 M7
VSS
M11
M3 M10 M12 M4
M8 M6
M1 M2
CC
M5
VB M13
M9 M7
VSS
Allen and Holberg - CMOS Analog Circuit Design
VDD
M3 M4
M8 M6
VB1
M1 M2 VDD
M10
VB2 VSS CC
VB M5 M11
M9 M7
VSS
1 1
+ n
nN P
AV = 2 ≈ 10,000
Vt ( λ P n P + λ N 2 n N 2 )
2
self-compensating
Low power << 1 µW
Allen and Holberg - CMOS Analog Circuit Design
Micropower Op Amp
VDD
M5 M6
M9 M7 M8 M10
M16
va vb M15 M18
M3 M4 100nA
v-1 v+2 vo
M19
M17
M2
VBIAS M14
M11 M12
120nA 20nA 20nA
VSS
where
ro ≈ (rds10gm18rds18)||(rds12gm19rds19)
and
nP 1 + k
(va - vb) = va - vb = n 1 - k ( v 2 - v 1 )
N
Small-Signal Analysis
va vb
gm3 g m8
va = -v1 g - vb g
m5 m5
gm4 g m7
vb = -v2 - v a
gm6 gm6
v1ggm5
m3
gm8
va
-1 -g
m5
v2gm4
=
gm7 v
gm6 -g
m4
-1
b
gm3 gm8
v1g -g
m5 m5
gm4 gm 3 g m4 g m 8
v2g
m6
-1 -v 1 g + v 2 g g
m5 m5 m6
va = =
-1
gm8
-g 1-
g m7 g m 8
m5 gm5 gm6
gm7
-g
m4
-1
Allen and Holberg - CMOS Analog Circuit Design
gm3
-1 v1g
m5
gm7 gm4 gm 4 g m3 g m 7
-g
m6
v2g
m6 -v 2 g + v 1 g g
m6 m5 m6
vb = =
-1
gm8
-g 1-
g m7 g m 8
m5 gm5 gm6
gm7
-g
m4
-1
gm3 g m4 g m 8 gm4 g m3 g m 7
-v1 - -v2
gm5 gm6
+ v 2 + v 1
gm5 gm5 gm6 gm6
v a - vb = g m7 g m 8
1- g g
m5 m4
Then
gmIII
Define:
gmII = k
gmI gmI
v
( 2 - v 1) g ( 1 + k)
mII gmII
v a - vb = = ( v 2 - v1)
1 - k2 1 - k
gmI 1
gmII 1 - k ( v 2 - v 1 )
v a - vb =
I 3 = I5 + I8
Allen and Holberg - CMOS Analog Circuit Design
S8 S7
I 8 = I6 S ; I 7 = I 5 S
6 5
I8 S 8
⇒ in W.I. gm is proportional to I
I6 = S6
I 8 S8 I 7 S7
= = k;
I6 S6 I5 = S5 = k
I4 = I6 (1 + k)
I3 = I5 (1 + k)
I6
gm4 ∝ I 6(1 + k) or gm4 =
kT (1 + k)
nN
q
and
gm3 ∝ I5(1 + k)
since
I6
gm3 = gm4 = gmI ⇒ gmI =
k T (1 + k)
nN
q
Also
I6
gm4 = gmII =
kT
nN
q
then
gmI nP
gmII n N (1 + k)
=
Allen and Holberg - CMOS Analog Circuit Design
finally:
nP 1 + k
v a - vb = n ( v 2 - v 1 )
N 1 - k
1 + k
≈ 1 - k ( v 2 - v1)
Therefore,
1+k
vo = gm9 ro 1-k vid
Allen and Holberg - CMOS Analog Circuit Design
Need large sinking and source currents without having to have large
quiescent currents.
One possible solution uses "tail current boosting" -
Assume that S 3 = S4 = S11 = S13, S18 = AS17, S15 = S16 = S17 = ..
M11 M13
M3 M4
I1 I2
I2
- +
M1 M2
I1
I2 I2 +I1 +A I2 -I1
W18 = AW17
L18 L17
Allen and Holberg - CMOS Analog Circuit Design
iD
I10 (overdrive)
I10 (normal)
I10 (overdrive)
2
I10 (normal)
2
vIN
0
I10 (overdrive) I10 (overdrive)
-
B B
I10 (normal) I10 (normal)
-
B B
Positive feedback -
I10 I10 I10
iOUT (max/min) ≈ 1 - Loop gain = =
g m 1 8 gm 1 3 gm 1 3
1- g 1- g A
m17 gm14 m9
Allen and Holberg - CMOS Analog Circuit Design
VDD
I1 I2
- +
M1 M2 VBP
M5B
vOUT
M6B
VBN
I10
M7 M15 M16 M17 M18 M9 M10 M19 M20 M21 M22 M6A
VSS
Allen and Holberg - CMOS Analog Circuit Design
A=2
A = 1.5
IOUT 1
A=1
I10
A = 0.3
A=0
0
0 1 2
vIN/ nVt
Allen and Holberg - CMOS Analog Circuit Design
φ1
φ1 switches
on
φ1 switches
t/T
off 0 1 2 3 4 5
φ2
φ2 switches
on
φ2 switches t/T
off 0 1 2 3 4 5
φ2 φ1
D
Pretune φ2 G VSS RFET
circuit CG
φ2 φ1
S
Switched resistor
Allen and Holberg - CMOS Analog Circuit Design
i
+ D
- D1 M1
VC
+ G1 VSS
D2 S1 vDS RFET
M2
G2 +
VSS
VC
S2 -
- S
φ2 φ1
CG
φ2
VSS
Pretune M2
RFET
circuit
φ2
VSS
CG M1
φ2 φ1
Switched resistor
Allen and Holberg - CMOS Analog Circuit Design
CB
M2
iD
φ2 φ2
vOUT
COS
φ1
M1
+
vIN
φ2 VSS
-
During phase 2 the offset and bias of the inverter is sampled and
applied to C OS and C B.
Simplified schematic -
VDD
+
VB2 φ1 φ2
-
M8 M4
M7 M3
VDD VDD
C2
φ2 φ1
IB v-IN v+IN vOUT
C1
M6 M2
VSS VSS
φ1 φ2
M5 + M1
VB1
-
VSS
Allen and Holberg - CMOS Analog Circuit Design
M8
M7
VDD
+ VDD - VB2 - v+IN
C2
-
IB v+IN
C1
v+IN - VSS - VB1
VSS
M6
M5
VSS
M3 VDD
+
VDD - VB2 - v+IN - C2
v-IN vOUT
v+IN - VSS - VB1 C1
M2
VSS
VSS
Allen and Holberg - CMOS Analog Circuit Design
φ2 φ1
M8 φ1 φ2 M4
M7 M3
VDD VDD
C2 C4
φ1 φ2
C1 C3
M6 M2
VSS VSS
φ2 φ1
M5 M1
φ1 φ2
VSS
Chapter 10
Chapter 11
D/A and A/D
Analog Systems
Converters
SYSTEMS
COMPLEX
CIRCUITS
Chapter 5 Chapter 6
CMOS CMOS
Subcircuits Amplifiers
SIMPLE
Chapter 2 Chapter 3
Chapter 4 Device
CMOS CMOS Device
Characterization
Technology Modeling
DEVICES
Allen and Holberg - CMOS Analog Circuit Design Page X.0-2
ANALOG
SIGNAL PRE-PROCESSING DIGITAL POST-PROCESSING ANALOG
(Speech, (Filtering and analog PROCESSOR (Digital to analog OUTPUT
sensors, to digital conversion) (Microprocessor) conversion and SIGNAL
radar, filtering)
etc.)
CONTROL
Transmission links
Analog computer
Magnetic tape recorders
Audio signals
Computer memories
Video signals
Paper tape recorders
Power sources
Chemical cells Analog Real-time processor
Synchros/resolvers
Sample to Digital Comparators
Multi- and Digital System System and process
Pressure cells
Thermocouples
plexer Hold Converter controls
Numerical machine
Strain gages
controls
Bridges
Minicomputers
Photomultiplier
Miroprocessors
Etc.
Etc.
Reference
Reference
Allen and Holberg - CMOS Analog Circuit Design Page X.1-1
Reference
b0
b1
b2 Digital-to-
b3 vOUT or iOUT
Analog
Converter
bN-1
where
K = gain constant (independent of digital input)
b0 b1 b2 b N-1
D = N + N-1 + N-2 + ···· + 1 = scaling factor
2 2 2 2
Vref (I ref ) = voltage (current) reference
bN-1 = most significant bit (MSB)
b0 = least significant bit (LSB)
For example,
b0 b1 b2 bN - 1
vOUT = KV ref N + N-1 + N-2 + ···· +
2 2 2 21
N-1
= KVref N
1
2 ∑ b j2 j
j=0
Allen and Holberg - CMOS Analog Circuit Design Page X.1-2
Binary Switches
b0 b1 b2 bN-1
Clocked D/A Converter-
Vref
b0
b1
b2 Digital V
to out Sample V*out
Latch and
analog hold
converter
bN-1
Clock
Allen and Holberg - CMOS Analog Circuit Design Page X.1-3
D/A Converters
Serial Parallel
Slow Fast
Allen and Holberg - CMOS Analog Circuit Design Page X.1-4
1.000
0.875
0.750
1 LSB
Analog Ouput Value
0.625 Ideal
analog
output
0.500
0.375
0.250
0.125
0.000
000 001 010 011 100 101 110 111
Digital Input Code
Vref
An ideal LSB change causes an analog change of
2N
Allen and Holberg - CMOS Analog Circuit Design Page X.1-5
Definitions
VREF -VREF
-0.5LSB -0.5 =
000 001 010 011 2N 2 N+1
Dynamic range (DR) is the ratio of FS to the smallest resolvable
difference.
2N − 1
V REF
FS 2N
DR = LSB change = 1 = 2N − 1
VREF N
2
DR(dB) = 20 log 10( 2 − 1) ≅ 6N dB
N
2N
Full scale RMS value 2 2 12 N
SNR = RMS value of quantization noise = = 2
1 2 2
12
6 6
SNR (dB) = 20 log 10 2 N = 20 log 10 + 20 log10 (2 N)
2 2
Definitions - Continued
Full scale (FS) is the the maximum DAC analog output value. It is one LSB
less than V REF .
2N − 1
FS = VREF
2N
VREF
1 LSB
5
8
(Ratio to VREF)
1 Ideal
2 analog
output
3
8
1
4
1
8
0
000 001 010 011 100 101 110 111
0 1 2 3 4 5 6 7 8
8 8 8 8 8 8 8 8
7 7
8 8
Gain Error
5 5
8 8
3 3
Offset 8 8
Error
1 1
8 8
0 0
000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111
Offset Error Gain Error
Nonmonotonicity
7 7
8 Nonlinearity 8
5 5
8 8
3 3
8 8
1 1
8 8
0 0
000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111
Linearity Error Nonmonotonicity
(Due to Excessive Differ-
ential Nonlinearity)
Typical sources of errors
Allen and Holberg - CMOS Analog Circuit Design Page X.1-9
10
Analog output (Ideal LSB) 9 0.5 LSB
8
5 1.5 LSB
4
3
Ideal
2
0
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1011
Digital word output
Ideal
10
9
0 LSB
Analog output (Ideal LSB)
6 1 LSB
4
2 LSB
3
0
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1011
Digital word output
Allen and Holberg - CMOS Analog Circuit Design Page X.2-1
MSB: b2
LSB: b0
+VREF
b0 b0 b1 b1 b2 b2
R/2
8
R
7
R
6
R
5
R vOUT
4
R
3
R
2
R
1
R/2
VREF V REF 11
vOUT = D+0.5 = 2D+1 = 0.6875V =
8 ( ) 16 ( ) REF 16 VREF
Allen and Holberg - CMOS Analog Circuit Design Page X.2-2
VREF
7VREF
8
6VREF
8
5VREF
8
OUT
4VREF
8
3VREF
8
2VREF
8
VREF
8
Input
000 001 010 011 100 101 110 111
Advantages:
Inherent monotonicity
Compatible with CMOS technology
Small area if n < 8 bits
Disadvantages:
Large area if n > 8 bits
Requires a high input impedance buffer at output
Integral linearity depends on the resistor ratios
Allen and Holberg - CMOS Analog Circuit Design Page X.2-3
b0 b1 b2
+VREF
R/2
3-to-8 Decoder
8
R
7
R
6
R
5
R vOUT
4
R
3
R
2
R
1
R/2
Allen and Holberg - CMOS Analog Circuit Design Page X.2-4
The difference between the ideal and worst case voltages is,
Vk Vk' kR kRmin
- = -
VREF VREF 2NR ( 2N-k) R max + kR min
Assuming that this difference should be less than 0.5 LSB gives,
kR kRmin 0.5
- <
2NR ( 2N-k) R max + kR min 2N
0.5(R- 0.5∆R) 1 ∆R 1
0 . 5 - 0.5(R + 0.5∆R) + 0.5(R- 0.5∆R) = 4 R < 2 2-N
∆R 1
⇒ < N-1 or 0.25(0.02) < 0.5( 2-N) ⇒ N = 6
R 2
Allen and Holberg - CMOS Analog Circuit Design Page X.2-5
2R 2R 2R 2R 2R 2R
b0 b1 b2 b N-1 bN
+
VREF
-
Equivalent circuit at A:
R A
b0 VREF +
2 -
Equivalent circuit at B:
R R B R B
2R +
+
b0 VREF + = ( b4 + b2 )V
0 1
REF
b1 VREF -
- 2
-
vOUT
R Q R
+ -
b0 b1 b2 b
-
( 2N
+ N-1
2
+ N-2
2
+...+ N-1 VREF
2 ) +
R
sign bit
bN
-
VREF
+
Allen and Holberg - CMOS Analog Circuit Design Page X.3-1
-
C C C v OUT
C C 2N-2 2N-1 2 N-1
C +
φ 2 4
1
SN-1 SN-2 SN-3 S1 S0
φ φ φ φ φ
2 2 2 2 2 Terminating
capacitor
VREF
Operation:
1.) During φ1, all capacitors are discharged.
Ceq.
vOUT = 2C VREF
+ Ceq.
VREF vOUT
2C-Ceq.
-
Allen and Holberg - CMOS Analog Circuit Design Page X.3-2
Four-Quadrant Operation:
If VREF can have ±values, then a full, four quadrant DAC can be
obtained.
Multiplying DAC:
If VREF is an analog signal (sampled and held), then the output is the
product of a digital word and an analog signal and is called a multiplying
DAC (MDAC).
Allen and Holberg - CMOS Analog Circuit Design Page X.3-3
v'OUT Ceq.(min)
VREF = 2C - C eq.
(max) + C eq. (min)
The difference between the ideal output and the worst case output is,
1pF
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b 10 b 11 b12
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b 10 b 11 b 12 +VREF
-VREF
5 ±b iCi VREF 12 ±bi Ci VREF
VL =∑ VR = ∑
i=0 64 i=6 127
An equivalent circuit-
1 1 64
+ C = 1 ⇒ C = 63 ≈ 1.016
64
+ 1 63 1
+ 64
1.016pF 64 127
64pF 127pF vOUT = 1 63 1 V R + 1 VL
1 63
+ 64 + 127 + 64 + 127
+ + 64 64
VL VR
- - 127 1
- = 128 V R + 128 VL
∑ ∑
12 5
±biVREFCi ±biVREFCi
VR = and VL=
127 64
i=6 i=0
or
12
±VREF ∑
+ ∑ 64
5
biCi
vOUT = 128
i=6 b iC i
i=0
Allen and Holberg - CMOS Analog Circuit Design Page X.3-5
VREF
φ b b φ b b φ b b φ b b φ b b φ b b φ b b φ b b
1 0 0 1 1 1 1 2 2 1 3 3 1 4 4 1 5 5 1 6 6 1 7 7
C C C C
C C C C
8 4 2 8 4 2
C
8 φ
1
2C
-
v OUT
+
Allen and Holberg - CMOS Analog Circuit Design Page X.4-1
R(2M-1)
SF
v OUT
R(2M-2)
Ck-1 C k-2 C1 C0
R(2M-3) 2C C C
2k-1 C 2k-2
C
M=4 k=8
SA A
R1 S(k-1)A S(k-2) A S1A S0A
Advantages:
• Resistor string is inherently monotonic so the first M bits are
monotonic.
• Can remove voltage threshold offsets.
• Switching both busses A and B removes switch imperfections.
• Can make tradeoffs in performance between the resistors and
capacitors.
• Example with 4 MSB's voltage scaling and 8 LSB's charge scaling:
Allen and Holberg - CMOS Analog Circuit Design Page X.4-2
2k-1 C 2k-2 C 2C C C
vOUT
A
+ S k,A S k-1,A S 2A SA
2-MV REF
- S k,B S k-1,B S 2B SB -
B
+
V 'REF
-
Ceq.
+ M+K-1
∑bi2-(M+K-i) VREF
+
2-MVREF vOUT =
2KC - Ceq. vOUT
- i=0
-
+
V 'REF
-
Allen and Holberg - CMOS Analog Circuit Design Page X.4-3
4C 2C C
MSBs R
LSBs
Conversion sequence:
4 Bit D/A Converter
INPUT WORD: 1101
1 Close S4: VC2 = 0
3/4 13/16 Start with LSB first-
Close S2 (b0=1): VC1 = VREF
VC1 /VREF 1/2
VREF
1/4 Close S1: VC1 = 2 = VC2
Close S3 (b1=0): VC1 = 0
0 2 4 6 8
VREF
Close S1: VC1 = VC2 = 4
1
13/16 Close S2 (b2=1): VC1 = VREF
3/4
5
VC2 /VREF 1/2 Close S1: VC1 = VC2 = 8 VREF
1/4 Close S2 (b3=1): VC1 = VREF
13
Close S1: VC1 = VC2 = 16 VREF
0 2 4 6 8
Comments:
• LSB must go first.
• n cycles to make an n-bit D-A conversion.
• Top plate parasitics add error.
• Switch parasitics add error.
Allen and Holberg - CMOS Analog Circuit Design Page X.5-2
b0 b1 bN-1
LSB MSB
VREF
bN-1 bN-2 b0
vOUT (z) = 2 z-1 + 4 z -2 +.... + N z-N VREF
2
where bi = 1 or 0
Approaches:
1.) Pipeline with N cascaded stages.
2.) Algorithmic.
bi z-1VREF
vOUT(z) =
1 - 0.5z - 1
Allen and Holberg - CMOS Analog Circuit Design Page X.5-3
1
2
Assume that the digital word is 11001 in the order of MSB to LSB. The
steps in the conversion are:
Digital y(kTN)
x(t) Processor
1.) Serial.
111
Ideal A/D conversion
110
Output digital number
101 Normal
quantized
value
100 (± 1/2 LSB) Ideal
transition
011
010
1 LSB Ideally
001 quantized
0
1 2 3 4 5 6 7 analog
8 8 8 8 8 8 8 input
000
1 FS 2 FS 3 FS 4 FS 5 FS 6 FS 7 FS FS
8 8 8 8 8 8 8
Normal quantized value (± LSB)
Allen and Holberg - CMOS Analog Circuit Design Page X.6-3
Offset
error
111 111
Gain error
110 Ideal 110
101 101
100 100
011 011
Ideal
010 010
001 001
000 000
1 FS 1 FS 3 FS FS 1 FS 1 FS 3 FS FS
4 2 4 4 2 4
Analog input value Analog input value
Offset Error Scale factor (gain) error
111 111
Ideal
110 110
Digital output code
Digital output code
101 101
Ideal
100 100
Missed
011 011 codes due to
excessive
010 Nonlinearity 010 differential
nonlinearity
001 001
000 000
1 FS 1 FS 3 FS FS 1 FS 1 FS 3 FS FS
4 2 4 4 2 4
Analog input value Analog input value
Integral Nonlinearity Differential Nonlinearity
Allen and Holberg - CMOS Analog Circuit Design Page X.6-4
S-H command
Sample
Hold Hold
S*
S(t)
S*
S(t)
t
Tsample = ts + ta
ta = acquisition time
ts = settling time
kT
Noise = C V 2 (rms)
Allen and Holberg - CMOS Analog Circuit Design Page X.6-5
Simple
-
vO
φ A1
vI +
CH
Improved
φ
φ -
vO
- φ A2
A1 +
vI +
CH
Waveforms
v0(t)
v1(t),v0(t)
v1(t)
Volts
vIN*
NT NT
vr Output
Ramp - counter
VREF generator vr
vIN*
Reset Output
t
0 NT
Interval
counter
f= 1
T
clock
• Simplicity of operation
Block Diagram:
1
Vin*
Positive vint
2 integrator +
-VREF
Vth -
Digital
control
Binary
Counter output
Operation:
1.) Initially vint = 0 and vin is sampled and held (Vin* > 0).
NrefT
⌠ * *
vint(t1) = vint (NrefT) = k ⌡Vin dt + vint(0) = kNrefTVin + Vth
0
*
4.) The Carry Output on the counter is used to switch the integrator from Vin to -V REF.
Integrate until vint is equal to Vth resulting in
NoutT + t1
vint(t1 + t2) = vint(t1) + k ⌠
⌡-VREFdt = V th
t1
* Nout *
∴ kNref TVin + Vth - kVREFNoutT= Vth ⇒ VREF N = V in
ref
Allen and Holberg - CMOS Analog Circuit Design Page X.7-3
vin
V'''in
V''in
V'in
Vth
0 t
0
t1 = NrefT t'2
Reset
t0 (start) t''2
t'''2
t2 = Nout T
Noninverting:
C1 C2
+ φ1 φ2 +
-
v1 (t) φ2 φ1 v2 (t) fsignal << fclock
+
- -
Operation:
Assume non-overlapping clocks φ1 and φ2. During φ1, C1 is charged to v1[ ( n-1) T]
giving a charge of q1[ ( n-1) T] on C1. During φ2, the charge across C1 is added to the charge
already on C2 which is q2[ ( n-1) T] resulting in a new charge across C2 designated as
q2( nT) . The charge equation can be written as,
C1
-jωT
H(ejωT) =
C1 e
-jωT
=
e 2
C2 jω
e 2 - e-jω2
C2 1 - e-jωT T T
ωo ( ωΤ/2) ωo 1
= exp( -jωΤ/2) ≈ if f << fc = T
jω sin( ωΤ/2) jω
ejx - e-jx
where ωο = C1/( TC2) , sinx = 2j
Allen and Holberg - CMOS Analog Circuit Design Page X.7-6
ωc
ωo =
2π
ωT 2πf πf πω
= 2f = f =
2 c c ωc
Log Plot-
10
ωT
ωo 2
ω sin ωT
2
H(ejωt ) dB 0
ωo =0.5ωc
ωo
ω π
-10
0.1 1 2 3 4 5
ω
πω
c
Linear Plot-
10
H(ejωt ) ωT
ωo 2
4
ω sin ωT
2 ωo
ω
2
π
0
0 0.5 1 1.5 2 2.5 3 3.5
ω
πω
c
Allen and Holberg - CMOS Analog Circuit Design Page X.7-7
Inverting:
C1 C2
+ φ2 φ2 +
-
v1 (t) φ1 φ1 v2 (t)
+
- -
jωT ωo
H(e )≈- , if f << fc = 1/T
jω
Important when the op amp plus feedback circuit has two or more
poles or the op amp has a second pole.
φ1
t
φ2
t
vout Slew Rate
t
Settling Time
Allen and Holberg - CMOS Analog Circuit Design Page X.8-1
Conversion Time ≈ NT
Successive ApproximationArchitecture:
Conditional
gate
Input
Comparator
D/A Output
Converter register Shift
register Clock
Reference
Output
End of
Start conversion
Successive Approximation Process:
vo
VREF
0.5VREF
t
0 1 2 3 4 5 6 T
Allen and Holberg - CMOS Analog Circuit Design Page X.8-2
Vref
R1 SF
R2 _
R3 +
2K-1C 2C C C
SA A
R 2 M-1 SB B
Operation:
1.) With SF closed, the bottom plates of all capacitors are connected through switch SB to
Vin*. (Automatically accounts for voltage offsets).
2.) After SF is opened, a successive approximation search among the resistor string taps to
find the resistor segment in which the stored sample lies.
3.) Buses A and B are then connected across this segment and the capacitor bottom plates
are switched in a successive approximation sequence until the comparator input
voltage converges back to the threshold voltage.
V*in +
Data storage
register
-
S2 precharge
Serial D/A control
S3 discharge
Vref D/A register
converter S1 charge share
(Fig. 10.3-1) S4 reset
Shift left
Start Sequence and Parallel data transfer
control logic Shift right
Clock
Conversion Sequence:
1 1 1
Digital word = aM N + aN-1 + ... + a N-K +1 +.
2 2N-1 2N-K+1
2.) Assume (K + 1)th MSB is 1 and compare this analog output with Vin* to
determine aN-K.
3/4 13/16
Close S4: VC2 = 0
VC1 /VREF 1/2 Store with LSB first-
1/4 Close S2 (b0=1): VC1 = VREF
VREF
Close S1: VC1 = 2 = VC2
0 2 4 6 8
Close S3 (b1=0): VC1 = 0
1 VREF
13/16 Close S1: VC1 = VC2 = 4
3/4
3
4
1
2
vc1 /Vref
1
4
t/T
0 1 2 0 1 2 3 4 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8
3
4
1
2
vc2 /Vref
1
4
t/T
0 1 2 0 1 2 3 4 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8
Allen and Holberg - CMOS Analog Circuit Design Page X.8-6
• Requires N comparators
MSB LSB
bi
+ - + - + -
2 vi-1 2 vi
V*in ∑ z-1 ∑ z-1
±1 ±1
Vref
ith stage
N N-1 N
VN = ∏ i in ∑ ∏Aj bi + bN Vref
A V -
i=1 i=1 j=i+1
where Ai and bi are the gain and bit value of the ith stage
Allen and Holberg - CMOS Analog Circuit Design Page X.8-7
Example 1
x2 -VREF
1 1 1 1
3/4 3/4 3/4 3/4
x2 -VREF
1/2 1/2 1/2 1/2
1/4 1/4 1/4 1/4
x2 +VREF
0 0 0 0
-1/4 -1/4 -1/4 -1/4
-1/2 -1/2 -1/2 -1/2
-3/4 -3/4 -3/4 -3/4
-1 -1 -1 -1
B=1 B=1 B=0 B=1
Example 2
1 1 1 1
x2 -VREF
3/4 3/4 3/4 3/4
1/2 1/2 -VREF 1/2 1/2
1/4 1/4 1/4 1/4 x2 +VREF
x2
0 0 0 0
-1/4 -1/4 -1/4 -1/4
-1/2 -1/2 -1/2 -1/2
-3/4 -3/4 -3/4 -3/4
-1 -1 -1 -1
B=0 B=1 B=0 B=1
Allen and Holberg - CMOS Analog Circuit Design Page X.8-8
Vi Vi-1
ith Stage Plot of: V = 2 V − bi
ref ref
Vi
Vref
bi+1 =+1
Vi-1
-1 -.5 0 .5 1 Vref
bi+1 =-1
-1
bi =-1 bi =+1
bi ,bi+1 [00] [01] [10] [11]
1.) bi+1 must change at 0, and ±0.5Vref. (when Vi-1=0 and ±0.5Vre f)
IDEAL PERFORMANCE
Example
Vin b(i) v(i+1) b(i+1) v(i+2) b(i+2) v(i+3) b(i+3) v(i+4) b(i+4) v(i+5)
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-0.9 -1 -0.8 -1 -0.6 -1 -0.2 -1 0.6 1 0.2
-0.8 -1 -0.6 -1 -0.2 -1 0.6 1 0.2 1 -0.6
-0.7 -1 -0.4 -1 0.2 1 -0.6 -1 -0.2 -1 0.6
-0.6 -1 -0.2 -1 0.6 1 0.2 1 -0.6 -1 -0.2
-0.5 -1 0 1 -1 -1 -1 -1 -1 -1 -1
-0.4 -1 0.2 1 -0.6 -1 -0.2 -1 0.6 1 0.2
-0.3 -1 0.4 1 -0.2 -1 0.6 1 0.2 1 -0.6
-0.2 -1 0.6 1 0.2 1 -0.6 -1 -0.2 -1 0.6
-0.1 -1 0.8 1 0.6 1 0.2 1 -0.6 -1 -0.2
0 1 -1 -1 -1 -1 -1 -1 -1 -1 -1
0.1 1 -0.8 -1 -0.6 -1 -0.2 -1 0.6 1 0.2
0.2 1 -0.6 -1 -0.2 -1 0.6 1 0.2 1 -0.6
0.3 1 -0.4 -1 0.2 1 -0.6 -1 -0.2 -1 0.6
0.4 1 -0.2 -1 0.6 1 0.2 1 -0.6 -1 -0.2
0.5 1 0 1 -1 -1 -1 -1 -1 -1 -1
0.6 1 0.2 1 -0.6 -1 -0.2 -1 0.6 1 0.2
0.7 1 0.4 1 -0.2 -1 0.6 1 0.2 1 -0.6
0.8 1 0.6 1 0.2 1 -0.6 -1 -0.2 -1 0.6
0.9 1 0.8 1 0.6 1 0.2 1 -0.6 -1 -0.2
1 1 1 1 1 1 1 1 1 1 1
Allen and Holberg - CMOS Analog Circuit Design Page X.8-10
1
0.8
0.6
0.4
Inputs (Volts)
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
VIN
(Volts)
Allen and Holberg - CMOS Analog Circuit Design Page X.8-11
• Summer offset (k 5)
Illustration:
+
bi Vref
-
±k2 ±k5
±k3
+ - +
+ ∑
Vi-1 2 ∑ + ∑ ∑ Vi
+ +
+ +
±k1 ±k4
N N-1 N
VN = ∏ i in ∑ ∏AjVOSi + VOSN
A V +
i=1 i=1 j=i+1
N-1 N
- Vref ∑ ∏Aj Asibi + A sNbN
i=1 j=i+1
N N-i
- V ref∑( A ) Asbi
N
VN = A NVin + ∑( AN-i) VOS
i=1 i=1
Assuming only the first stage has errors:
N
VN = A12N-1Vin + 2N-1VOS1 - Vref2N-1As1b1 - Vref ∑( 2N-i) bi
i=2
Allen and Holberg - CMOS Analog Circuit Design Page X.8-13
Identification of Errors
1. Gain Errors
∆A 1
2N( ∆A/A) < 1 ⇒ N=10 ⇒ <
A 1000
Vi
Vref
2∆A
1+
1 A
2∆A
1-
A
bi+1 =+1
Vi-1
-1 0 1 Vref
bi+1 =-1
-1
bi =-1 bi =+1
Allen and Holberg - CMOS Analog Circuit Design Page X.8-14
Vref
VOS <
2N
Vi
Vref
1+VOS
1
1+VOS
bi+1 =+1
Vi-1
-1 0 1 Vref
bi+1 =-1
-1
bi =-1 bi =+1
Allen and Holberg - CMOS Analog Circuit Design Page X.8-15
∆A s 1
<
A s 2N
∆A 1
For N=10, A <
1024
Vi
Vref
1+∆As /As
1-∆As /As
Vi-1
-1 -0.5 0.5 1 Vref
-1+∆As /As
-1-∆As /As
Allen and Holberg - CMOS Analog Circuit Design Page X.8-16
The comparator offset error is any nonzero value of the input to a stage where the stage
bit is caused to change. It can be expressed as:
Vi = 2Vi-1 - biVref
where
Vi
Vref
bi+1 =+1
Vi-1
-1-1 -0.5 0.5 1 Vref
bi+1 =-1
bi =-1 bi =+1
VOC = ?
Allen and Holberg - CMOS Analog Circuit Design Page X.8-17
SUMMARY
1.) The 1-bit/pipe, pipeline converter which uses standard components including a sample
and hold, an amplifier, and a comparator would be capable of realizing at most an 8 or 9 bit
converter.
2.) The accuracy of the gains and offset of the first stage of an N-Bit converter must be
within 0.5LSB.
3.) The accuracy of the gains and offset of a stage diminishes with the remaining number
of stages to the output of the converter.
4.) Error correction and self-calibrating techniques are necessary in order to realize the
potential resolution capability of the 1-bit/'stage pipeline ADC.
Allen and Holberg - CMOS Analog Circuit Design Page X.8-18
If Voi is stored and feedback to the input, the same stage can be used for the
conversion. The configuration is as follows:
Comparator
Voi
X2
+1 +Vref
Sample +1
and ∑
hold -Vref
Practical implementation:
Comparator
Va
X2 + Vo
+Vref -
Vo = "1"
+1 +Vref
Vb -1
Sample ∑
and
hold S1 Vo = "0"
Vin
Allen and Holberg - CMOS Analog Circuit Design Page X.8-19
2.) Va(0) is 1.6VREF (b1=1) which causes -VREF to be subtracted from Va(0) giving
3.) In the next cycle, Va(1) is 1.2VREF (b2=1) and Vb(1) is 0.2VREF.
4.) The next cycle gives Va(2) = 0.4VREF (b3=0) and Vb(2) is 0.4VREF.
5.) The next cycle gives Va(3) = 0.8VREF (b4=0) and Vb(3) is 0.8VREF.
6.) Finally, V a(4) = 1.6V REF (b5=1) and V b(4) = 0.6V REF.
Va/VREF Vb /VREF
2.0 2.0
1.6 1.6
1.2 1.2
0.8 0.8
0.6
0.4 0.4
0.2
0 t t
0 1 2 3 4 5 T 1 2 3 4 5 T
Allen and Holberg - CMOS Analog Circuit Design Page X.8-20
Practical Converter
12 Bits
SELF-CALIBRATING ADC's
S1
MAINDAC TO SUCCESIVE
COMP APPROXIMATION
CN CN-1 C1B C1A CCAL
REGISTER
Vref
GND
REGISTER
CALIBRATION ADDER
SUBDAC DAC
DATA REGISTER
SUCCESSIVE CONTROL
APPROXIMATION LOGIC
REGISTER
VεN VεN-1
DATA OUTPUT
Self-Calibration Procedure
During calibration cycles, the nonlinearity factors caused by capacitor mismatching are
calibrated and stored in the data register for use in the following normal conversion cycles.
The calibration procedure begins from MSB by connecting CN to VREF and the
remaining capacitors CNX to GND, then exchange the voltage connection as follows:
VX
VX
CN CNX CN CNX
VREF VREF
CNX - CN
VX = VREF
CNX + C N
otherwise VX ≠ 0. This residual voltage VX is digitized by the calibration DAC. Other less
significant bits are calibrated in the same manner.
After all bits are calibrated, the normal successive-approximation conversion cycles
occurs. The calibrated data stored in the data register is converted to an analog signal by
calibration DAC and is fed to the main DAC by CCAL to compensate the capacitor
mismatching error.
Allen and Holberg - CMOS Analog Circuit Design Page X.8-23
Supply voltage ± 5V
Resolution of 16 bits
Linearity of 16 bits
12 µs for 12 Bits
80 µs for 16 Bits.
• Flash or parallel
• Time interleaving
R
7 VREF +
8 1
R -
6 VREF + 1
8
R -
5 VREF +
8 0
Output
R - Digital digital
4 VREF decoding word
+ 0
8 network 101
R -
3 VREF + 0
8
R -
2 VREF + 0
8
R -
1 VREF + 0
8
R -
T1
T2
TM
t
T1 T2 TM T1 + TC T2 + TC TM + TC
Allen and Holberg - CMOS Analog Circuit Design Page X.9-4
320
160
FLASH
80 5
Relative die size
Succ. Approx.
4 Array
40 (m- WAY)
3 m
20
10
4 5 6 7 8 9
# of bits
Allen and Holberg - CMOS Analog Circuit Design Page X.9-5
• 8-bit, 1M Hz.
Gain = 2M
+
V*in ∑ V*in
-
Vref Vref
+ +
- -
+ +
- -
+ Digital + Digital
decoding decoding
- network - network
+ +
- -
D/A
Converter
M MSB's M LSB's
2M - 1 2M - 1
equal equal
resistors resistors
and and
comparators comparators
Allen and Holberg - CMOS Analog Circuit Design Page X.9-6
Use XOR gates to connect to the appropriate point in the resistor divider resulting in the
Vref
Analog V*in
Out
+ 1
-
0
+ 1
-
1
+ 0
-
0
+ 0
-
0
Allen and Holberg - CMOS Analog Circuit Design Page X.10-1
Digital y(kTN)
x(t) Processor
The anti-aliasing filter at the input stage limits the bandwidth of the input signal and
prevents the possible aliasing of the following sampling step. The modulator pushes the
quantization noise to the higher frequency and leaves only a small fraction of noise energy
in the signal band. A digital low pass filter cuts off the high frequency quantization noise.
Therefore, the signal to noise ratio is increased.
Allen and Holberg - CMOS Analog Circuit Design Page X.10-2
ANTI-ALIASING FILTER
The anti-aliasing filter of an oversampling ADC requires less effort than that of a
conventional ADC. The frequency response of the anti-aliasing filter for the conventional
ADC is sharper than the oversampling ADC.
Conventional ADC's Anti-Aliasing Filter
fB
f
fN/2 fS=fN
fB
f
fN/2 fN fS/2 fS
fB : Signal Bandwidth
fN : Nyquist Frequency, fN = 2fB
fS : Sampling Frequency and usually fS >> fN
fS
M : Oversampling ratio, M = f
N
So the analog anti-aliasing filter of an oversampling ADC is less expensive than the
conventional ADC. If M is sufficiently large, the analog anti-aliasing filter is simply an RC
filter.
Allen and Holberg - CMOS Analog Circuit Design Page X.10-3
QUANTIZATION
Conventional ADC's Quantization
3
ideal curve
1
-6 -4 -2
input (x)
2 4 6
-1
y=Gx+e
-3
-5
e
1
x
-1
Therefore, each doubling of the sampling frequency decreases the in-band noise
energy by 3 dB, and increases the resolution by 0.5 bit. This is not a very efficient method
of reducing the inband noise.
Allen and Holberg - CMOS Analog Circuit Design Page X.10-5
OVERSAMPLING ADC
fS fD
∑∆ LOW-PASS 2fB
analog fB DECIMATOR
input MODULATOR FILTER digital
PCM
∑∆ modulator
Also called the noise shaper because it can shape the quantization noise and push
majority of the noise to high frequency band. It modulates the analog input signal to a
simple digital code, normally is one bit, using a sampling rate much higher the Nyquist
rate.
Decimator
Also called the down-sampler because it down samples the high frequency
modulator output into a low frequency output.
Low-pass filter
Use digital low pass filter to cut off the high frequency quantization noise and
preserve the input signal.
Allen and Holberg - CMOS Analog Circuit Design Page X.10-6
+
x(t) + Integrator A/D yi
-
D/A
Modulator Output
input signal
modulator
Amplitude (V)
output
0 0.5 1
Time (ms)
Allen and Holberg - CMOS Analog Circuit Design Page X.10-7
First-Order ∑∆ Modulator
+ gn wn+1 wn
xn Delay yn
-
en
Quantizer
Accumulator
yn = wn + en
(1)
wn+1 = gn + wn = xn - yn + wn
= xn -(wn + en) + wn = xn - en
(2)
Therefore, wn = xn-1 - en-1, which when substituted into (1) gives
yn = xn-1 + ( en - en-1)
The output of ∑∆ modulator yn is the input signal delayed by one clock cycle xn-1,
plus the quantization noise difference en - en-1. The modulation noise spectrum density of
en - en-1 is
ωτ ωτ
N(f) = E(f) 1 - z-1 = E(f) 1 - e-jωτ = 2E(f) sin 2 = 2e rms 2τ sin 2
Plot of Noise Spectrum
2
signal baseband
N(f)
1.5
N(f)/E(f)
1 E(f)
0.5
0
0 fB fS
Frequency 2
Allen and Holberg - CMOS Analog Circuit Design Page X.10-8
Each doubling of the oversampling ratio reduces the modulation noise by 9 dB and
increase the resolution by 1.5 bits.
Allen and Holberg - CMOS Analog Circuit Design Page X.10-9
ωτ 2 ωτ
|N(f)| = E(f) 1 - e-jωτ = 2E(f) sin 2 = 2 erms sin 2
fS
The noise power is found as
fB
fB
⌠ 2 2πfτ
no(f) = ⌠
2 ⌡|N(f)|2 df = 2 2
erms sin2 2 df
0 ⌡ fS
0
2πfτ
Let sin 2 ≈ πfτ if fS >> fB. Therefore,
fB
2 2 2 8π2 2 fB 3
no(f) = 4 f erms (πτ)2 ⌠ ⌡f2 df =
S 3 erms fS
0
or
3/2
8 fB VREF
no(f) = π·erms f ≤ 10
3 S 2
Solving for fB/fS gives (using ∆ in erms term is equal to VREF)
fB 12 3 1 2/3
= [0.659x10-3]2/3 = 0.007576
fS 8 π 210
=
fB = 0.007576·10MHz = 75.76kHz.
Allen and Holberg - CMOS Analog Circuit Design Page X.10-10
Decimator (down-sampling)
The one-bit output from the ∑∆ modulator is at very high frequency, so we need a
decimator (or down sampler) to reduce the frequency before going to the digital filter.
fS fD
∑∆ LOW-PASS 2fB
analog fB DECIMATOR
input MODULATOR FILTER digital
PCM
Removes the Removes the
modulation noise out-of-band
components
of the signal
REGISTER
fS
1 N fS
yn = N ∑ xn , where N = = down-sampling ratio
fD
N=0
The transfer function of decimator is
N-1
1 1 - z-N
H(z) = X(z) = N ∑ z-i = N
Y(z) 1
1 - z-1
i=0
sinc(πfNτ)
H(ejωτ) =
sinc(πfτ)
Allen and Holberg - CMOS Analog Circuit Design Page X.10-11
sinc(πfNτ)
H(ejωτ) =
sinc(πfτ)
10
0 Quantization Noise
Signal
Bandwidth
-10
Magnitude (dB)
-20
-30
-40
-50
fD fS
Frequency
2
fD = intermediate decimation frequency
When the modulation noise is sampled at fD, its components in the vicinity of fD
and the harmonics of fD fold into the signal band. Therefore, the zeros of the decimation
filter must be placed at these frequencies.
Allen and Holberg - CMOS Analog Circuit Design Page X.10-12
∑∆ LOW-PASS 2fB
analog fB DECIMATOR
input MODULATOR FILTER digital
PCM
10
-20
Magnitude (dB)
-50
-80
signal
-50
Magnitude (dB)
-150
Bit resolution
From the frequency response of above diagram, the signal-to-noise ratio (SNR)
signal
SNR = 10log 10 f (dB)
B
∑ noise(f)
f=0
and
SNR(db)
Bit resolution (B) ≈ 6dB
Allen and Holberg - CMOS Analog Circuit Design Page X.10-14
digital
PCM
2fB
Frequency
LOW-PASS
FILTER
fD
DECIMATOR
Frequency
Time
fS
MODULATOR
∑∆ analog fB
input
Time
Frequency
Allen and Holberg - CMOS Analog Circuit Design Page X.10-15
Second-Order ∑∆ Modulator
D/A
QUANTIZER
yn = xn-1 + (en - 2en-1 + en-2)
The output of a second order ∑∆ modualtor yn is the input signal delayed by one
clock cycle xn-1, plus the quantization noise difference en - 2en-1 + en-2. The modulation
noise spectrum density of en - 2en-1 + en-2 is
2 2 ωτ
N(f) = E(f) 1 - z-1 = E(f) 1 - e-jωτ = 4E(f) sin2 2
Noise Spectrum
4
signal baseband
E(f)
1
0 fS
0 fB Frequency
2
Allen and Holberg - CMOS Analog Circuit Design Page X.10-16
Each doubling of the oversampling ratio reduces the modulation noise by 15 dB and
increase the resolution by 2.5 bits.
This noise falls 3(2L+1) dB for every doubling of the sampling rate providing L+0.5 extra
bits.
Decimation Filter
sinc(πfNτ) L+1
A filter function of is close to being optimum for decimating the
sinc(πfτ)
signal from an Lth-order ∆−Σ modulator.
Stability
For orders greater than 2, the loop can become unstable. Loop configuration must
be used that provide stability for order greater than two.
Allen and Holberg - CMOS Analog Circuit Design Page X.10-17
4∆ 2 ωt
|N(f)| = sin2 4
12 fs
where ∆ is the signal level out of the 1-bit quantizer and fs = (1/τ) = the
sampling frequency and is 10MHz. Find the signal bandwidth, fB, in Hz if
the modulator is to be used in an 18 bit oversampled ADC. Be sure to state
any assumption you use in working this problem.
Allen and Holberg - CMOS Analog Circuit Design Page X.10-18
C2 C2
S2 S3 S2 S3
C1 C1
S1 S4 S1 S4
- + - +
IN OUT
+ - + -
S1 S4 S1 S4
C1 C1
S2 S3 S2 S3
C2 C2
V-REF
V+REF
Fully differential, switched-capacitor integrators can reduce charge injection effect.
2. Linear Errors
3. Nonlinear Errors
Harmonic distortion
Thermal noise
Allen and Holberg - CMOS Analog Circuit Design Page X.10-20
kT/C Noise
1
T = f ≈ 10RC (1)
c
V ref
Set the value of the LSB = equal to kT/C noise of the switch,
2N
Vref kT
= (2)
2N C
2
Vref Vref
N = 10kTRfc ⇒ 2N f c = (3)
2 10kRT
or
kT/C Noise
Comparison of high-performance, monolithic A/D converters in terms
of resolution versus sampling frequency with fundamental limits due to
kT/C noise superimposed.
Allen and Holberg - CMOS Analog Circuit Design Page X.11-2
vo(t) e-ζGBt
= 1 - sin 1-ζ 2 GB·t + φ
A(0) 1-ζ 2
1.5
+ε
1
-ε
0.5 Settling
Time
0
0 4 8 12 16 20
ωn t
If we define the error (±ε) in vo settling to A(0) as the multiplier of the
sinusoid, then an expression for the settling time can be derived as
1 e-ζGBt 1 2πζGB
ts = 2πζGB ln ⇒ fsample = =
1 - ζ2 ts
ln
1
ε 1-ζ2
vin
Clock
Analog-to- ∆V
Analog digital Digital
In converter Out Slope = dvin
dt
t
∆T
dvin
∆V = slope x ∆T = dt ∆T
∆V Vref/2N
∆T = Aperature uncertainty = dV = dv /dt
in in
dt
Assume that vin(t) = Vp sin ωt
dvin
dt = ωV p
max
Vref 1 Vref 1
∆T = x ≈ =
2N ωV p 2NωVref 2 N ω
1 1
Therefore, ∆T = =
2πf2N πf2N+1
1
Suppose f = 100kHz and N = 8, ∆T = = 6.22ns
200πKx29
6.22ns 622ppm
Clock accuracy = 10,000ns = 0.06% = ?
Allen and Holberg - CMOS Analog Circuit Design Page X.12-1
Conclusions
• The best A/D converter depends upon the application
• Both resolution and speed are ultimately limited by the accuracy of the
process
• High resolution A/D's will be more oriented toward "signal averaging"
type converters, particularly with shorter channel lengths