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ch04 PDF
ch04 PDF
Jin-Fu Li
Department of Electrical Engineering
National Central University
Jungli, Taiwan
Outline
¾ Registers, Memory Access, and Data Transfer
¾ Arithmetic and Logic Instructions
¾ Branch Instructions
¾ Assembly Language
¾ I/O Operations
¾ Subroutines
¾ Program Examples
Address Data/Instruction
Control Unit
Input/Output System
R14
31 0
R15 (PC) Program counter
31 30 29 28 7 6 4 0
CPSR … Status register
N-Negative
Z-Zero
C-Carry Processor mode bits
V-Overflow Interrupt disable bits
Conditional code flags
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
Register Structure
¾ The use of processor mode bits and interrupt disable bits
will be described in conjunction with input/output
operations and interrupts in Chapter 5
¾ There are 15 additional general-purpose registers called
the banked registers
They are duplicates of some of the R0 to R14 registers
They are used when the processor switches into Supervisor or
Interrupt modes of operation
¾ Saved copies of the Status register are also available in the
Supervisor and Interrupt modes
¾ The banked registers and Status register copies will also
be discussed in Chapter 5
With offset in Rn
Pre-indexed [Rn, +Rm, shift] EA=[Rn]+[Rm] shifted
Pre-indexed with writeback [Rn, +Rm, shift]! EA=[Rn]+[Rm] shifted;
RnÅ[Rn]+[Rm] shifted
Post-indexed [Rn], +Rm, shift EA=[Rn];
RnÅ[Rn]+[Rm] shifted
Relative (Pre-indexed with Location EA=Location=[PC]+offset
Immediate offset)
shift=direction #integer, where direction is LSL for left shift or LSR for right shift, and integer
is a 5-bit unsigned number specifying the shift format
+ Rm=the offset magnitude in register Rm can be added to or subtracted from the contents
of based register Rn
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
Relative Addressing Mode
Memory
address word (4 bytes)
52=offset
ITEM=1060 Operand
The operand must be within the range of 4095 bytes forward or backward from the
updated PC.
1000 R5
Based register
STR R3, [R5,R6]
200 R6
Offset register
1000
200=offset
1200 Operand
1000 R2
Based register
1000 6
25 R10
100=25x4
Offset register
1100 -17
100=25x4
Load instruction:
1200 321 LDR R1, [R2], R10, LSL, #2
2012 R5
Based register (stack pointer)
27 R0
2008 27
2012 - TOS (top-of-stack)
After execution of
Push instruction
Push instruction:
STR R0, [R5,# -4]!
31 28 27 24 23 0
Offset=92
Assume that the memory location N, POINTER, and SUM are within the range
Reachable by the offset relative to the PC
GT: signed greater than
BGT: Branch if Z=0 and N=0
0 1 n-2 n-1
…
k j