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TinySwitch-III Family
®
Product Highlights + +
Lowest System Cost with Enhanced Flexibility DC
Output
• Simple ON/OFF control, no loop compensation needed
-
• Selectable current limit through BP/M capacitor value
Wide-Range
- Higher current limit extends peak power or, in open HV DC Input
D
EN/UV
frame applications, maximum continuous power BP/M
TinySwitch-III
- Lower current limit improves efficiency in enclosed S
adapters/chargers
-
- Allows optimum TinySwitch-III choice by swapping PI-4095-082205
devices with no other circuit redesign
• Tight I2f parameter tolerance reduces system cost Figure 1. Typical Standby Application.
- Maximizes MOSFET and magnetics power delivery
- Minimizes max overload power, reducing cost of
transformer, primary clamp & secondary components OUTPUT POWER TABLE
• ON-time extension – extends low line regulation range/ 230 VAC ±15% 85-265 VAC
hold-up time to reduce input bulk capacitance Peak or Peak or
• Self-biased: no bias winding or bias components PRODUCT3
Adapter1 Open Adapter1 Open
• Frequency jittering reduces EMI filter costs Frame2 Frame2
• Pin-out simplifies heatsinking to the PCB
• SOURCE pins are electrically quiet for low EMI TNY274 P or G 6W 11 W 5W 8.5 W
TNY275 P or G 8.5 W 15 W 6W 11.5 W
Enhanced Safety and Reliability Features TNY276 P or G 10 W 19 W 7W 15 W
• Accurate hysteretic thermal shutdown protection with
automatic recovery eliminates need for manual reset TNY277 P or G 13 W 23.5 W 8W 18 W
• Improved auto-restart delivers <3% of maximum power TNY278 P or G 16 W 28 W 10 W 21.5 W
in short circuit and open loop fault conditions TNY279 P or G 18 W 32 W 12 W 25 W
• Output overvoltage shutdown with optional Zener TNY280 P or G 20 W 36.5 W 14 W 28.5 W
• Line under-voltage detect threshold set using a single
optional resistor Table 1. Notes: 1. Minimum continuous power in a typical non-
• Very low component count enhances reliability and ventilated enclosed adapter measured at 50 °C ambient. Use of an
external heatsink will increase power capability 2. Minimum peak
enables single-sided printed circuit board layout power capability in any design or minimum continuous power in an
• High bandwidth provides fast turn on with no overshoot open frame design (see Key Application Considerations). 3. Packages:
and excellent transient load response P: DIP-8C, G: SMD-8C. See Part Ordering Information.
• Extended creepage between DRAIN and all other pins
improves field reliability
®
EcoSmart – Extremely Energy Efficient • PC Standby and other auxiliary supplies
• Easily meets all global energy efficiency regulations • DVD/PVR and other low power set top decoders
• No-load <150 mW at 265 VAC without bias winding, • Supplies for appliances, industrial systems, metering, etc.
<50 mW with bias winding
• ON/OFF control provides constant efficiency down to Description
very light loads – ideal for mandatory CEC regulations
and 1 W PC standby requirements TinySwitch-III incorporates a 700 V power MOSFET, oscillator,
high voltage switched current source, current limit (user
Applications selectable) and thermal shutdown circuitry. The IC family uses
• Chargers/adapters for cell/cordless phones, PDAs, digital an ON/OFF control scheme and offers a design flexible solution
cameras, MP3/portable audio, shavers, etc. with a low system cost and extended power capability.
February 2006
TNY274-280
BYPASS/
MULTI-FUNCTION DRAIN
(BP/M) (D)
REGULATOR
5.85 V
LINE UNDER-VOLTAGE
115 µA 25 µA
FAULT BYPASS PIN
PRESENT + UNDER-VOLTAGE
AUTO-
RESTART -
COUNTER 5.85 V VI
CURRENT
4.9 V LIMIT
LIMIT STATE
6.4 V RESET
MACHINE
CURRENT LIMIT
COMPARATOR
ENABLE -
JITTER
CLOCK
1.0 V + VT
DCMAX THERMAL
SHUTDOWN
OSCILLATOR
ENABLE/
1.0 V
UNDER-
S Q
VOLTAGE
(EN/UV)
R Q
LEADING
EDGE
BLANKING
SOURCE
(S)
PI-4077-013106
2 E
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TNY274-280
MOSFET is controlled by this pin. MOSFET switching is maximum duty cycle signal (DCMAX) and the clock signal that
terminated when a current greater than a threshold current is indicates the beginning of each cycle.
drawn from this pin. Switching resumes when the current being
pulled from the pin drops to less than a threshold current. A The oscillator incorporates circuitry that introduces a small
modulation of the threshold current reduces group pulsing. The amount of frequency jitter, typically 8 kHz peak-to-peak, to
threshold current is between 60 µA and 115 µA. minimize EMI emission. The modulation rate of the frequency
jitter is set to 1 kHz to optimize EMI reduction for both average
The EN/UV pin also senses line under-voltage conditions through and quasi-peak emissions. The frequency jitter should be
an external resistor connected to the DC line voltage. If there is measured with the oscilloscope triggered at the falling edge of
no external resistor connected to this pin, TinySwitch-III detects the DRAIN waveform. The waveform in Figure 4 illustrates
its absence and disables the line under-voltage function. the frequency jitter.
SOURCE (S) Pin: Enable Input and Current Limit State Machine
This pin is internally connected to the output MOSFET source The enable input circuit at the EN/UV pin consists of a low
for high voltage power return and control circuit common. impedance source follower output set at 1.2 V. The current
through the source follower is limited to 115 µA. When the
TinySwitch-III Functional current out of this pin exceeds the threshold current, a low
logic level (disable) is generated at the output of the enable
Description circuit, until the current out of this pin is reduced to less than
TinySwitch-III combines a high voltage power MOSFET switch the threshold current. This enable circuit output is sampled
with a power supply controller in one device. Unlike conventional at the beginning of each cycle on the rising edge of the clock
PWM (pulse width modulator) controllers, it uses a simple signal. If high, the power MOSFET is turned on for that cycle
ON/OFF control to regulate the output voltage. (enabled). If low, the power MOSFET remains off (disabled).
Since the sampling is done only at the beginning of each cycle,
The controller consists of an oscillator, enable circuit (sense and subsequent changes in the EN/UV pin voltage or current during
logic), current limit state machine, 5.85 V regulator, BYPASS/ the remainder of the cycle are ignored.
MULTI-FUNCTION pin under-voltage, overvoltage circuit, and
current limit selection circuitry, over- temperature protection, The current limit state machine reduces the current limit by
current limit circuit, leading edge blanking, and a 700 V power discrete amounts at light loads when TinySwitch-III is likely to
MOSFET. TinySwitch-III incorporates additional circuitry for switch in the audible frequency range. The lower current limit
line under-voltage sense, auto-restart, adaptive switching cycle raises the effective switching frequency above the audio range
on-time extension, and frequency jitter. Figure 2 shows the and reduces the transformer flux density, including the associated
functional block diagram with the most important features. audible noise. The state machine monitors the sequence of
enable events to determine the load condition and adjusts the
Oscillator current limit level accordingly in discrete amounts.
The typical oscillator frequency is internally set to an average
of 132 kHz. Two signals are generated from the oscillator: the Under most operating conditions (except when close to no-load),
the low impedance of the source follower keeps the voltage on
600 the EN/UV pin from going much below 1.2 V in the disabled
PI-2741-041901
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TNY274-280
4 E
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TNY274-280
load is proportional to the primary inductance of the transformer not to proceed with the next switching cycle. The sequence of
and peak primary current squared. Hence, designing the supply cycles is used to determine the current limit. Once a cycle is
involves calculating the primary inductance of the transformer started, it always completes the cycle (even when the EN/UV
for the maximum output power required. If the TinySwitch-III pin changes state half way through the cycle). This operation
is appropriately chosen for the power level, the current in the results in a power supply in which the output voltage ripple
calculated inductance will ramp up to current limit before the is determined by the output capacitor, amount of energy per
DCMAX limit is reached. switch cycle and the delay of the feedback.
V V
EN EN
CLOCK CLOCK
DC DC
MAX MAX
I DRAIN I DRAIN
V DRAIN
V DRAIN
PI-2667-082305 PI-2377-082305
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TNY274-280
200
PI-2381-1030801
V V
EN 100
DC-INPUT
0
CLOCK
10
DC
MAX V
5 BYPASS
I DRAIN 400
200 V
DRAIN
0
0 1 2
Time (ms)
V DRAIN Figure 11. Power-Up Without Optional External UV Resistor
Connected to EN/UV Pin.
PI-2348-030801
PI-2661-082305
0
The response time of the ON/OFF control scheme is very fast 0 .5 1
compared to PWM control. This provides tight regulation and Time (s)
excellent transient response.
Figure 12. Normal Power-Down Timing (without UV).
200
PI-2383-030801
PI-2395-030801
100 V
DC-INPUT 200
V
0 100 DC-INPUT
10 0
V
5 BYPASS 400
0 300
400 200 V
DRAIN
200 V 100
DRAIN
0 0
0 1 2 0 2.5 5
Time (ms) Time (s)
Figure 10. Power-Up with Optional External UV Resistor (4 MΩ) Figure 13. Slow Power-Down Timing with Optional External
Connected to EN/UV Pin. (4 MΩ) UV Resistor Connected to EN/UV Pin.
6 E
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TNY274-280
Power Up/Down Functional Description above). This has two main benefits.
The TinySwitch-III requires only a 0.1 µF capacitor on the First, for a nominal application, this eliminates the cost of a
BYPASS/MULTI-FUNCTION pin to operate with standard bias winding and associated components. Secondly, for battery
current limit. Because of its small size, the time to charge this charger applications, the current-voltage characteristic often
capacitor is kept to an absolute minimum, typically 0.6 ms. The allows the output voltage to fall close to zero volts while still
time to charge will vary in proportion to the BYPASS/MULTI- delivering power. TinySwitch-III accomplishes this without a
FUNCTION pin capacitor value when selecting different current forward bias winding and its many associated components. For
limits. Due to the high bandwidth of the ON/OFF feedback, applications that require very low no-load power consumption
there is no overshoot at the power supply output. When an (50 mW), a resistor from a bias winding to the BYPASS/
external resistor (4 MΩ) is connected from the positive DC MULTI-FUNCTION pin can provide the power to the chip.
input to the EN/UV pin, the power MOSFET switching will The minimum recommended current supplied is 1 mA. The
be delayed during power-up until the DC line voltage exceeds BYPASS/MULTI-FUNCTION pin in this case will be clamped
the threshold (100 V). Figures 10 and 11 show the power-up at 6.4 V. This method will eliminate the power draw from the
timing waveform in applications with and without an external DRAIN pin, thereby reducing the no-load power consumption
resistor (4 MΩ) connected to the EN/UV pin. and improving full-load efficiency.
Under startup and overload conditions, when the conduction time Current Limit Operation
is less than 400 ns, the device reduces the switching frequency Each switching cycle is terminated when the DRAIN current
to maintain control of the peak drain current. reaches the current limit of the device. Current limit operation
provides good line ripple rejection and relatively constant power
During power-down, when an external resistor is used, the delivery independent of input voltage.
power MOSFET will switch for 64 ms after the output loses
regulation. The power MOSFET will then remain off without BYPASS/MULTI-FUNCTION Pin Capacitor
any glitches since the under-voltage function prohibits restart The BYPASS/MULTI-FUNCTION pin can use a ceramic
when the line voltage is low. capacitor as small as 0.1 µF for decoupling the internal power
supply of the device. A larger capacitor size can be used to adjust
Figure 12 illustrates a typical power-down timing waveform. the current limit. For TNY275-280, a 1 µF BP/M pin capacitor
Figure 13 illustrates a very slow power-down timing waveform will select a lower current limit equal to the standard current
as in standby applications. The external resistor (4 MΩ) is limit of the next smaller device and a 10 µF BP/M pin capacitor
connected to the EN/UV pin in this case to prevent unwanted will select a higher current limit equal to the standard current
restarts. limit of the next larger device. The higher current limit level of
the TNY280 is set to 850 mA typical. The TNY274 MOSFET
No bias winding is needed to provide power to the chip does not have the capability for increased current limit so this
because it draws the power directly from the DRAIN pin (see feature is not available in this device.
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TNY274-280
C5
2.2 nF
250 VAC
L2
D7 Ferrite Bead
VR1 BYV28-200
P6KE150A T1 3.5 × 7.6 mm +12 V, 1 A
NC 8
C10 C11 J3
D1 D2 R2 1000 µF 100 µF
1N4007 1N4007 100 Ω 1 6 25 V 25 V J4
F1
J1 3.15 A C4 RTN
C1 C2 R1
6.8 µF 22 µF 1 kΩ 10 nF
1 kV 3 R7
400 V 400 V
85-265 RV1 4 20 Ω
VAC 275 VAC
D5
1N4007GP 2 D6
R5* UF4003
J2 3.6 MΩ
D3 D4 5
1N4007 1N4007
L1 VR2
1 mH 1N5255B C6 VR3
28 V 1 µF BZX79-C11
60 V 11 V
R3
47 Ω
*R5 and R8 are optional 1/8 W R6
components 390 Ω
R8* 1/8 W
† 21 kΩ
C7 is configurable to adjust 1% U2
D PC817A
U1 current limit, see circuit EN/UV
description
BP/M
S
S R4
TinySwitch-III C7 † 2 kΩ
U1 100 nF 1/8 W
TNY278P 50 V
PI-4244-021406
Applications Example LED forward drop, current will flow in the optocoupler LED.
This will cause the transistor of the optocoupler to sink current.
The circuit shown in Figure 14 is a low cost, high efficiency, When this current exceeds the ENABLE pin threshold current
flyback power supply designed for 12 V, 1 A output from the next switching cycle is inhibited. When the output voltage
universal input using the TNY278. falls below the feedback threshold, a conduction cycle is allowed
to occur and, by adjusting the number of enabled cycles, output
The supply features under-voltage lockout, primary sensed regulation is maintained. As the load reduces, the number of
output overvoltage latching shutdown protection, high enabled cycles decreases, lowering the effective switching
efficiency (>80%), and very low no-load consumption frequency and scaling switching losses with load. This provides
(<50 mW at 265 VAC). Output regulation is accomplished using almost constant efficiency down to very light loads, ideal for
a simple zener reference and optocoupler feedback. meeting energy efficiency requirements.
The rectified and filtered input voltage is applied to the primary As the TinySwitch-III devices are completely self-powered,
winding of T1. The other side of the transformer primary is there is no requirement for an auxiliary or bias winding on the
driven by the integrated MOSFET in U1. Diode D5, C2, R1, transformer. However by adding a bias winding, the output
R2, and VR1 comprise the clamp circuit, limiting the leakage overvoltage protection feature can be configured, protecting
inductance turn-off voltage spike on the DRAIN pin to a safe the load against open feedback loop faults.
value. The use of a combination a Zener clamp and parallel
RC optimizes both EMI and energy efficiency. Resistor R2 When an overvoltage condition occurs, such that bias voltage
allows the use of a slow recovery, low cost, rectifier diode by exceeds the sum of VR2 and the BYPASS/MULTIFUNCTION
limiting the reverse current through D5. The selection of a (BP/M) pin voltage (28 V+5.85 V), current begins to flow into the
slow diode also improves efficiency and conducted EMI but BP/M pin. When this current exceeds 5 mA the internal latching
should be a glass passivated type, with a specified recovery shutdown circuit in TinySwitch-III is activated. This condition
time of ≤2 µs. is reset when the BP/M pin voltage drops below 2.6 V after
removal of the AC input. In the example shown, on opening
The output voltage is regulated by the Zener diode VR3. When the loop, the OVP trips at an output of 17 V.
the output voltage exceeds the sum of the Zener and optocoupler
8 E
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TNY274-280
For lower no-load input power consumption, the bias winding Key Application Considerations
may also be used to supply the TinySwitch-III device. Resistor
R8 feeds current into the BP/M pin, inhibiting the internal high TinySwitch-lll Design Considerations
voltage current source that normally maintains the BP/M pin
capacitor voltage (C7) during the internal MOSFET off time. Output Power Table
This reduces the no-load consumption of this design from The data sheet output power table (Table 1) represents the
140 mW to 40 mW at 265 VAC. minimum practical continuous output power level that can be
obtained under the following assumed conditions:
Under-voltage lockout is configured by R5 connected between
the DC bus and EN/UV pin of U1. When present, switching 1. The minimum DC input voltage is 100 V or higher for
is inhibited until the current in the EN/UV pin exceeds 25 µA. 85 VAC input, or 220 V or higher for 230 VAC input or
This allows the startup voltage to be programmed within the 115 VAC with a voltage doubler. The value of the input
normal operating input voltage range, preventing glitching of capacitance should be sized to meet these criteria for AC
the output under abnormal low voltage conditions and also on input designs.
removal of the AC input. 2. Efficiency of 75%.
3. Minimum data sheet value of I2f.
In addition to the simple input pi filter (C1, L1, C2) for 4. Transformer primary inductance tolerance of ±10%.
differential mode EMI, this design makes use of E-Shield™ 5. Reflected output voltage (VOR) of 135 V.
shielding techniques in the transformer to reduce common 6. Voltage only output of 12 V with a fast PN rectifier diode.
mode EMI displacement currents, and R2 and C4 as a damping 7. Continuous conduction mode operation with transient KP*
network to reduce high frequency transformer ringing. These value of 0.25.
techniques, combined with the frequency jitter of TNY278, 8. Increased current limit is selected for peak and open frame
give excellent conducted and radiated EMI performance with power columns and standard current limit for adapter
this design achieving >12 dBµV of margin to EN55022 Class columns.
B conducted EMI limits. 9. The part is board mounted with SOURCE pins soldered to
a sufficient area of copper and/or a heatsink is used to keep
For design flexibility the value of C7 can be selected to pick one the SOURCE pin temperature at or below 110 °C.
of the 3 current limits options in U1. This allows the designer 10. Ambient temperature of 50 °C for open frame designs and
to select the current limit appropriate for the application. 40 °C for sealed adapters.
• Standard current limit (ILIMIT) is selected with a 0.1 µF BP/M *Below a value of 1, KP is the ratio of ripple to peak primary
pin capacitor and is the normal choice for typical enclosed current. To prevent reduced power capability due to premature
adapter applications. termination of switching cycles a transient KP limit of ≥0.25
• When a 1 µF BP/M pin capacitor is used, the current is recommended. This prevents the initial current limit (IINIT)
limit is reduced (ILIMITred or ILIMIT-1) offering reduced RMS from being exceeded at MOSFET turn on.
device currents and therefore improved efficiency, but at
the expense of maximum power capability. This is ideal For reference, Table 2 provides the minimum practical power
for thermally challenging designs where dissipation must delivered from each family member at the three selectable current
be minimized. limit values. This assumes open frame operation (not thermally
• When a 10 µF BP/M pin capacitor is used, the current limited) and otherwise the same conditions as listed above.
limit is increased (ILIMITinc or ILIMIT+1), extending the power These numbers are useful to identify the correct current limit
capability for applications requiring higher peak power or to select for a given device and output power requirement.
continuous power where the thermal conditions allow.
Overvoltage Protection
Further flexibility comes from the current limits between adjacent The output overvoltage protection provided by TinySwitch-III
TinySwitch-III family members being compatible. The reduced uses an internal latch that is triggered by a threshold current
current limit of a given device is equal to the standard current of approximately 5.5 mA into the BP/M pin. In addition to an
limit of the next smaller device and the increased current limit is internal filter, the BP/M pin capacitor forms an external filter
equal to the standard current limit of the next larger device. providing noise immunity from inadvertent triggering. For the
bypass capacitor to be effective as a high frequency filter, the
capacitor should be located as close as possible to the SOURCE
and BP/M pins of the device.
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TNY274-280
For best performance of the OVP function, it is recommended practically eliminates audible noise. Vacuum impregnation
that a relatively high bias winding voltage is used, in the range of of the transformer should not be used due to the high primary
15 V-30 V. This minimizes the error voltage on the bias winding capacitance and increased losses that result. Higher flux densities
due to leakage inductance and also ensures adequate voltage are possible, however careful evaluation of the audible noise
during no-load operation from which to supply the BP/M pin performance should be made using production transformer
for reduced no-load consumption. samples before approving the design.
Selecting the Zener diode voltage to be approximately 6 V Ceramic capacitors that use dielectrics such as Z5U, when used
above the bias winding voltage (28 V for 22 V bias winding) in clamp circuits, may also generate audio noise. If this is the
gives good OVP performance for most designs, but can be case, try replacing them with a capacitor having a different
adjusted to compensate for variations in leakage inductance. dielectric or construction, for example a film type.
Adding additional filtering can be achieved by inserting a low
value (10 Ω to 47 Ω) resistor in series with the bias winding TinySwitch-lll Layout Considerations
diode and/or the OVP Zener as shown by R7 and R3 in
Figure 14. The resistor in series with the OVP Zener also limits Layout
the maximum current into the BP/M pin. See Figure 15 for a recommended circuit board layout for
TinySwitch-III.
Reducing No-load Consumption
As TinySwitch-III is self-powered from the BP/M pin capacitor, Single Point Grounding
there is no need for an auxillary or bias winding to be provided Use a single point ground connection from the input filter capacitor
on the transformer for this purpose. Typical no-load consumption to the area of copper connected to the SOURCE pins.
when self-powered is <150 mW at 265 VAC input. The addition
of a bias winding can reduce this down to <50 mW by supplying Bypass Capacitor (CBP)
the TinySwitch-III from the lower bias voltage and inhibiting the The BP/M pin capacitor should be located as near as possible
internal high voltage current source. To achieve this, select the to the BP/M and SOURCE pins.
value of the resistor (R8 in Figure 14) to provide the data sheet
DRAIN supply current. In practice, due to the reduction of the Primary Loop Area
bias voltage at low load, start with a value equal to 40% greater The area of the primary loop that connects the input filter
than the data sheet maximum current, and then increase the value capacitor, transformer primary and TinySwitch-III together
of the resistor to give the lowest no-load consumption. should be kept as small as possible.
10 E
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TNY274-280
Y1-
Capacitor
+
HV DC
INPUT
-
T
r
a
n
s
f Output Filter
S S S S o Capacitor
CBP r
m
e
TinySwitch-III r
EN/UV BP/M D
Opto-
coupler
- DC +
OUT
Maximize hatched copper
areas ( ) for optimum
heatsinking
PI-4278-013006
Figure 15. Recommended Circuit Board Layout for TinySwitch-III with Under-Voltage Lock Out Resistor.
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TNY274-280
Quick Design Checklist startup. Repeat under steady state conditions and verify that
the leading edge current spike event is below ILIMIT(Min) at the
As with any power supply design, all TinySwitch-III designs end of the tLEB(Min). Under all conditions, the maximum drain
should be verified on the bench to make sure that component current should be below the specified absolute maximum
specifications are not exceeded under worst case conditions. The ratings.
following minimum set of tests is strongly recommended: 3. Thermal Check – At specified maximum output power,
minimum input voltage and maximum ambient temperature,
1. Maximum drain voltage – Verify that VDS does not exceed verify that the temperature specifications are not exceeded
650 V at highest input voltage and peak (overload) output for TinySwitch-III, transformer, output diode, and output
power. The 50 V margin to the 700 V BVDSS specification capacitors. Enough thermal margin should be allowed for
gives margin for design variation. part-to-part variation of the RDS(ON) of TinySwitch-III as
2. Maximum drain current – At maximum ambient temperature, specified in the data sheet. Under low line, maximum power,
maximum input voltage and peak output (overload) power, a maximum TinySwitch-III SOURCE pin temperature of
verify drain current waveforms for any signs of transformer 110 °C is recommended to allow for these variations.
saturation and excessive leading edge current spikes at
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TNY274-280
THERMAL IMPEDANCE
Notes:
Thermal Impedance: P or G Package:
1. Measured on the SOURCE pin close to plastic interface.
(θJA) ........................... 70 °C/W(2); 60 °C/W(3)
2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
(θJC)(1) ............................................... 11 °C/W
3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol Min Typ Max Units
See Figure 16
(Unless Otherwise Specified)
CONTROL FUNCTIONS
Output Frequency TJ = 25 °C Average 124 132 140
fOSC kHz
in Standard Mode See Figure 4 Peak-Peak Jitter 8
Maximum Duty
DCMAX S1 Open 62 65 %
Cycle
EN/UV Pin Upper
Turnoff Threshold IDIS -150 -115 -90 µA
Current
EN/UV Pin IEN/UV = 25 µA 1.8 2.2 2.6
VEN V
Voltage IEN/UV = -25 µA 0.8 1.2 1.6
EN/UV Current > IDIS (MOSFET Not
IS1 290 µA
Switching) See Note A
TNY274 275 360
TNY275 295 400
DRAIN Supply EN/UV Open TNY276 310 430
Current (MOSFET
IS2 TNY277 365 460 µA
Switching at fOSC)
See Note B TNY278 445 540
TNY279 510 640
TNY280 630 760
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TNY274-280
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol Min Typ Max Units
See Figure 16
(Unless Otherwise Specified)
CONTROL FUNCTIONS (cont.)
TNY274 -6 -3.8 -1.8
VBP/M = 0 V,
ICH1 TJ = 25 °C TNY275-279 -8.3 -5.4 -2.5
See Note C, D
BP/M Pin Charge TNY280 -9.7 -6.8 -3.9
mA
Current TNY274 -4.1 -2.3 -1
VBP/M = 4 V,
ICH2 TJ = 25 °C TNY275-279 -5 -3.5 -1.5
See Note C, D
TNY280 -6.6 -4.6 -2.1
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TNY274-280
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol Min Typ Max Units
See Figure 16
(Unless Otherwise Specified)
CIRCUIT PROTECTION (cont.)
TNY276 di/dt = 70 mA/µs
256 275 305
TJ = 25 °C See Note E
TNY277 di/dt = 90 mA/µs
326 350 388
Reduced Current TJ = 25 °C See Note E
Limit (BP/M TNY278 di/dt = 110 mA/µs
ILIMITred 419 450 499 mA
Capacitor = 1 µF) TJ = 25 °C See Note E
See Note D TNY279 di/dt = 130 mA/µs
512 550 610
TJ = 25 °C See Note E
TNY280 di/dt = 150 mA/µs
605 650 721
TJ = 25 °C See Note E
TNY274 di/dt = 50 mA/µs
196 210 233
TJ = 25 °C See Note E, F
TNY275 di/dt = 55 mA/µs
326 350 388
TJ = 25 °C See Note E
TNY276 di/dt = 70 mA/µs
419 450 499
Increased Current TJ = 25 °C See Note E
Limit (BP/M TNY277 di/dt = 90 mA/µs
ILIMITinc 512 550 610 mA
Capacitor = 10 µF) TJ = 25 °C See Note E
See Note D TNY278 di/dt = 110 mA/µs
605 650 721
TJ = 25 °C See Note E
TNY279 di/dt = 130 mA/µs
698 750 833
TJ = 25 °C See Note E
TNY280 di/dt = 150 mA/µs
791 850 943
TJ = 25 °C See Note E
Standard 0.9 × 1.12 ×
I2f
Current Limit I2f I2f
I2f = ILIMIT(TYP)2 ×
Power Coefficient I2f
fOSC(TYP) Reduced or A2Hz
0.9 × 1.16 ×
Increased I2f
I2f I2f
Current Limit
See Figure 19 0.75 ×
Initial Current Limit IINIT
TJ = 25 °C, See Note G ILIMIT(MIN) mA
Leading Edge TJ = 25 °C
tLEB 170 215 ns
Blanking Time See Note G
Current Limit TJ = 25 °C
tILD 150 ns
Delay See Note G, H
Thermal Shutdown
TSD 135 142 150 °C
Temperature
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TNY274-280
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol Min Typ Max Units
See Figure 16
(Unless Otherwise Specified)
CIRCUIT PROTECTION (cont.)
Thermal Shut-
TSDH 75 °C
down Hysteresis
BP/M Pin Shut-
down Threshold ISD 4 5.5 7.5 mA
Current
TNY275 TJ = 25 °C 19 22
ID = 28 mA TJ = 100 °C 29 33
TNY276 TJ = 25 °C 14 16
ID = 35 mA TJ = 100 °C 21 24
16 E
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TNY274-280
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol Min Typ Max Units
See Figure 16
(Unless Otherwise Specified)
OUTPUT (cont.)
Auto-Restart TJ = 25 °C
tAR 64 ms
ON-Time at fOSC See Note K
Auto-Restart
DCAR TJ = 25 °C 3 %
Duty Cycle
NOTES:
A. IS1 is an accurate estimate of device controller current consumption at no-load, since operating frequency is so
low under these conditions. Total device consumption at no-load is the sum of IS1 and IDSS2.
B Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the
DRAIN. An alternative is to measure the BP/M pin current at 6.1 V.
C. BP/M pin is not intended for sourcing supply current to external circuitry.
D. To ensure correct current limit it is recommended that nominal 0.1 µF / 1 µF / 10 µF capacitors are used. In
addition, the BP/M capacitor value tolerance should be equal or better than indicated below across the ambient
temperature range of the target application. The minimum and maximum capacitor values are guaranteed by
characterization.
F. TNY274 does not set an increased current limit value, but with a 10 µF BP/M pin capacitor the current limit is the
same as with a 1 µF BP/M pin capacitor (reduced current limit value).
H. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the ILIMIT
specification.
I. IDSS1 is the worst case OFF state leakage specification at 80% of BVDSS and maximum operating junction
temperature. IDSS2 is a typical specification under worst case application conditions (rectified 265 VAC) for no-load
consumption calculations.
J. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up
to but not exceeding minimum BVDSS.
K. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to
frequency).
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2/06 17
TNY274-280
470 Ω
5W S2
470 Ω
S D
S1
S
2 MΩ
S BP/M 50 V
EN/UV 10 V
S
150 V
0.1 µF
NOTE: This test circuit is not applicable for current limit or output characteristic measurements.
PI-4079-080905
DCMAX
(internal signal)
tP
EN/UV
tEN/UV
VDRAIN
1
tP =
fOSC
PI-2364-012699
Figure 17. Duty Cycle Measurement. Figure 18. Output Enable Timing.
PI-4279-013006
0.8
18 E
2/06
TNY274-280
PI-4280-012306
PI-2213-012301
1.0
(Normalized to 25 °C)
(Normalized to 25 °C)
Breakdown Voltage
Output Frequency
0.8
1.0 0.6
0.4
0.2
0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125
Junction Temperature (°C) Junction Temperature (°C)
Figure 20. Breakdown vs. Temperature. Figure 21. Frequency vs. Temperature.
1.2 1.4
PI-4081-082305
PI-4102-010906
1.0
0.8
0.8 Normalized
0.6 di/dt = 1
0.6 TNY274 50 mA/µs
TNY275 55 mA/µs Note: For the
0.4 TNY276 70 mA/µs normalized current
0.4 limit value, use the
TNY277 90 mA/µs
TNY278 110 mA/µs typical current limit
0.2 specified for the
0.2 TNY279 130 mA/µs appropriate BP/M
TNY280 150 mA/µs capacitor.
0 0
-50 0 50 100 150 1 2 3 4
Temperature (°C) Normalized di/dt
Figure 22. Standard Current Limit vs. Temperature. Figure 23. Current Limit vs. di/dt.
300 1000
PI-4083-082305
PI-4082-082305
Scaling Factors:
TNY274 1.0
250
Drain Capacitance (pF)
TNY275 1.5
Drain Current (mA)
TNY276 2.0
200 TNY277 3.5 100
TNY278 5.5 Scaling Factors:
TNY279 7.3 TNY274 1.0
150 TNY280 11 TNY275 1.5
TNY276 2.0
TNY277 3.5
100 10 TNY278 5.5
TNY279 7.3
TCASE=25 °C TNY280 11
50 TCASE=100 °C
0 1
0 2 4 6 8 10 0 100 200 300 400 500 600
DRAIN Voltage (V) Drain Voltage (V)
Figure 24. Output Characteristic. Figure 25. COSS vs. Drain Voltage.
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2/06 19
TNY274-280
PI-4084-082305
1.2
PI-4281-012306
Scaling Factors:
TNY274 1.0
Under-Voltage Threshold
40 1.0
TNY275 1.5
(Normalized to 25 °C)
TNY276 2.0
TNY277 3.5
Power (mW)
0.8
30 TNY278 5.5
TNY279 7.3
TNY280 11 0.6
20
0.4
10 0.2
0 0
0 200 400 600 -50 -25 0 25 50 75 100 125
Figure 26. Drain Capacitance Power. Figure 27. Under-Voltage Threshold vs. Temperature.
20 E
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TNY274-280
DIP-8C
⊕D S .004 (.10) Notes:
-E- 1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
.240 (6.10) 3. Dimensions shown do not include mold flash or other
.260 (6.60) protrusions. Mold flash or protrusions shall not exceed
.006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock-
wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 3 is omitted.
Pin 1
5. Minimum metal to metal spacing at the package body for
.367 (9.32) the omitted lead location is .137 inch (3.48 mm).
-D- 6. Lead width measured at package body.
.387 (9.83)
7. Lead spacing measured with the leads constrained to be
.057 (1.45) perpendicular to plane T.
.068 (1.73)
(NOTE 6)
.125 (3.18) .015 (.38)
.145 (3.68) MINIMUM
-T-
SEATING .008 (.20)
PLANE .120 (3.05) .015 (.38)
.140 (3.56)
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TNY274-280
SMD-8C
Notes:
⊕ D S .004 (.10) .046 .060 .060 .046 1. Controlling dimensions are
inches. Millimeter sizes are
-E- shown in parentheses.
.080 2. Dimensions shown do not
include mold flash or other
.086 protrusions. Mold flash or
.186 protrusions shall not exceed
.372 (9.45) .006 (.15) on any side.
.240 (6.10)
.388 (9.86) .286 .420 3. Pin locations start with Pin 1,
.260 (6.60)
⊕ E S .010 (.25) and continue counter-clock-
wise to Pin 8 when viewed
from the top. Pin 3 is omitted.
4. Minimum metal to metal
spacing at the package body
Pin 1 Pin 1 for the omitted lead location
.137 (3.48) is .137 inch (3.48 mm).
MINIMUM Solder Pad Dimensions 5. Lead width measured at
.100 (2.54) (BSC)
package body.
6. D and E are referenced
.367 (9.32) datums on the package
-D-
.387 (9.83) body.
.057 (1.45)
.125 (3.18) .068 (1.73)
.145 (3.68) (NOTE 5)
.004 (.10)
.032 (.81) .048 (1.22)
.053 (1.35)
.009 (.23) .004 (.10) .036 (0.91) 0°- 8°
.037 (.94)
.012 (.30) .044 (1.12) G08C
PI-4015-013106
22 E
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TNY274-280
E
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TNY274-280
PATENT INFORMATION
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S.
and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrationsʼ patents
may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm.
LIFE SUPPORT POLICY
POWER INTEGRATIONSʼ PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform,
when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, EcoSmart, Clampless, E-Shield, Filterfuse,
PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.
©Copyright 2006, Power Integrations, Inc.
24 E
2/06