2017 4th International Conference on Signal Processing and Integrated Networks (SPIN)

Analysis of Vedic Multiplier using Various Adder

Topologies

Shamim Akhter, Vikas Saini, Jasmine Saini

JIIT Noida,ECE Department
shamim.akhter@jiit.ac.in, vikas.km.saini@gmail.com, jasmine.saini@jiit.ac.in

Abstract— Vedic maths based multiplier is a novel and high B can be represented as AMAL and BMBL. Multiplication
speed multiplier. Adder is one of the main components used in operation between A and B can be represented as:
this technique. Using fast adder will enhance the overall
performance of the Vedic multiplier. In this work, comparative
analysis is done using different adder architectures in Synopsis
Design Compiler with different standard cell libraries at 32/28
nm. Various Adder topologies like Ripple Carry Adder (RCA),
Carry Select Adder (CSA), Square Root Carry Select Adder
(SQRT-CSA), Common Boolean Logic (CBL) and Binary to
Excess one Converter (BEC) are used to compare area, delay and
power. Designing is done for 8-bit, 16-bit, 32-bit and 64-bit Vedic Figure 1: Cross Multiplication Representations [1]
multiplier using the above adders. It is found that 64-bit Vedic
multiplier using SQRT-CSA adder is approximately 5% faster
than RCA-CSA and BEC, 75% faster than CBL and RCA These partial products can be generated and added as per
structure proposed in [1]. The block diagram for 16x16
Keywords—Vedic Multiplier, RCA, CBL, BEC, CSA, SQRT-CSA, Multiplication based on Vedic technique as proposed in [1] is
Design Compiler, Power, Delay, Area.
shown in Figure 2. The first stage is four sets of 8x8 Multiplier
I. INTRODUCTION which is also based on Vedic technique.
Multiplication operation is intensively used in digital signal
processing applications, so there is a need for high speed
multiplier. This paper presents a systematic design
methodology for fast and area efficient multiplier based on
Vedic mathematics [1].The Multiplier Architecture is based on
the Vertical and Crosswise algorithm of ancient Indian Vedic
Mathematics. The adder block used in Vedic multiplier is the
main source of delay in overall multiplication operation.
The organization of this paper is as follows. Section-II
presents logic for Vedic Algorithm based multiplication
operation. Section-III deals with different adder topologies.
Section –IV deals with the Comparative Analysis of Vedic
Multipliers using different adder architectures followed by
conclusion and references.
II. VEDIC ALGORITHM BASED MULTIPLICATION
The generalized structure of Vedic multiplier is proposed in
[1]. The basic module is 2x2 Multiplier. For N x N
multiplication, divide the multiplicand and multiplier into two
parts, consisting of (N to N/2-1) bits and (N/2 to 1) bits. For Figure 2: Block Diagram for 16-bit Vedic Multiplication [1]
example, if A=0000001010101101, then it is divided as
00000010, and 10101101. Similarly if B= 0010001110101011, As can be seen that adder is used in the intermediate
then it can be divided as 00100011 and 10101011. computation, hence fast and area efficient design will enhance
Representing the divided parts of A as AM and AL. Similarly the overall performance of multiplication. In next section,
for the input B, it is divided in two parts as BM and BL. A and different adder topologies are discussed which are used to
design Vedic multiplier for different input bit length.

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 2017 4th International Conference on Signal Processing and Integrated Networks (SPIN)

III. DIFFERENT TOPOLOGIES FOR ADDER 12

10

Delay(ns)
8
In literature different architectures of adders namely Ripple 6
Carry Adder (RCA) [2, 3], CSA [2, 4-11], CBL [2, 7] and 4
SQRT-CSA, Modified SQRT-CSA [6] is available. A brief 2
discussion on above adders is given below for clarity. 0
8bit 16bit 32bit 64bit
RCA 1.69 3.15 5.81 10.94
RCA is basic parallel adder where a chain of adders are BEC 1.97 3.08 4.5 6.48
cascaded with carry rippled from one stage to another. In CSA,
each stage consists of two ripple carry adders and a set of RCA-CSA 1.69 2.7 4.26 6.54
multiplexers. Based on previous carry input, the current sum SQRT-CSA 1.69 2.36 4.04 6.27
and carry for the next stage is computed. As the bit length of CBL 1.62 2.39 5.79 10.94
input data to the adder increases, the number of stages of CSA
also increases. In linear CSA, equal number of input bits is Figure 3: Delay of Vedic Multiplier using different Adders for HVT
used in all the stages. Later SQRT-CSA was proposed where
the progressively increasing input bit size was used for 9
different stages. It was found that delay distribution in SQRT- 8

Delay(ns)
CSA was much better than that of linear CSA. 7
6
Later Modified SQRT-CSA was proposed in which CSA 5
with Cin =1 was replaced by BEC (Binary to Excess-1 4
Converter) [5, 6]. 3
2
We have used std_cell based approach where synthesis tool 1
use predesigned optimized cell for the realization. Next section 0
deals with the analysis of Vedic multiplier based on different 8bit 16bit 32bit 64bit
adder topologies. RCA 1.24 2.32 4.26 7.99
BEC 1.46 2.27 3.33 4.8
IV. COMPARATIVE ANALYSIS OF VEDIC MULTIPLIERS RCA-CSA 1.25 1.99 3.15 4.84
USING DIFFERENT ADDER ARCHITECTURE SQRT-CSA 1.24 1.94 2.98 4.62
In this section, we have presented the comparison of delay, CBL 1.2 1.77 4.2 8.11
power and area of Vedic multiplier using various adders in
32/28nm digital Standard Cell Library by Synopsis Design Figure 4: Delay of Vedic Multiplier using different Adders for RVT
Compiler. Important aspects of digital design, like area, power,
and delay are computed by Design Compiler. For this we need
HDL code of the design and standard cells library at desired
8
technology node. Different Standard Cells Libraries are
provided by the Synopsis for the academic purpose. The 6
Delay(ns)

Libraries are in three formats .db ,.lib and .v. In Design

Compiler .db format is required. The .lib format is the readable 4
format of the .db format.
2
We have computed the area, power or delay for the vedic
multiplier using different adders with different input bit 0
8bit 16bit 32bit 64bit
lengths. We have developed HDL code for each module for
different input bit length. Figures 3, 4 and 5 show the delay for RCA 1.04 1.96 3.61 6.78
32/28nm technology for HVT (High voltage threshold), RVT BEC 1.23 1.91 2.8 4.4
(Regular Voltage Threshold), and LVT (Low Voltage
Threshold) respectively for different multiplier architecture for RCA-CSA 1.05 1.93 2.52 4.09
8-bit, 16-bit, 32-bit and 64-bit adder. RVT is equivalent to SQRT-CSA 1.05 1.64 2.52 3.91
standard Voltage Threshold (units are in Neno-second).
CBL 1 1.48 3.58 6.75
Figure 5: Delay of Vedic Multiplier using different Adders for LVT
From delay point of view, it can be concluded that as the input
length increases, SQRT-CSA based Vedic multiplier
outperform in all threshold cases. Figures 6, 7 and 8 show the
dynamic dissipation power for 32/28nm technology for HVT,
RVT, and LVT respectively (units are in Microwatt).

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8000
7000

Power (μW)
7000
Power (μW)
6000
6000
5000
5000
4000
4000
3000
3000
2000 2000
1000 1000
0 0
8bit 16bit 32bit 64bit 8bit 16bit 32bit 64bit
RCA 31.46 123.05 823.37 3630.2 RCA 31.98 125.95 837.24 3691.6
BEC 41.96 235.49 1125.8 4973.5 BEC 43.18 243.3 1165 5146.6
RCA-CSA 41.48 263.14 1342.9 6106.6 RCA-CSA 42.19 254.04 1476.4 6217
SQRT-CSA 45.49 287.36 1449.7 6573.2 SQRT-CSA 46.31 292.62 1476.4 6694.3
CBL 39.61 129.64 1035.1 4572 CBL 40.5 132.58 1058.6 4675.6

Figure 6: Dynamic Power Dissipation of Vedic Multiplier for HVT

Figure 8: Dynamic Power Dissipation of Vedic Multiplier for LVT

8000
160000
Power (μW)

7000
140000
Area (sq.μm)

6000
120000
5000
100000
4000
80000
3000
60000
2000
40000
1000
20000
0 0
8bit 16bit 32bit 64bit 8bit 16bit 32bit 64bit
RCA 31.92 125.73 836.3 3687.7 RCA 1159.59 5026.66 23770.98 104356.86
BEC 42.47 238.62 1141.5 5043.9 BEC 1336.69 6233.05 27859.46 121719.73
RCA-CSA 42.12 267.4 1365.1 6208.1 RCA-CSA 1341.73 6666.24 30621.14 134931.24
SQRT-CSA 46.22 292.15 1474.2 6684.4 SQRT-CSA 1432.19 6978.88 32687.56 143356.15
CBL 40.31 131.92 1054 4655.5 CBL 1370.91 5153.17 27815.53 121024.12

Figure 7: Dynamic Power Dissipation of Vedic Multiplier for RVT Figure 9: Area of Vedic Multiplier using different Adders

From the Figures 6,7, and 8, it can be concluded that as the Figure 9 shows silicon area required to realize design (units are
input length increases, RCA followed by CBL based Vedic in square Micrometer). From Figure 9, it can inferred that as
multiplier outperform.

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 2017 4th International Conference on Signal Processing and Integrated Networks (SPIN)

the input length increase, the BEC which is Modified SQRT-
based is better as compared to other architecture of adder.
The leakage power analysis is shown in Figure.10 for different
architecture of 8-bit, 16-bit, 32-bit and 64-bit adders (units are
in Microwatt). Again BEC based implementation outperforms
other like CSA, CBL, SQRT-CSA.
3500
Power (μW)
With respect to Power Dissipation: RCA consumes power
approximately 20% lesser than CBL, 35% lesser than BEC,
65% lesser than RCA-CSA and 80% lesser than SQRT-CSA.
With respect to Area: RCA requires area approximately 10%
less than CBL, 20% less than BEC, 30% less than RCA-CSA
and 40% less than SQRT-CSA.
With respect to Leakage Power: RCA has leakage power
approximately 15% less than BEC, 25% less than CBL, 30%
less than RCA-CSA and 460% less than SQRT-CSA.
So depending upon the requirements we can chose the adder

3000
accordingly. The similar analysis can also be performed on
2500 other various adders for standard cell at different technology
node.
2000
REFERENCES
1500
[1] S. Akhter, “VHDL Implementation of Fast NxN Multiplier Based on
1000 Vedic Mathematic”, Proc. of 18th European Conference on Circuit
Theory and Design (ECCTD), pp. 472-475, Aug. 2007.
500 [2] Vikas K. Saini, Shamim Akhter, and Tanuj Chauhan, “Implementation,
Test Pattern Generation, and Comparative Analysis of Different Adder
0 Circuits”, VLSI Design, Vol. 2016, Article ID 1260879, 8 pages, 2016.
8bit 16bit 32bit 64bit doi:10.1155/2016/1260879.
[3] N. H. E. Weste, D. Harris, and A. Banerjee, “CMOS VLSI Design: A
RCA 25.85 107 495.67 2038.5 Circuits and Systems Perspective”, Pearson Education, 3rd Edition, 2005.
[4] Basant Kumar Mohanty and Sujit Kumar Patel “Area-Delay-Power
BEC 29.08 133.73 571.39 2361.8 Efficient Carry-Select Adder” ,IEEE Transaction On Circuits and
RCA-CSA Systems-II Express Briefs, Vol-61, No.6, June 2014.
29.92 147.31 689.68 2705.7 [5] O. J. Bedrij, “Carry-select adder,” IEEE IRE Transactions on Electronic
SQRT-CSA 31.83 157.2 689.68 2883.4 Computers, Vol: EC – 11, pp. 340–344, 1962.
[6] S.Akhter, S. Chaturvedi, and K.Pardhasardi, “CMOS Implementation of
CBL 31.95 117.73 614.15 2524.9 Efficient 16-Bit Square Root Carry-Select Adder”,2nd International
Conference on Signal Processing and Integrated Networks (SPIN), India,
Noida, pp. 891 – 896, Feb 2015.
[7] B. Ramkumar, and H. M. Kittur, “Low-Power and Area- Efficient Carry
Select Adder”, IEEE Transactions on Very Large Scale Integration
Figure 10: Leakage Power of Vedic Multiplier using different Adders (VLSI) Systems, Vol. 20, No. 2, pp. 371-375, Feb. 2012.
[8] G.Singh , “Design of Low Area and Low Power Modified 32-BIT Square
Root Carry Select Adder”, International Journal of Engineering Research
V. CONCLUSION and General Science Vol 2, No. 4, pp-422-431, 2014.
[9] I-Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin, and Chien-Chang PengAn
A comparative analysis of Vedic multiplier using various “Area-Efficient Carry Select Adder Design by Sharing the Common
digital adders has been presented in this paper. The parameters Boolean Logic Term”, International Multiconference of Engineers and
Computer Scientists, Vol 2, March 2012.
of comparison were delay, area and power (dynamic and
[10] Yajuan He, Chip-Hong Chang and Jiangmin Gu “An Area Efficient 64-
leakage) using digital standard cell library. bit Square Root Carry-select Adder for Low Power Applications”, IEEE
International Symposium on Circuits and Systems”, Vol.4, pp.4082 –
With respect to Delay: 8-bit Vedic multiplier using CBL 4085, May 2005.
adder is approximately 5% faster than SQRT-CSA, RCA-CSA, [11] V. Kokilavani, K. Preethi, and P. Balasubramanian “FPGA-Based
RCA and 20% faster than BEC. Synthesis of High-Speed Hybrid Carry Select Adders”, Advances in
Electronics,Volume 2015, Article ID 713843, 13 pages doi:
16-bit Vedic multiplier using CBL adder is /10.1155/2015/713843.
approximately 10% faster than SQRT-CSA and RCA-CSA and
30% faster than BEC and RCA.
32-bit Vedic multiplier using SQRT-CSA adder is
approximately 5% faster than RCA-CSA and 10% faster than
BEC, and 40% faster than CBL and RCA.

64-bit Vedic multiplier using SQRT-CSA adder is

approximately 5% faster than RCA-CSA and BEC, 75% faster
than CBL and RCA.

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