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Irf740, Sihf740: Vishay Siliconix
Irf740, Sihf740: Vishay Siliconix
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
• Dynamic dV/dt Rating
VDS (V) 400 Available
• Repetitive Avalanche Rated
RDS(on) (Ω) VGS = 10 V 0.55
• Fast Switching RoHS*
Qg (Max.) (nC) 63 COMPLIANT
ORDERING INFORMATION
Package TO-220AB
IRF740PbF
Lead (Pb)-free
SiHF740-E3
IRF740
SnPb
SiHF740
VGS
Top 15 V
10 V 150 °C
8.0 V 101
ID, Drain Current (A)
101
91054_01 VDS, Drain-to-Source Voltage (V) 91054_03 VGS, Gate-to-Source Voltage (V)
3.0
RDS(on), Drain-to-Source On Resistance
VGS ID = 10 A
Top 15 V VGS = 10 V
101 10 V 2.5
8.0 V
ID, Drain Current (A)
7.0 V
2.0
(Normalized)
6.0 V
5.5 V 4.5 V
5.0 V 1.5
Bottom 4.5 V
100 1.0
0.5
20 µs Pulse Width
TC = 150 °C
0.0
10-1 100 101 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160
91054_02 VDS, Drain-to-Source Voltage (V) 91054_04 TJ, Junction Temperature (°C)
Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 4 - Normalized On-Resistance vs. Temperature
2500
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
25 °C
1500 Ciss
1000 100
Coss
500
Crss
VGS = 0 V
0 10-1
100 101 0.50 0.70 0.90 1.10 1.30 1.50
91054_05 VDS, Drain-to-Source Voltage (V) 91054_07 VSD, Source-to-Drain Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage
20 103
ID = 10 A
VGS, Gate-to-Source Voltage (V)
5
VDS = 320 V Operation in this area limited
16 2 by RDS(on)
ID, Drain Current (A)
10 100 µs
5
8
2
1 ms
1 10 ms
4
5 TC = 25 °C
For test circuit TJ = 150 °C
2
see figure 13 Single Pulse
0 0.1 2 5 2 5 2 5 2 5
0 15 30 45 60 75 0.1 1 10 102 103
91054_06 QG, Total Gate Charge (nC) 91054_08 VDS, Drain-to-Source Voltage (V)
Fig. 6 - Typical Gate Charge vs. Drain-to-Source Voltage Fig. 8 - Maximum Safe Operating Area
RD
10 VDS
VGS
D.U.T.
8 RG
ID, Drain Current (A)
+
- VDD
6
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
4
0 VDS
25 50 75 100 125 150
90 %
91054_09 TC, Case Temperature (°C)
10
Thermal Response (ZthJC)
1
0 - 0.5
PDM
0.2
0.1 0.1
t1
0.05 t2
0.02 Single Pulse Notes:
0.01 (Thermal Response) 1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-2
10-5 10-4 10-3 10-2 0.1 1 10
L
VDS
VDS
Vary tp to obtain tp
required IAS
VDD
RG D.U.T +
V DD
- VDS
IAS
10 V
tp 0.01 Ω
IAS
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
1200
ID
Top 4.5 A
EAS, Single Pulse Energy (mJ)
1000 5.3 A
Bottom 10 A
800
600
400
200
VDD = 50 V
0
25 50 75 100 125 150
Current regulator
Same type as D.U.T.
QG 50 kΩ
10 V 12 V 0.2 µF
0.3 µF
QGS QGD +
VDS
D.U.T. -
VG
VGS
3 mA
Charge
IG ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
- +
-
Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test
VGS = 10 Va
Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD
Re-applied
voltage
Body diode forward drop
Inductor current
Ripple ≤ 5 % ISD
Note
a. VGS = 5 V for logic level devices
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91054.
DWG: 6031
Note
• M* = 0.052 inches to 0.064 inches (dimension including
protrusion), heatsink hole for HVM
C
b
e
J(1)
e(1)
Package Picture
ASE Xi’an
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