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JFET AMPLIFIER CONFIGURATIONS

+15V +15V +15V

RL RL

+ +

+ +

+ +
+
+
+
+
VOUT + + VOUT
Vin RG Vin RG RS VOUT Vin
RS RS
- -
- - - -

[a] Common Source Amplifier [b] Common Drain [Source Follower] Amplifier [c] Common Gate Amplifier

Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007.MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].
JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITS
COMMON SOURCE AMPLIFIER WITH BYPASSED SOURCE RESISTOR

+15V

ID
RL

d
+ g +
2N5459

Ri s
Vout
+ RG
RS
Vi
_ _

g d
+
Vgs gmVgs +
Ri _ s
+
RL Vout
Vi
_ RS
_

vout − g m v gs RL − g m v gs RL
Av = = =
vin v gs + g m v gs RS v gs [1 + g m RS ]
− g m RL
Av = or Av = − g m RL
1 + g m RS
2 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].
JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITS
COMMON DRAIN [SOURCE FOLLOWER] AMPLIFIER

+15V

ID

+ g
2N5459

Ri s
+ RG +
RS Vout
Vi
_ _

g d
+
Vgs gmVgs
Ri _ s
+ +
Vi
_ RS Vout

vout g m v gs RS g m v gs RS g m RS
Av = = = ; Av =
vin v gs + g m v gs RS v gs [1 + g m RS ] 1 + g m RS

3 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].
JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITS
COMMON GATE AMPLIFIER

+15V

ID
RL

d
g +
2N5459
+ s
Ri Vout
+ RS
Vi
_ _

gmVgs +
s
_ RL
Ri Vout

+ Vgs RS
Vi
+ _
_ g

4 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].
v − g m v gs RL g m RL
A = out = = ; if Ri = 0,
v v ⎡ R ⎤ Ri
− v gs ⎢ g m Ri + i + 1⎥ 1 + g m Ri +
in

⎣ RS ⎦ RS

then Av = g m RL

5 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].
DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
CAMBRIDGE, MASSACHUSETTS 02139

Low Frequency Hybrid-π Equation Chart

TRANSISTORS

Characteristic Common CE with RE CC [E. Follower] Common Base


Emitter
Voltage Gain Av = − g m RL RL Av ≈ 1 β o RL
Av ≈ − Av =
[if ro >>RL]
RE rπ // RE + (β o + 1)Rs

Current Gain βo βo β o+1 βo


βo +1
Input rπ // RB [rπ + (β o + 1)RE ] // RB [rπ + (β o + 1)RE ] // RB rπ
Impedance β o +1
Output RL RL ⎡ (rπ + Rs // RB ) ⎤ RL

β o + 1 ⎥⎦
Impedance // RE
[if ro >>RL] [if ro >>RL] ⎣ [if ro >>RL]

Phase Yes Yes No No


Reversal?

JFET’S

Characteristic Common Source C Source with Common Drain Common Gate


RS [Source Follower]
Voltage Gain Av = − g m RL − g m RL g m RS g m RL
Av = Av = Av =
1 + g m RS 1 + g m RS Ri
[if rds >>RL] 1 + g m Ri +
RS
Ri = generator resistance
Current Gain ID ID ID g m RS
Ai =
IS IS IS g m RS + 1
Very large! Very large! Very large!
Input RG RG RG RS 1
Impedance = // RS
g m RS + 1 g m
Output RL RL RS 1 RL
Impedance [if rds >> RL] [if rds >> RL] = // RS [if rds >>RL]
g m RS + 1 g m
Phase Yes Yes No No
Reversal?

6 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].
FET COMMON-SOURCE AMPLIFIER BIASING-GRAPHICAL METHOD #1

1. FIND VGS(OFF) & IDSS FOR YOUR DEVICE; MEASURE USING CURVE TRACER.
[VGS(OFF) = GATE-SOURCE VOLTAGE FOR WHICH ID = 0. IDSS = ID WHEN VGS = 0]

2. ASSUME RS << RL.

3. PLOT A LOAD LINE ON THE OUTPUT CHARACTERISTICS. KEEP THE ID , VDS = 0


INTERCEPT ON THE GRAPH PAGE; I. E. STAY AWAY FROM NEARLY VERTICAL LOAD
LINES.

4. CALCULATE RL FROM THE LOAD LINE INTERCEPTS. USE CLOSEST STD. VALUE.

5. PICK Q-POINT VALUE OF VGS FOR MAXIMUM LINEAR OUTPUT SWING.

2
⎛ VGS ⎞⎟
6. CALCULATE ID: I D = I DSS ⎜1 − ; OR ESTIMATE FROM CHARACTERISTICS.
⎜ V ⎟
⎝ GS ( off ) ⎠

⎛ VGS ⎞
7. CALCULATE RS FOR VGS AT ID . ⎜ RS = ⎟. USE CLOSEST STANDARD VALUE.
⎝ ID ⎠

8. COMPARE RS AND RL ; IF RS IS CLOSE TO RL , REPLOT THE LOAD LINE.

9. RECALCULATE RS FOR NEW VGS . REPEAT STEPS 7 AND 8 AS NECESSARY!

CALCULATING JFET SMALL-SIGNAL gm

1. CALCULATE gm FROM ΔID /ΔVGS ON DRAIN CHARACTERISTICS FROM CURVE


TRACER [LARGE SIGNAL gm ]

2. OR USE MEDIAN SPECIFICATION SHEET VALUE. [FOR A FAST ESTIMATE.]

− 2I DSS ⎛⎜ VGS ⎞⎟ − 2I DSS ID


OR gm = 1− = WHERE VGS or ID = OPERATING POINT.
VGS( off ) ⎜⎝ VGS( off ) ⎟⎠ VGS( off ) I DSS

When VGS = VGS(OFF), ID = 0 ; IDSS = ID @ VGS = 0. NOTE THAT THE SMALL-SIGNAL

TRANSCONDUCTANCE DEPENDS ON THE DC BIAS POINT, JUST AS IT DOES


FOR THE BIPOLAR TRANSISTOR!

7 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].
FET COMMON-SOURCE AMPLIFIER BIASING-GRAPHICAL METHOD #2

1. FIND VGS(OFF) & IDSS FOR YOUR DEVICE; MEASURE USING CURVE TRACER.
[VGS(OFF) = GATE-SOURCE VOLTAGE FOR WHICH ID = 0. IDSS = ID WHEN VGS = 0]

2. REFER TO THE COMBINED TRANSFER [TRANSCONDUCTANCE] CHARACTERISTICS


AND DRAIN CHARACTERISTICS CURVES [ATTACHED].

VGS( OFF)
3. CHOOSE RS AS FOLLOWS: R S = . DRAW THE LINE REPRESENTING RS
I DSS
FROM THE ORIGIN OF THE TRANSFER CURVE GRAPH; THE “Q” POINT IS AT THE
INTERSECTION OF THE TWO PLOTS. THIS SETS IDQ AT ABOUT 0.4 IDSS.

4. EXTEND A HORIZONTAL LINE FROM THE IDQ VALUE ON THE TRANSFER


CHARACTERISTICS’ LEFT-HAND AXIS ALL THE WAY ACROSS THROUGH THE DRAIN
CHARACTERISTICS.

5. THE RIGHT-HAND VOLTAGE INTERCEPT FOR THE LOAD LINE [ON THE DRAIN
CHARACTERISTICS] IS EQUAL TO THE SUPPLY VOLTAGE VDD. CHOOSE A VALUE FOR
VDSQ THAT GIVES A ROUGHLY SYMMETRICAL OUTPUT VOLTAGE SWING AROUND VDSQ.

6. DRAW A VERTICAL LINE FROM VDSQ UPWARDS TO INTERSECT WITH THE LINE
DRAWN IN STEP #4. THIS INTERSECTION GIVES THE Q-POINT.

7. DRAW THE LOAD LINE FROM THE SUPPLY VOLTAGE THRU THE Q-POINT UNTIL IT
INTERSECTS WITH THE CURRENT AXIS.

8. DIVIDE THE SUPPLY VOLTAGE BY THE CURRENT AXIS VALUE TO GET THE TOTAL
VALUE OF RESISTANCE IN THE DRAIN-SOURCE CIRCUIT.

9. SUBTRACT THE VALUE OF RS FOUND IN STEP #3 FROM THE VALUE FOUND IN STEP
#8 TO GET THE VALUE OF LOAD [OR DRAIN] RESISTOR. USE CLOSEST STANDARD
VALUE FOR BOTH RESISTORS.

10. NOTE THAT THE MORE VERTICAL THE LOAD LINE, THE SMALLER THE VALUE OF
RL. LOW RL EQUALS LOW VOLTAGE GAIN [AV = - gmRL]. ACCEPTING A LOWER
VOLTAGE VDQ WITH ITS ATTENDANT ASYMMETRICAL VOLTAGE SWING WILL ALLOW A
HIGHER VALUE RL. INCREASING SUPPLY VOLTAGE WILL ALSO ALLOW A LARGER
VALUE OF RL AND A MORE SYMMETRICAL VOLTAGE SWING. [THE MORE HORIZONTAL
THE LOAD LINE, THE HIGHER THE TOTAL DRAIN-SOURCE RESISTANCE.]

8 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].
FET SOURCE-FOLLOWER LOAD LINE/GAIN EXAMPLES & METHOD

1. FIND VGS(OFF) & IDSS FOR YOUR DEVICE; MEASURE USING CURVE TRACER.
[VGS(OFF) = GATE-SOURCE VOLTAGE FOR WHICH ID = 0. IDSS = ID WHEN VGS = 0]

2. CHOOSE Q-POINT; i.e. CHOOSE -VGS FROM DRAIN CHARACTERISTICS GRAPH.

2
⎛ VGS ⎞⎟
3. CALCULATE ID: I D = I DSS ⎜1 − ; OR ESTIMATE FROM CHARACTERISTICS.
⎜ V ⎟
⎝ GS ( off ) ⎠

4. CALCULATE RS; USE CLOSEST STANDARD VALUE.

5. CALCULATE LOAD LINE INTERCEPTS, [MAY HAVE TO USE Δ BECAUSE THE


ID-VDS = 0 INTERCEPT MAY BE WAY OFF THE GRAPH PAGE].

− 2I DSS ⎛⎜ VGS ⎞⎟ − 2I DSS ID


6. CALCULATE gm: gm = 1− =
VGS( off ) ⎜⎝ VGS( off ) ⎟⎠ VGS( off ) I DSS

gm RS
7. CALCULATE Av: Av =
1 + gm RS
1
8. Ro = // RS
gm

9. EXAMPLES [VP = VGS(OFF) = -5.8V; IDSS = 9mA]

Example 1 Example 2 Example 3

1. VGS, ID -4V, 1.2mA -3V, 2.3mA -2V, 4.2mA

2. RS= 3.3 kΩ 1.2 kΩ 470 Ω

3. Δ ID @ Δ VDS 4.55mA 12.5V, 5.32mA 10V, 4.17mA

4. gm= 963 μMHO 1,500 μMHO 2,030 μMHO

9 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].
5. Av= .761 .643 .488

6. Ro= 790Ω 428Ω 240Ω

10 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].

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