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Amplier Jfet PDF
Amplier Jfet PDF
RL RL
+ +
+ +
+ +
+
+
+
+
VOUT + + VOUT
Vin RG Vin RG RS VOUT Vin
RS RS
- -
- - - -
[a] Common Source Amplifier [b] Common Drain [Source Follower] Amplifier [c] Common Gate Amplifier
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007.MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].
JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITS
COMMON SOURCE AMPLIFIER WITH BYPASSED SOURCE RESISTOR
+15V
ID
RL
d
+ g +
2N5459
Ri s
Vout
+ RG
RS
Vi
_ _
g d
+
Vgs gmVgs +
Ri _ s
+
RL Vout
Vi
_ RS
_
vout − g m v gs RL − g m v gs RL
Av = = =
vin v gs + g m v gs RS v gs [1 + g m RS ]
− g m RL
Av = or Av = − g m RL
1 + g m RS
2 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].
JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITS
COMMON DRAIN [SOURCE FOLLOWER] AMPLIFIER
+15V
ID
+ g
2N5459
Ri s
+ RG +
RS Vout
Vi
_ _
g d
+
Vgs gmVgs
Ri _ s
+ +
Vi
_ RS Vout
vout g m v gs RS g m v gs RS g m RS
Av = = = ; Av =
vin v gs + g m v gs RS v gs [1 + g m RS ] 1 + g m RS
3 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].
JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITS
COMMON GATE AMPLIFIER
+15V
ID
RL
d
g +
2N5459
+ s
Ri Vout
+ RS
Vi
_ _
gmVgs +
s
_ RL
Ri Vout
+ Vgs RS
Vi
+ _
_ g
4 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].
v − g m v gs RL g m RL
A = out = = ; if Ri = 0,
v v ⎡ R ⎤ Ri
− v gs ⎢ g m Ri + i + 1⎥ 1 + g m Ri +
in
⎣ RS ⎦ RS
then Av = g m RL
5 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].
DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
CAMBRIDGE, MASSACHUSETTS 02139
TRANSISTORS
JFET’S
6 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].
FET COMMON-SOURCE AMPLIFIER BIASING-GRAPHICAL METHOD #1
1. FIND VGS(OFF) & IDSS FOR YOUR DEVICE; MEASURE USING CURVE TRACER.
[VGS(OFF) = GATE-SOURCE VOLTAGE FOR WHICH ID = 0. IDSS = ID WHEN VGS = 0]
4. CALCULATE RL FROM THE LOAD LINE INTERCEPTS. USE CLOSEST STD. VALUE.
2
⎛ VGS ⎞⎟
6. CALCULATE ID: I D = I DSS ⎜1 − ; OR ESTIMATE FROM CHARACTERISTICS.
⎜ V ⎟
⎝ GS ( off ) ⎠
⎛ VGS ⎞
7. CALCULATE RS FOR VGS AT ID . ⎜ RS = ⎟. USE CLOSEST STANDARD VALUE.
⎝ ID ⎠
7 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].
FET COMMON-SOURCE AMPLIFIER BIASING-GRAPHICAL METHOD #2
1. FIND VGS(OFF) & IDSS FOR YOUR DEVICE; MEASURE USING CURVE TRACER.
[VGS(OFF) = GATE-SOURCE VOLTAGE FOR WHICH ID = 0. IDSS = ID WHEN VGS = 0]
VGS( OFF)
3. CHOOSE RS AS FOLLOWS: R S = . DRAW THE LINE REPRESENTING RS
I DSS
FROM THE ORIGIN OF THE TRANSFER CURVE GRAPH; THE “Q” POINT IS AT THE
INTERSECTION OF THE TWO PLOTS. THIS SETS IDQ AT ABOUT 0.4 IDSS.
5. THE RIGHT-HAND VOLTAGE INTERCEPT FOR THE LOAD LINE [ON THE DRAIN
CHARACTERISTICS] IS EQUAL TO THE SUPPLY VOLTAGE VDD. CHOOSE A VALUE FOR
VDSQ THAT GIVES A ROUGHLY SYMMETRICAL OUTPUT VOLTAGE SWING AROUND VDSQ.
6. DRAW A VERTICAL LINE FROM VDSQ UPWARDS TO INTERSECT WITH THE LINE
DRAWN IN STEP #4. THIS INTERSECTION GIVES THE Q-POINT.
7. DRAW THE LOAD LINE FROM THE SUPPLY VOLTAGE THRU THE Q-POINT UNTIL IT
INTERSECTS WITH THE CURRENT AXIS.
8. DIVIDE THE SUPPLY VOLTAGE BY THE CURRENT AXIS VALUE TO GET THE TOTAL
VALUE OF RESISTANCE IN THE DRAIN-SOURCE CIRCUIT.
9. SUBTRACT THE VALUE OF RS FOUND IN STEP #3 FROM THE VALUE FOUND IN STEP
#8 TO GET THE VALUE OF LOAD [OR DRAIN] RESISTOR. USE CLOSEST STANDARD
VALUE FOR BOTH RESISTORS.
10. NOTE THAT THE MORE VERTICAL THE LOAD LINE, THE SMALLER THE VALUE OF
RL. LOW RL EQUALS LOW VOLTAGE GAIN [AV = - gmRL]. ACCEPTING A LOWER
VOLTAGE VDQ WITH ITS ATTENDANT ASYMMETRICAL VOLTAGE SWING WILL ALLOW A
HIGHER VALUE RL. INCREASING SUPPLY VOLTAGE WILL ALSO ALLOW A LARGER
VALUE OF RL AND A MORE SYMMETRICAL VOLTAGE SWING. [THE MORE HORIZONTAL
THE LOAD LINE, THE HIGHER THE TOTAL DRAIN-SOURCE RESISTANCE.]
8 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].
FET SOURCE-FOLLOWER LOAD LINE/GAIN EXAMPLES & METHOD
1. FIND VGS(OFF) & IDSS FOR YOUR DEVICE; MEASURE USING CURVE TRACER.
[VGS(OFF) = GATE-SOURCE VOLTAGE FOR WHICH ID = 0. IDSS = ID WHEN VGS = 0]
2
⎛ VGS ⎞⎟
3. CALCULATE ID: I D = I DSS ⎜1 − ; OR ESTIMATE FROM CHARACTERISTICS.
⎜ V ⎟
⎝ GS ( off ) ⎠
gm RS
7. CALCULATE Av: Av =
1 + gm RS
1
8. Ro = // RS
gm
9 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].
5. Av= .761 .643 .488
10 9/27/06
Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT
OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month
YYYY].