LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
ENTITY alu IS
END alu;

ARCHITECTURE behavior OF alu IS

COMPONENT alu_4bit
PORT(
n1 : IN std_logic_vector(3 downto 0);
n2 : IN std_logic_vector(3 downto 0);
op : IN std_logic_vector(2 downto 0);
result : OUT std_logic_vector(3 downto 0);
flag : OUT std_logic
);
END COMPONENT;

signal n1 : std_logic_vector(3 downto 0) := (others => '0');----Inputs

signal n2 : std_logic_vector(3 downto 0) := (others => '0');
signal op : std_logic_vector(2 downto 0) := (others => '0');
signal result : std_logic_vector(3 downto 0); -----Outputs
signal flag : std_logic;

BEGIN
uut: alu_4bit PORT MAP (
n1 => n1, -- Instantiate the Unit Under Test (UUT)
n2 => n2,
op => op,
result => result,
flag => flag
);

stim_proc: process -- Stimulus process

begin
n1<="1101";
n2<="0011";
op<="000";
wait for 10 ns;
op<="001";
wait for 10 ns;
op<="010";
wait for 10 ns;
op<="011";
wait for 10 ns;
op<="100";
wait for 10 ns;
op<="101";
wait for 10 ns ;
op<="110";
wait for 10 ns;
op<="111";
wait for 10 ns ;
end process;
END;