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V3

MbreakP MbreakP 1.8


3.3
W W
L L
R3 M5 M6

0
OUT

C1
M1 W W M2 250f
L L
V1 V4
DC MbreakN MbreakN DC 0
AC = 1
0
0 0

M4 M3

HW#8:
W W
L L
M=1 MbreakN MbreakN M

Please design an CMOS amplifier using 0.18um CMOS model to


meet the differential gain Av ≥ 28dB and f3dB ≥ 100MHz. The DC
bias voltage of output port is 0.9V. The loading capacitance is
0.25pF.
1. Please derive the DC voltage gain equation of the above amplifier.
2. Please also write down its small-signal model parameters gm, gds,
Cgs, and Cgd values of M2 and M6 at your bias condition.
3. Please specify all the device sizes, input DC bias voltage, bias
current, the calculated and simulated Gain and the simulated
f3dB.
CYCU/EL, Chun-Chieh Chen, AIC 1

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