ANSWER ALL QUESTIONS

PART A(9x 2 Marks = 18 Marks) BT CO MARKS

1. Draw the hardware organization of a 4 stage pipeline. AP CO3 2

Illustrate with an example how branch instructions affect the pipeline
2. AP CO3 2
operations.
3. Discuss about superscalar processors. U CO3 2
4. Distinguish between Static RAM and Dynamic RAM. U CO4 2
5. Show how logic value 1 and 0 is stored in a ROM cell with a neat diagram. AP CO4 2
Calculate the average access time of a processor with two levels of caches L1
6. and L2 with access time 25ns and 50ns, hit rate 65% and 55% respectively. AP CO4 2
The memory access time is 120ns.
7. Describe about virtual memory organization. U CO4 2

8. Identify the benefits of multicore processor architecture. U CO5 2

9. Demonstrate the two approaches of bus arbitration in DMA. AP CO5 2

PART B (2 X 16 Marks = 32 Marks) BT CO MARKS

10 i) Demonstrate how the performance of the processors is affected by

the various types of hazards in pipelining with examples. AP CO3 16
11 i) Discuss the three types of mapping in cache memory organization
and compute the number of bits used in Tag/Set/Block/word fields
of the main memory address. The main memory contains 4096 AP CO4 10
blocks, each with 128 words and the cache contain 64 blocks with 128
words in each block. (Assume a 4 way set associative cache is used).
ii) Explain how interrupts are handled in I/O organization. U CO5 6