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1.1 Existing System: Design and Implementation of Four Bit Ripple Carry Adder Using 180Nm Cmos Technology
1.1 Existing System: Design and Implementation of Four Bit Ripple Carry Adder Using 180Nm Cmos Technology
1. INTRODUCTION
Most of the VLSI applications, such as digital signal processing, image and
video processing and microprocessors, extensively use arithmetic operations. Addition,
subtraction, multiplication and multiply and accumulate (MAC) are examples of the
most commonly used operations. The 1-bit full-adder cell is the building block of all
these modules. Thus, enhancing its performance is critical for enhancing the overall
module performance. The most important performance parameters for future VLSI
systems are speed and power consumption. this paper we present a novel 1-bit full adder
cell which offers faster operation and consumes less area and power than standard
implementations of the full adder cell.
With the popularity of portable systems as well as fast growth of power density
in integrated circuits, power dissipation becomes main design objectives equal for
digital system has become main goal. Generally ripple carry adders are used among all
types of adders because of its compact design but it is the slowest adder.
Several ripple carry adders have been proposed using different full adder cells
targeting on design accents such as power, delay and area. Among those designs with
less transistor count using transmission gate logic have been widely used to reduce area.
The proposed ripple carry adder is implemented using Cadence EDA too. The
tool provides sophisticated features such as Cadence Virtuoso Schematic Editor which
provides sophisticated capabilities which speed and ease the design, Cadence Virtuoso
Visualization and Analysis which efficiently analyzes the performance of the design and
Cadence Virtuoso Layout Suite that speeds up the physical layout of the design.
In this paper, we propose a design of ripple carry adder using full adder cell with
18 transistors. The paper is organized as follows: in section II, previous work is
reviewed. Subsequently, in section III, the proposed design of ripple carry adder is
presented. In section IV, the schematic and layout of the adders are presented. In section
V, the simulation results are given and discussed. The comparison and evaluation for
proposed and conventional designs are carried out. Finally a conclusion will be made in
the last section
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
outputs, a sum and a carry; this circuit is called a full adder. The relation between the
inputs A, B, Cin and the outputs Sum and Cout are expressed as:
Inputs Outputs
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
The proposed ripple carry adder is designed using a full adder cell with 18-
transisitors based on transmission gate. It uses a novel exclusive-or (XOR) gate. The
schematic for this XOR gate is shown in Fig.1.3.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
1.3PROBLEM DEFINITION
The issue of case of design is not always attained easily. The CMOS design style
is not area efficient from complex gates with large fan-in's in conventional ripple carry
adder. The power consumption and transistor count are relatively high for low power
Arithmetic circuits. To overcome this problem we reduce the transistor count, delay and
power.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
1.7 ORGANIZATIONOFTHESIS
This is report contains six chapters.
CHAPTER 1: Introduction about the Project.
CHAPTER 2: Literature Survey introduction to VLSI.
CHAPTER 3: Hardware Description.
CHAPTER 4: Software Description.
CHAPTER 5: Results.
CHAPTER 6: Conclusion and Future Scope.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
2 . LITERATURE SURVEY
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
interconnecting them too long, the electric signals couldn't travel fast enough through
the circuit, thus making the computer too slow to be effective.
Jack Kilby at Texas Instruments found a solution to this problem in 1958.
Kilby's idea was to make all the components and the chip out of the same block
(monolith) of semiconductor material. Kilby presented his idea to his superiors, and was
allowed to build a test version of his circuit. In September 1958, he had his first
integrated circuit ready. Although the first integrated circuit was crude and had some
problems, the idea was groundbreaking. By making all the parts out of the same block
of material and adding the metal needed to connect them as a layer on top of it, there
was no need for discrete components. No more wires and components had to be
assembled manually. The circuits could be made smaller, and the manufacturing process
could be automated. From here, the idea of integrating all components on a single
silicon wafer came into existence, which led to development in small-scale integration
(SSI) in the early 1960s, medium-scale integration (MSI) in the late 1960s, and then
large-scale integration (LSI) as well as VLSI in the 1970s and 1980s, with tens of
thousands of transistors on a single chip (later hundreds of thousands, then millions, and
now billions (109)).
2.3 Developments
The first semiconductor chips held two transistors each. Subsequent advances
added more transistors, and as a consequence, more individual functions or systems
were integrated over time. The first integrated circuits held only a few devices, perhaps
as many as ten diodes, transistors, resistors and capacitors, making it possible to
fabricate one or more logic gates on a single device. Now known retrospectively as
small-scale integration (SSI), improvements in technique led to devices with hundreds
of logic gates, known as medium-scaleintegration (MSI). Further improvements led to
large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current
technology has moved far past this mark and today's microprocessors have many
millions of gates and billions of individual transistors.
At one time, there was an effort to name and calibrate various levels of large-
scale integration above VLSI. Terms like ultra-large-scale integration(ULSI) were used.
But the huge number of gates and transistors available on common devices has rendered
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
such fine distinctions moot. Terms suggesting greater than VLSI levels of integration
are no longer in widespread use.
As of early 2008, billion-transistor processors are commercially available. This
became more commonplace as semiconductor fabrication advanced from the then-
current generation of 65 nm processes. Current designs, unlike the earliest devices, use
extensive design automation and automated logic synthesis to lay out the transistors,
enabling higher levels of complexity in the resulting logic functionality. Certain high-
performance logic blocks like the SRAM (static random-access memory) cell, are still
designed by hand to ensure the highest efficiency. VLSI technology may be moving
toward further radical miniaturization with introduction of NEMS technology.1970s -
NMOS Technology – Intel 1101 SRAM – 256 bit static random access memory and
4004 4-bit microprocessor
Late 40s Transistor invented at Bell Labs
Late 50s First IC (JK-FF by Jack Kilby at TI)
Early 60s Small Scale Integration (SSI) 10s of transistors on a chip
Late 60s Medium Scale Integration (MSI) 100s of transistors on a chip
Early 70s Large Scale Integration (LSI) 1000s of transistor on a chip
Early 80s VLSI 10,000s of transistors on a chip (later 100,000s & now 1,000,000s)
Ultra LSI is sometimes used for 1,000,000s.Research has a long history of
involvement with IBM high-performance processor design: from the pioneering 801
RISC processor of the 1980s and ground-breaking work in Very Long Instruction Word
(VLIW) architecture and systems to the first IBM mainframe with a CMOS
microprocessor in 1996 and the current ultra-complex systems such as those use
POWER5™. As the latest processor for IBM’s I Series™ and p Series® systems,
POWER5 uses eight levels of copper wiring and over a quarter billion transistors to take
full advantage of IBM’s leading-edge 130 nm. Silicon-On-Insulator (SOI) technology.
Research continues to make major contributions to IBM’s microprocessors, spanning
the full spectrum of system design, including micro architectures, circuits and circuit
techniques, low power, design methodologies and tools, design verification, and
interaction with technology development. A strong focus centers on developing
advanced high-end systems. Along with industry collaborators, for example, Research is
working with IBM’s Systems and Technology Group in the development of future
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
server processors, as well as the Cell Broadband Engine™ — the next generation of
scalable and power-efficient microprocessors, a multi-core architecture optimized for
computer-intensive rich media applications. IBM places a significant emphasis on
System-on-a-Chip (SoC) design capabilities, in which pre-design components are used
to quickly compose chips with high levels of function. Research contributes to IBM’s
SoC capabilities in both the design and tools areas. These capabilities played an integral
part in the design of Blue Gene/L that became the world’s fastest supercomputer in
2004.
2.4 LEVEL OF INTEGRATION
VLSI (very large-scale integration) is the current level of computer microchip
miniaturization and refers to microchips containing in the hundreds of thousands of
transistors. LSI (large-scale integration) meant microchips containing thousands of
transistors. Earlier, MSI (medium-scale integration) meant a microchip containing
hundreds of transistors and SSI (small-scale integration) meant transistors in the
tens.The MOS Transistor means, Metal-Oxide-Semiconductor Field Effect Transistor
which is the most basic element in the design of large scale integrated circuits(IC).These
transistors are formed as a ``sandwich'' consisting of a semiconductor layer, usually a
slice, or wafer, from a single crystal of silicon; a layer of silicon dioxide (the oxide) and
a layer of metal. These layers are patterned in a manner which permits transistors to be
formed in the semiconductor material.
The MOS technology is considered as one of the very important and promising
technologies in the VLSI design process. The circuit designs are realized based on
pMOS, nMOS, and CMOS and BiCMOS devices. The pMOS devices are based on the
p-channel MOS transistors .Specifically, the PMOS channel is part of a n-type substrate
lying between two heavily doped p+ wells beneath the source and drain electrodes.
Generally speaking, a pMOS transistor is only constructed in consort with an NMOS
transistor. The nMOStechnology and design processes provide an excellent background
for other technologies. In particular, some familiarity with nMOS allows a relatively
easy transition to CMOS technology and design.
The techniques employed in nMOS technology for logic design are similar to
GaAs technology.. Therefore, understanding the basics of nMOS design will help in the
layout of GaAs circuits In addition to VLSI technology, the VLSI design processes also
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
provides a new degree of freedom for designers which helps for the significant
developments. With the rapid advances in technology the the size of the ICs is shrinking
and the integration density is increasing.
The minimum line width of commercial products over the years is shown in the
graph below.
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computer user may not understand what the figures mean; a simpler way to explain is
that the earlier CPUs on the market had a single speed or frequency rating while the
newer models have a rating which refers to more than one CPU.
2.7 VLSI DESIGN FLOW
The VLSI IC circuits design flow is shown in the figure below. The various
level of design are numbered and the gray coloured blocks show processes in the design
flow
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
As we all know VLSI stands for Very large scale integration. Very large scale
integration is the process of creating an integrated circuit by combining thousands of
transistors into a single chip. Now the question comes why we need VLSI. So the
answer is that one of the most characteristics of information service is there increasing
need for very high processing and band width. The other important characteristics is that
the information service tend to become more personalized, which means that the
information processing device must be more intelligent and also be portable to allow
more mobility.
VLSI is mainly classified in two classes.
VLSI back end – VLSI back-end includes Route, place and floor planning.
Back end includes development and fabrication part. It is too costly and time consuming
process. Physical designing and layout refers to back end.
VLSI front end – VLSI Frontend includes designing and testing part. It uses
Verilog and HDL, VHDL .RTL designing, minimizing delay and simulation refers to
Front end.
There are two important steps. VLSI design and design verification. VLSI
design refers to the designing of VLSI circuits and its implementation. Design
verification is use to test the design and verify us that the given designing is working
properly or not
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
Now, we should move towards physical and digital design of VLSI. Both are
very important part of VLSI. Digital design is divided in three steps. First is, second is
structural and third one is design. Behavioural describes the algorithm, structural
describes component and their connections, and physical describes how circuit built.
In standard design cycle physical design comes after the circuit design. Physical design
includes both design and verification and validation of layout. At this step circuit
representation is converted into geometric representation.
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systems. Being the heaviest and biggest component in many portable systems, batteries
have not experienced the similar rapid density growth compared to the electronic
circuits. The main source of power dissipation in these high performance battery-
portable digital systems running on batteries such as note-book computers, cellular
phones and personal digital assistants are gaining prominence. For these systems, low
power consumption is a prime concern, because it directly affects the performance by
having effects on battery longevity. In this situation, low power VLSI design has
assumed great importance as an active and rapidly developing field.
At the circuit design level, considerable potential for power savings exists by
means of proper choice of a logic style for implementing combinational circuits. This is
because all the important parameters governing power dissipation switching
capacitance, transition activity, and Short-circuit currents are strongly influenced by the
chosen logic style.
2.9.2 Logic Style Requirements for Low Power
According to the formula:
Pdyn = V2dd. fclk . ∑nαn .cn + Vdd. ∑niscn1.1
The dynamic power dissipation of a digital CMOS circuit depends on the
supplyvoltageVdd, the clock frequency fclk the node switching activities αn, node
capacitances cn, the node short- circuit currents iscn, and the number of nodes n. A
reduction of each of these parameters results in a reduction of dissipated power.
However, clock frequency fclk reduction is only feasible at the architecture level,
whereas at the circuit level frequency is usually regarded as constant in order to fulfill
some given throughput requirement. All the other parameters are influenced to some
degree by the logic style applied. Thus, some general logic style requirements for low-
power circuit implementation can be stated at this point.
2.9.3 Switched capacitance reduction
Capacitive load, originating from transistor capacitances (gate and diffusion) and
inter- connect wiring, is to be minimized. This is achieved by having as few transistors
and circuit nodes as possible, and by reducing transistor sizes to a minimum. In
particular, the number of (high- capacitive) inter-cell connection and their length (by the
circuit size) should be kept minimal. Another source for capacitance reduction is found
at the layout level. Transistor downsizing is an effective way to reduce switched
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
capacitance of logic gates on noncritical signal paths. For that purpose, a logic style
should be robust against transistor downsizing, i.e., correct functioning of logic gates
with minimal or near minimal transistor sizes must be guaranteed.
2.9.4 Supply voltage reduction
The supply voltage and the choice of logic style are indirectly related through
delay-driven voltage scaling. That is, a logic style providing fast logic gates to speed up
critical signal paths allows a reduction of the supply voltage in order to achieve a given
throughput. For that purpose, a logic style must be robust against supply voltage
reduction
2.10 Design Depiction
VLSI configuration style basically utilizes three areas of
plandepiction,viz.Thebehavioral, the portrayal of the capacity of the plan; the auxiliary,
the depiction of the type of the usage; and the physical, and the depiction of the physical
execution of the outline.There are numerous conceivable portrayals of a circuiting every
depiction, and a reasonable selection of portrayals is critical in instrument designee. The
VLSI designee style is appeared in beneath. Towards the start of a plan, it is vital to
determine the prerequisites without unduly limiting the outline. The question is to
portray the reason for the outline including all angles, for example, the capacities to the
acknowledged, timing imperatives, and power dissemination necessities, and so on.
Depictions in piece level may indicate either information stream, control system, or
both. The individual squares by and large compared to equipment modules. The
utilitarian plan determines the practical connections among subunits or registers. By and
large, a portrayal of the IC in either the practical or the piece chart space comprises both
information yield depiction, and how conduct is to be acknowledged as far as
subordinate modules.
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MOS is turned on or off dependent upon the portal voltage. In CMOS advancement,
both n-channel or N-MOS and the p channel MOS or P-MOS gadget exist. The N-MOS
and P-MOS pictures are represented underneath. By then channel MOS is produced
using poly silicon as the door material and N+ spread to manufacture the source and
exhaust. The p-channel MOS is gathered using poly silicon as the entry way material
and p+ spread to fabricated the source and drain. The pictures for the ground voltage
source is 0 (or) VSS and the supply is 1 (or) VDD.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
third terminal, called the entryway. N-MOS transistor has four techniques for operation
like cut-off, triode, inundation and speed drenching
The MOSFET’s are n-sort redesign mode transistors, organized in a gathered
“pull down Network’ i.e., PDN between the method of reasoning entryway yield and
negative supply voltage which is consistently the ground. A draw up i.e., a “stack” that
can be thought of as a resistor, see underneath is set between the positive supply voltage
and each justification entryway yield. Any method of reasoning passage, including the
logical inverter, would then have the capacity to be realized by illustrating an
arrangement of parallel and also course of action circuits, to such a degree, to the point
that if the desired yield for a particular blend of Boolean data regards is zero (or) false,
the PDN will be dynamic, inferring that no short of what one transistor is allowing a
present route between the negative supply and the yield. This cause a voltage drop over
the stack and in this way a low voltage at the yield, addressing the zero.
Form long ago; these N-MOS circuits were considerably speedier than
equivalent P-MOS and CMOS circuits, which is needed to use P-channel transistors
which are slow. It was likewise less demanding to produce N-MOS tan CMOS, as the
last need to execute p-direct transistors in uncommon n-wells on the p-substrate. The
real disadvantage with N-MOS and most other rationale families is that a DC current
must course through a rationale door notwithstanding when the yield is in a relentless
state low in account of N-MOS. This implies static power scattering, i.e., control deplete
notwithstanding when the circuit isn’t exchanging.
2.12.2 P-MOS Logic
P-type metal oxide semiconductor rationale utilizes P-channel metal oxide
semiconductor field impact transistors i.e., MOSFET’s to execute rationale doors and
other advanced circuits. P-MOS transistors work by making a reversal layer in an N-
type transistor body. This reversal layer, called the p-channel, can lead openings
between p-type “source” and “deplete” terminals. The p-channel is made by applying a
voltage to the third terminal, called the door. Like typical MOSFET’s, P-MOS
transistors has four methods of operation which are cut-off, triode, immersion i.e.,
dynamic and speed immersion.
While P-MOS rationale is anything but difficult to outline and produce a
MOSFET can be made to work as a resistor, so the entire circuit can be made with P-
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
MOS FETs, it has a few deficiencies too. The most exceedingly terrible issue is that
there is an immediate current i.e., DC through a P-MOS rationale entryway when the
PUN i.e., “Pull Up Network’ is dynamic, that is, at whatever point the yield is high,
which prompts static power scattering notwithstanding when the circuit sits out of gear.
The P-MOS circuits are ease back to progress from high to low. When there is a
change in the transition from low to high, the transistors gives low protection and the
capacitive charge at the yield collects rapidly like charging a capacitor at the output with
a low protection. Be that as it may, the protection between the yield and negative supply
rail is substantially more noteworthy, so the high-to low change takes longer like the
release of a capacitor through a high protection. Utilizing a resistor of lower esteem will
accelerate the procedure yet, in addition, builds static power scattering.
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3 SOFTWARE DESCRIPTIONS
3.1 Tools Used
The tools used in the thesis are as follows:
Simulation Software:
Cadence EDA Tool
3.1.1 Boolean Algebra
Boolean algebra is the field of mathematics that deals exclusively with the set of
values consisting of True and False [8]. It is the mathematical foundation for all digital
electronics, and a review of this subject is absolutely necessary to understand the design
of the adder. In addition, we will see how Boolean algebra provides useful abstractions
for the construction of virtually any type of digital circuit.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
Table:3.1.2
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The XOR gate, also called the “exclusive-OR gate”,is a modified version of the
OR gate, in which the output is 1 if A or B is 1, but 0 if both A and B are 1. Its truth
table is given below, and at first glance it does not seem much more complex than any
of the gates listed above; however, it is deceptively challenging to actually implement
using discrete transistors. As an exercise, let us apply some of the principles of Boolean
algebra to implement the XOR gate as a combination of simpler logical opera tions.
A B A㊉B
0 0 0
0 1 1
1 0 1
1 1 0
Table 3.1.4
A ㊉B = A • B + A • B.
By the Complementation and Identity over OR Laws (see Appendix II), I can also
add the following terms without changing the output:
A ㊉B = B • A + A • B + A • A + B • B.
OR)
=(A + B) • (B+ A)(Distributive over AND)
=(A + B) • (A • B)(De Morgan’s Law)
This result is something that can be easily implemented. It consists of an OR
operation, a NAND operation, and then performs an AND on the two results. Hence, the
XOR gate can be implemented in the following way:
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Fig3.1.5: Implementation of the NAND gate using two n-type MOSFET’s. This circuit
has inputs A and B, and an output A- B.
So far in this section, I have discussed how logical operations can be used to
construct digital components, but how can transistors be used to implement these logical
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
operations in the first place? For example, consider the NAND gate, which has an
output of 0 if both of its inputs are 1, and an output of 1 otherwise (refer to Table I for
the full truth table). This function can be created by attaching two n-type MOSFET’s in
series, with one transistor’s source terminal attached to the other’s drain terminal (see
Figure 5). The output of such a circuit would be 0 if both A and B were 1, because both
transistors would be allowing current to pass through directly to ground. If only one (or
neither) transistor were on, then the output would have to be high.
There were some design choices made in Figure 5. For one, the values of the
voltage source and the pull-up resistor are arbitrary, depending on what output current is
desired. Also, Figure 5 does not represent the only possible implementation of the
NAND gate. There are many possible variations, some of which may be more elegant
than the one pictured above. However, it is the opinion of this author that Figure 5
represents the simplest implementation of the NAND gate that is to be constructed using
discrete components; were I to be designing a true integrated circuit, I might consider
another method.
This NAND gate implementation will be used for the construction of the adder, as
will many other types of logic gates. For a complete list of all logic gates used, and their
transistor- level implementations, refer to Appendix I.
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ordered bit. Continue by adding this sum to the product of 22 and the magnitude of the
next-lowest ordered bit, and so on until you reach the next-to-highest ordered bit. Using
our example string 00101111, this corresponds to:
3.(1 • 20) + (1 • 21) + (1 • 22) + (1 • 23) + (0 • 24) + (1 • 25) + (0 • 26) + (0 • 27) = 47.
4 The conversion from integer to binary is slightly more involved than binary-to-integer,
but is still relatively straightforward. Take an example integer, say 107. First, find the
largest power of two that is less than or equal to that integer. Recall that 2 6 is 64, but 27
is 128, so 6 is the highest power of 2. This tells us we need 8 bits to represent this
number: 7 to represent magnitude (not 6: remember the 0th order is included), and one
to represent sign. 107 is positive, so the sign bit (the highest-ordered bit) will be zero.
The next-highest ordered bit represents the factor of 26, which is less than 107, so it will
be a 1. Then, take 107 - 64 to get 43. Now, we again find the highest power of two less
than or equal to 43. In this case, we remember that 25 is 32, so the the bit corresponding
to 25 will also be a 1. Repeat this process again: 43 32 is 11. 23 is 8, but 24 is 16.
Therefore, the bit corresponding to 24 will be 0, and the bit corresponding to 23 will be a
one. Continuing on: 11 - 8 is 3, so the 21 bit will be 1 and the 22 bit will be 0. Finally 3 -
2 is 1, so the lowest-ordered bit will be a 1. This results in:
5 107 = (1 • 26) + (1 • 25) + (0 • 24) + (1 • 23) + (0 • 22) + (1 • 21) + (1 • 20) = 01101011.
6 Note that in our previous examples, both integers were positive. If the integer is
negative (or we know that the resulting integer should be negative), the conversion is a
little harder. In 2's complement, the most-significant bit determines the sign of the
integer. If it is a 0, the corresponding integer is positive; if it is a 1, the integer is
negative. However, under the 2's complement method we cannot simply flip the left-
most bit and expect the sign to change while leaving the magnitude the same (the
Signed Magnitude method actually does do this). Instead, for 2's complement, when
confronted with a negative bit string like 11101011, we must do the following
procedure: invert all of the bits, and then add 1 to it. Flipping the bits results in
00010100. Adding 1 to this, we get 00010101. Now, we can convert this to integer
using the same method outlined above: 00010101 = 21, but we have already determined
7 that our integer is negative, so 11101011 is equivalent to -21.
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G G
A B in SUM out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Gout are also 1. From these rules a truth table for the adder can be produced, which is
given on Table 4.
Table 4 provides the basis from which a 1-bit adder can be constructed. Generally
speaking, however, merely adding one bit to another bit is not that interesting. Much
more interesting would be creating a circuit that could compute the above example,
which contained two 8-bit inputs. This is entirely possible to do, since the operation is
exactly the same for each pair of bits. All that we need to do is design multiple 1-bit
adders from Table 4, and connect them in series such that Gout from the first pair of bits
is Gin for the second pair, and so on. This serialization of 1-bit adders through the carry-
out is the defining feature of the “ripple-carry” adder.
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=
Cin㊉(A ㊉B)(Definition of XOR)
This last equation is something that can be easily implemented using two XOR
gates, which w
C
out = A • B • Cin+ A • B • C+ A • B • Cin+ A • B • Cin
= C i n • (A • B + A • B) + (A • B) • (Cin+ Cin) (Distributive over OR)
Complementation Law)
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This result for Cout is simple enough to implement, especially since I already have
an XOR gate that compares A and B for the sum. I can reuse the output for that gate to
reduce the number of total gates in the adder like so:
Fig: 3.2.2 The complete full-bit adder. Note that the multi-colored
wires indicate that there is no junction where they cross.
Figure 7 represents the complete 1-bit adder, which I can implement and duplicate
four times to make a 4-bit, ripple carry adder.
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Next, consider the case of adding two negatives together to get a positive. Try
adding the values 1001 and 1010:
1001 (-7)
+ 1010 (-6)
0011 (3?)
In this case, it is the final carry-out bit that must be a 1, because both most-
significant bits of the inputs were 1, by definition. Also, the penultimate carry-out must
be a 0, otherwise the final answer would be negative.
From these two cases, a solution for overflow detection can be derived. We have
shown that if either the last carry-out bit or the next-to-last carry-out bit are 1, but not
both and not neither, then overflow has occurred. Therefore, the solution is to XOR the
last and next- to-last carry-outs. If the result is 1, then there has been overflow. If it is 0,
the sum is valid. This XOR gate is visualized in its appropriate place in Figure 9, and
will be implemented during the construction of the adder.
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Table:3.3.1
S=AXORB ;------------------------------------------(1)
Cout=AANDB ; --------------------------------------------(2)
Fig3.3.2schematicdiagramoffulladder
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Notices that both propagate and generate signals depend only on the input bits and thus
will be valid after one gate delay.
The new expressions for the output sum and the carryout are given by
Si= Pi⊕ Ci-1
These equations show that a carry signal will be generated in two cases:
1) if both bits Aiand Biare 1
These expressions show that C2, C3 and C4 do not depend on its previous carry-in.
Therefore C4 does not need to wait for C3 to propagate. As soon as C0 is computed, C4
can reach steady state. The same is also true for C2 and C3
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This is a two level circuit. In CMOS however the delay of the function is non linearly
dependent on its fan in. Therefore large fan in gates are not practical.
Carry look-ahead adder’s structure can be divided into three parts: the
propagate/generate generator Fig.1, the sum generator Fig. 2 and the carry generator
Fig.
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4 SOFTWARE DESCRIPTION
4.1 Introduction
The intentions for this manual is to serve as an introduction to the Cadence de-
sign environment and describe the methodology used when designing integrated
circuits.
The department is not giving courses in Cadence but in integrated circuit design
so only the minimum knowledge, needed to run the laboratories, of Cadence can be
gained from this manual. Also this manual describes the environment currently at the
department which is Cadence version 4.45 in conjunction witch a Design Kit from AMS
(Austria Mikro System International AG) which contains a set of rules and designs for a
0.35 µm CMOS process.
For a more thorough understanding of Cadence the extensive on line manual set
is recommended. These are accessed from any of the tools by pressing the help button.
More information about the topics in the first two chapters can be found in the
manuals Design Framework II Help and Cadence Application Infrastructure User
Guide.
The Cadence tool kit consists of several programs for different applications such
as schematic drawing, layout, verification, and simulation. These applications can be
used on various computer platforms. The open architecture also allows for integration of
tools from other vendors or of own design. The integration of all this tools is done by a
program called Design Framework II (DFW).
The DFW-application is the cornerstone in the Cadence environment. It provides
a common user interface and a common data base to the tools used. This makes it
possible to switch between different applications without having to convert the data
base.
In a terminal window, sort csh at the summon provoke to conjure the C shell.
Csh
Source cshrc
To check that the way to the product is legitimately set in the cshrc document, sort
the beneath summon in the terminal window and enter:
> Which virtuoso
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DESIGN AND IMPLEMENTATION OF RIPPLE CARRY ADDER IN 180NM CMOS TECHNOLOGY
It gives the entire way of IC617 instrument Installation.
>which apparition
It gives the total way of MMSIM101 apparatus Installation.
>which assura
It gives the total way of Assura410 apparatus Installation.
4.5 Starting of Cadence
Utilize the introduced database to do your work and the means are as per the
following:
Change to course registry bh entering this charge
>cd~/Database/cadence_analog_613
You will begin the rhythm outline structure II condition from this registry since
it contains CSD.lib, which is the nearby introduction record. The library look ways are
characterized in this record.
The cadence_analog_613 registry contains arrangements organizer and
furthermore work envelope. Inside work envelope you can make new cell/alterations of
the phone locally without influencing your source cell show inside arrangements
catalog.
/solution - Contains an area copy of all the workplace experiments as well as check
circuit for simulation.
/libs.cdb - Contains a technology library for the planning (gpdk 180nm).
/models - Contains spectra models of elements for simulation in gpdk180nm
technology.
/stream - Contains layer map file for GDSII format
/pv- Containing the Assura and Diva verification files
/tech files - contains ASCII versions of OA22tech files
/dig_source - Contains Verilog codes for SAR register and clock/cds. lib -File
containing pointer to the Cadence OA22 formatting file.
/cds.lib - File containing pointer to the cadence OA22 initialisation file.
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/hdl.var - file defines the work library for AMS simulation /docs - manual and user
manual for gpdk180nm technology.
/docs - Reference manual and user manual for gpdk180nm technology.
In the same terminal window, enter:
Virtuoso&
The virtuoso or Command Interpreter Window (CIW) shows up at the base of the
screen
If the "What's New..." window appears close it with the File Close command.
Keep opened CIW window.
2. Try not to alter the Library way document and the one above may be not quite the
same as the way appeared in your frame.
3. Snap OK when done the above settings. A clear schematic window for the inverter
configuration shows up.
On the off chance that you put a segment with a wrong parameter esteems,
utilize the Edit Properties Objects charge the parameters.
Utilize the Edit Move order on the off chance that you put parts in the wrong
area.
5 SIMULATION
The reproduction device is begun straightforwardly from the schematic proof
reader and all the fundamental net records portraying the plan will be made. A
reproduction is normally preformed in a test seat, which is likewise a schematic, with a
genuine outline included as a case. The test seat additionally incorporates flag source
and power supply. By using parameters for the properties of the parts utilized it is
conceivable to rapidly breakdown the outline for an extensive variety of factors.
The test systems keep running from inside Affirma Analog Circuit Design
Environment which are an instrument that handles the interface between the client and
the test system. The present form of Cadence utilized at the office (4.45) utilizes the
AffirmaSpecter Circuit Simulator. The test system offers an extensive variety of
investigations (DC, recurrence clear, transient, clamor, and so on.) and be introduced
graphically and be spared.
The outcomes (voltage levels, streams, clamor, and so forth.) can be
bolstered into a mini-computer which can exhibit different parameter of the investigated
circuit – postpone time, rise time, slew rate, stage edge, and numerous other fascinating
properties. It is likewise conceivable to set up the logarithmic articulation of in or yield
flag which can be pointed as an element of some other variable.
In this segment, we will run the reenactment for Inverter and plot the transient ,
DC attributes and we will do Parametric Analysis after the underlying reenactment.
6. RESULTS
1. Conventional full adder designed by using cadence