library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.std_logic_unsigned.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity CONTADOR_81HZ is

Port ( CLK_50MHZ : in STD_LOGIC;

PARE : in STD_LOGIC;

BORRAR : in STD_LOGIC;

CONTADOR : out STD_LOGIC_VECTOR (7 downto 0));

end CONTADOR_81HZ;

architecture Behavioral of CONTADOR_81HZ is

signal CLK_1HZ: std_logic;

begin

PROCESS (CLK_50MHZ,PARE)

Variable conta: natural range 0 to 25000000:= 25000000;

variable aux: std_logic:='0';

BEGIN

IF RISING_EDGE(CLK_50MHZ) THEN --IF CLK.50MHZ EVENT AND CLK.50MHZ='1' THEN

 IF CONTA=0 THEN

CONTA:= 25000000;

aux:= not aux;

ELSE

IF PARE='0' THEN

CONTA:= CONTA-1;

ELSE

CONTA:=CONTA;

END IF;

END IF;

END IF;

CLK_1HZ<=aux;

END PROCESS;

process (clk_1hz)

variable auxiliar: std_logic_vector(7 downto 0):="00000000";

begin

if RISING_EDGE(CLK_1HZ) then

if BORRAR='1' then

AUXILIAR:="00000000";

else

AUXILIAR := AUXILIAR+1;

end if;

end if;

CONTADOR<=AUXILIAR;

end process;

end Behavioral;