41

CHAPTER 3

PERFORMANCE EVALUATION STUDY ON CUK

CONVERTER DESIGN

3.1 INTRODUCTION

The extensive use of DC power supplies inside most of electrical

and electronic appliances leads to an increasing demand for power supplies
that draw current with low harmonic content and also have power factor close
to unity. DC power supplies are extensively used in computers, audio sets,
televisions and others. The presence of nonlinear loads results in low power
factor operation of the power system. The basic block in many power
electronic converters are uncontrolled diode bridge rectifiers with capacitive
filter. Due to the non-linear nature of bridge rectifiers, non-sinusoidal current
is drawn from the utility and harmonics are injected into the utility lines. The
bridge rectifiers contribute to high THD, low PF and low efficiency to the
power system. These harmonic currents cause several problems such as
voltage distortion, heating and noises which result in reduced efficiency of the
power system. Due to this fact, there is a need for power supplies that draw
current with low harmonic content and also have power factor close to unity.

The AC mains utility supply ideally is supposed to be free from

high voltage spikes and current harmonics. Discontinuous input current that
exists on the AC mains due to the non-linearity of the rectification process
should be shaped to follow the sinusoidal form of the input voltage. The
conventional input stage for single phase power supplies operates by
 42

rectifying the ac line voltage and filtering with large electrolytic capacitors.
This process results in a distorted input current waveform with large harmonic
content. As a result, the power factor becomes very poor (around 0.6). The
reduction of input current harmonics and operation at high power factor (close
to unity) are important requirements for good power supplies. Power factor
correction techniques are of two types: passive and active power factor
correction. While, passive power factor correction techniques are the best
choice for low power, cost sensitive applications, the active power factor
correction techniques are used in majority of the applications due to their
superior performance.

The isolated DC-DC converters convert a DC input power source to

a DC output power while maintaining isolation between the input and the
output, generally allowing differences in the input-output ground potentials in
the range of hundreds or thousands of volts. They can be an exception to the
definition of DC-DC converters, in that; their output voltage is often (but not
always) the same as the input voltage. The various topologies of the DC to
DC converter can generate voltages higher, lower, higher and lower or
negative of the input voltage namely:

Buck

Boost

Buck boost

Cuk

Sepic
 43

Among the different topologies, the conventional boost converter is

the most widely used topology for power factor correction applications. It
consists of a front-end full-bridge diode rectifier followed by the boost
converter as shown in Figure 3.1. The diode bridge rectifier is used to rectify
the AC input voltage to DC, which is then given to the boost section. During
ON-time of the switch, the current flows through two rectifier diodes (D1 and
D3) and the power switch (QB). Similarly during OFF-time of the switch, the
current flows through the other two rectifier diodes (D2 and D4) and the output
diode DB. Thus it results in significant conduction losses in three
semiconductor devices which reduce the converter efficiency. This approach
is good for a low to medium power range applications. For higher power
levels, the diode bridge becomes an important part of the application and it is
necessary to deal with the problem of heat dissipation in limited surface area.

Figure 3.1 Conventional PFC boost converter

The bridgeless PFC Boost Converter is shown in Figure 3.2. From

a functional point of view, the circuit is similar to the common boost
converter. The conventional PFC boost converter topology shown in
Figure 3.1, includes three semiconductor voltage drops in the current flow
path (i.e. two bridge diodes and one semiconductor switch QB) whereas, in the
 44

bridgeless power factor correction configuration, current flows through only

one diode and the return path is provided by a power MOSFET.

When the AC input voltage goes positive, the gate of S1 is driven

high and the current flows from input to load resistor through the inductor LB1
which stores the energy. When S1 turns off, energy stored in the inductor gets
discharged and the current flows through diode D1 to the load and returns
back via the body diode of switch S2. During the negative half cycle, switch
S2 turns on, current flows through the inductor and stores energy. When S2
turns off, energy stored in the inductor is released, the current flows through
D2 to load and return back to the mains through the body diode of switch S1.

Thus, in each half line cycle, one of the MOSFET operates as an

active switch and the other one operates as a diode. The difference between
the bridgeless PFC and conventional PFC is that in bridgeless PFC converter
the inductor current flows through only two semiconductor devices, but in
conventional PFC circuit the inductor current flows through three
semiconductor devices.

Figure 3.2 Bridgeless PFC boost converter

 45

The two slow diodes of the conventional PFC converter are

replaced by one MOSFET body diode in bridgeless PFC converter. It results
in reduced conduction losses in bridgeless PFC boost converter. Thus it helps
to improvement in efficiency of bridgeless PFC boost converter. The
bridgeless PFC converter also reduces the total component count as compared
to a conventional PFC converter. The disadvantage of this topology is the
floating input line with respect to the PFC stage ground, which makes it
impossible to sense the input voltage without a low frequency transformer or
an optical coupler. Also complex circuitry is needed to sense the current in the
MOSFET and diode paths separately, since the current path does not share the
same ground during each half-line cycle.

3.2 AN OVERVIEW OF CUK CONVERTER

Power supplies with active power factor correction techniques are

becoming necessary for many types of electronic equipment to meet harmonic
regulations and standards, such as the IEC 61000-3-2. Most of the PFC
rectifiers utilize a boost converter at their front end as shown in Figure 3.2.
However, a conventional PFC scheme has lower efficiency due to significant
losses in the diode bridge. The current flows through two rectifier bridge
diodes and the power switch (QB) during the switch ON-time and through two
rectifier bridge diodes and the output diode (DB) during the switch OFF-time.
Thus, during each switching cycle, the current flows through three power
semiconductor devices. As a result, a significant conduction loss, caused by
the forward voltage drop across the bridge diode, would degrade the
converter’s efficiency, especially at a low line input voltage.

To overcome these drawbacks, several bridgeless topologies, which

are suitable for step-up/step-down applications have been discussed by (Chen
and Dai, 2013). A bridgeless buck PFC rectifier was proposed by (Jang &
 46

Jovanovic 2011) for step-down applications. However, the input line current
cannot follow the input voltage around the zero crossings of the input line
voltage; besides, the output to input voltage ratio is limited to half. Also, buck
PFC converter results in an increased Total Harmonic Distortion (THD) and a
reduction in power factor (Jang & Jovanovic 2011).

The bridgeless PFC boost converter is presented by (Huber et al

2008). The main drawback of this converter is that during a negative half
cycle, the output ground is pulsating relative to the AC source with a high
frequency and amplitude equal to the output voltage. These output voltages
result in a significantly increased common mode noises which affects the
system stability. The buck-boost converter (Cuk & Middlebrook 2008) causes
very high voltage stresses on its two switching devices several times that of
the output DC voltage. A bridgeless PFC rectifier based on the SEPIC
topology is presented. In their work of Sabzali et al (2011) found that similar
to the boost converter, the SEPIC converter has the disadvantage of
discontinuous output current resulting in a relatively high output ripple. In
turn, the thermal and current stress on the power semiconductor devices is
increased.

The cuk converter offer several advantages in PFC applications,

such as easy implementation of transformer isolation, natural protection
against inrush current occurring at start or overload condition, lower input
current ripple and Electro-Magnetic Interference (EMI) associated with the
DCM topology (Fardoun et al 2012). Moreover, unlike the SEPIC converter,
the cuk converter has both continuous input and output currents with a low
current ripple. Thus, for applications, which require low current ripple at the
input and output ports of the converter, the cuk converter seems to be a
suitable among the different converter topologies.
 47

3.2.1 Bridgeless Cuk Converter for PFC Applications

Based on the potential efficiency of the cuk converter, Fardoun et al

(2012) have proposed a new bridgeless single-phase AC–DC PFC based on
cuk topology. The absence of an input diode bridge and the presence of only
two semiconductor switches in the current flowing path during each interval
of the switching cycle result in less conduction losses and an improved
thermal management compared to the conventional cuk PFC rectifier.

These topologies are designed to work in DCM to achieve almost a

unity power factor and low THD of the input current. The DCM operation
gives additional advantages, such as zero-current turn-ON in the power
switches, zero-current turn-OFF in the output diode and a simple control
circuitry. The three bridgeless PFC cuk converters are shown in Figure 3.3.
The proposed topologies are developed by connecting two DC–DC cuk
converters, one for each half line period (T/2) of the input voltage. The
topology illustrated in Figure 3.3 (a) is discussed in (Sabzali et al 2011) as a
new converter topology but it is not analyzed.

(a)

Figure 3.3 (Continued)

 48

(b)

(c)

Figure 3.3 Conventional Bridgeless Cuk PFC rectifiers (a) Type 1 (b)
Type 2 (c) Type 3
 49

It is observed that from Figure 3.3(a) to Figure 3.3(c), there are one
or two semiconductor(s) in the current flowing path. Hence, the current
stresses in the active and passive switches are further reduced and the circuit
efficiency is improved compared to the conventional cuk rectifier. Figure 3.3
(a) and (c) illustrates that only one rail of the output voltage bus is always
connected to the input AC line through the slow recovery diodes Dp and Dn or
directly as in the case of the topology shown in Figure 3.3 (b). Thus, the
proposed topologies do not suffer from the high common-mode EMI noise
emission problem and have a common mode EMI rejection performance
similar to that of conventional PFC topologies.

The conventional bridgeless PFC cuk converters shown in

Figure 3.3 (a) to (c) utilizes two power switches (Q1 and Q2) and it is driven
by the same control signal, which drastically simplifies the control circuitry.
All these three bridgeless PFC cuk converter topologies utilize one additional
inductor compared to the conventional cuk converter, which increase the
system size and cost. Among the three bridgeless PFC cuk converter
presented earlier, the Type-3 cuk converter is taken for comparison with the
proposed PFC cuk converter.

3.2.2 Conventional Bridgeless PFC Cuk Type-3 Converter

Power supplies with active power factor correction techniques are

becoming necessary for many types of electronic equipment to meet harmonic
regulations and standards, such as the IEC 61000-3-2. The conventional
bridgeless PFC cuk converter shown in Figure 3.3(c) is formed by connecting
two DC–DC cuk converters, one for each half-line period (T/2) of the input
voltage. The conventional bridgeless type-3 cuk converter during positive and
negative half cycle of the AC input voltage shown in Figure 3.4 (a) and (b)
which are considered for study.
 50

As shown in Figure 3.4 (a), during the positive half cycle of the
input voltage, the devices in the first DC–DC cuk converter circuit such as
input inductor L1, power switch (Q1), energy transfer capacitor (C1), output
inductor (L01) and output diode (D01) are active through input diode Dp, which
connects the input AC source to the output. During the negative half cycle of
the input voltage, the devices in the second DC–DC cuk circuit such as input
inductor L2, power switch (Q2), energy transfer capacitor (C2), output inductor
(L02) and output diode (D02) are active through input diode Dn, which
connects the input AC source to the output.

As a result, the average voltage across capacitor C1 during the line

cycle can be expressed as equation given in Equation (3.1):

T
vac t V0 , 0 t
v C1 t 2 (3.1)
T
V0 , t T
2

Due to the symmetry of the circuit, it is sufficient to analyze the

circuit for the positive half cycle of the input voltage. Moreover, the operation
of the conventional PFC Type-3 cuk converter involves three inductors which
are operating in DCM. By operating the conventional cuk converter in DCM,
several advantages can be obtained.

The advantages includes near-unity power factor, the power

switches are turned ON at zero current and the output diodes (D01 and D02) are
turned OFF at zero current. Thus, the losses due to the turn-ON switching and
the reverse recovery of the output diodes are considerably reduced.
 51

(a) Type-3 converter during positive half cycle of the AC input voltage

(b) Type-3 converter during negative half cycle of the AC input voltage

Figure 3.4 Type 3 cuk converters

 52

The circuit operation of the conventional PFC Type-3 cuk converter

in DCM can be divided into three distinct operating stages during one
switching period Ts.

Stage 1: This stage starts when the power switch Q1 is turned ON

and the input diode Dp is forward biased by the inductor current iL1. As a
result, the input diode Dn is reverse biased by the input voltage. The output
diode D01 is reverse biased by the reverse voltage (Vac + V0), while the output
diode D02 is reverse biased by the output voltageV0. In this stage, the currents
through the inductors L1 and L01 increases linearly with the input voltage,
while the current through L02 is zero due to the constant voltage across C2.
The current flows through the inductors of L1 and L01 during this stage are
given in Equation (3.2)

di Ln vac
, n 1, 01 (3.2)
dt Ln

Accordingly, the peak current through the active switch Q1 is

expressed as in Equation (3.3)

Vm
IQ1, pk D1Ts (3.3)
Le

where, Vm is the peak amplitude of the input voltage Vac, D1 is the switch duty
cycle of the switch, and Le is the net inductance obtained by the parallel
combination of inductors L1 and L01.

Stage 2: This stage starts, when the power switch Q1 is turned OFF
and the output diode D01 is turned ON simultaneously providing a path for the
inductor currents iL1 and iL01. The input diode Dp remains conducting to
provide a current path for iL1. The output diode D02 remains reverse biased
during this interval. This interval ends when output diode current reaches
 53

zero and becomes reverse biased. The output diode D01 is switched OFF
at zero current. The current flows through the inductors of L1 and L01 during
this stage can be represented as given in Equation (3.4)

diLn v0
, n 1, 01 (3.4)
dt Ln

Stage 3: During this interval, only the input diode Dp conducts to

provide a current path for iL1. In this stage, the inductors behave as constant
current sources. Hence, the voltages across the three inductors are zero. The
energy transfer capacitor C1 is being charged by the inductor current iL1. This
period ends when power switch Q1 is turned ON. By applying inductor volt
across L1 and L01, the normalized length of the second stage period can be
expressed as in Equation (3.5)

D1
D2 sin t (3.5)
M

where, is the line angular frequency and M is the voltage conversion ratio

In all the above three stages, the input diode Dp continuously

conducts throughout the entire switching period and the average voltage
across C2 is equal to the output voltageV0. As a result, a negligible AC current
will flows through the capacitor C2 and the output inductor L02. Therefore, the
current through the input inductor L2 during the positive half cycle of the input
voltage is equal to the negative current through the body diode of the power
switch Q2. It should be noted that the body diode of the inactive switch Q2
always conducts current during the positive half cycle of the input voltage. This
is due to the low impedance of the input inductors (L1 and L2) at the line
frequency. Therefore, the input diode Dp and body diode Q2 appears in parallel
 54

configuration to share the return current. A large portion of the return current will
pass through the diode that has a voltage drop. Thus, it degrades the efficiency
of the converter due to the input diode and body-diode conduction.

3.2.3 Evaluation study of the Conventional PFC Cuk Converters

From the survey, of the converter topologies, a comparison between

the conventional and Bridgeless (BL) cuk converter topologies in DCM mode
are accordingly furnished in Table 3.1. From the table, it is found that Type-2
cuk converter has the lowest number of semiconductor devices in the current
conduction path. However, it has two disadvantages: floating switch and a
step-up voltage gain greater than 2 as discussed by (Fardoun 2012). The
floating switch requires a more complex driver circuitry and it leads to higher
electromagnetic emissions. The gain range is limited by the blocking voltage
of during the positive half cycle of the input voltage similar to the
topology discussed by (Ismail 2009).

This disadvantage can be minimized by implementing input/output

galvanic isolation; however, components with higher blocking voltage
capability are needed. Type-1 also has the advantage of a lower component
count, but a higher current peak. In Type-3 cuk converter, it has a higher
component count, but lower stresses. The major limitation of the Type-3
circuit is the higher number of semiconductor devices which results in
switching losses. Based on the motivation of the above mentioned cuk
converter circuits, the present research work focus on a novel cuk converter
design which overcomes the limitation of the above mentioned circuits. Table
3.2 shows the device utility comparison of the conventional and the proposed
model. It is clearly observed from the table that the proposed converter design
utilizes lesser number of power utility devices. Especially, the number of
switches used in the proposed converter design is just one, where as in the
conventional converters, more than one switches are used.
 55

Table 3.1 Comparison between conventional and bridgeless Cuk

converters in DCM Mode

Proposed
Item Type-1 Type-2 Type-3 Cuk
Converter
2 slow + 3 2 slow + 2
Diode 2 fast 2 fast
fast fast
2 (with
unidirectional 1
Switch 2 2
current Bidirectional
capabilities)
1 slow diode,
Current conduction and 1 switch 1 body diode 1 slow diode
1 Switch
path when SW on with series and 1 switch and 1 switch
diode
2 diodes 2 diodes
Current conduction
(1 slow and 1 1 fast diode (1 slow and 1 2 fast diodes
path when SW off
fast) fast)
Current conduction
1 slow diode ----- 1 slow diode ----
path in DCM
Component count 11 11 13 9
Number of capacitors 3 4 3 4
Equivalent inductance,
L1 // L 2 // L 0 L1 // L 01 // L 02 L1 // L 01 // L02 L1 // L 01 // L02
Le

Minimum conduction
1 1 1 1
parameter, 2 2 2 2
2 M 1 2 M 2 2 M 1 2 M 2
K e crit min

Switch duty-cycle,
M 2K e
D1

Only step-up Step- Step-

Gain range Step-up/down
(M>2) up/down up/down
Integrated magnetic One core for One core for 3 2 core for 4 One core for
core 3 inductors inductors inductors 3 inductors
 56

Table 3.2 Device utility comparison of the conventional and proposed

converter

Number of Devices ½
Suitabi
Configuration Period
Sw D L C Total lity
Cond.
BL-Buck (Jang & Jovanovi, 2011) 2 4 2 2 10 5 No
BL-Boost (Huber et al 2008) 2 2 1 1 6 4 No
BL-Boost (Fardoun et al 2012) 2 2 1 2 7 7 No
BL-Buck-Boost (Wei et al 2008) 3 4 1 3 11 8 Yes
BL-Cuk T-1 (Fardoun et al 2012
2 3 3 3 11 7 Yes
and Fardoun et al 2010)
BL-Cuk T-2 (Fardoun et al 2012
2 2 3 4 11 11 Yes
and Fardoun et al 2010)
BL-Cuk T-3 (Fardoun et al 2012
2 4 4 3 13 7 Yes
and Fardoun et al 2010)
BL-Cuk
2 3 3 2 10 8 Yes
(Mahdavi & Farzaneh-Fard 2012)
BL-SEPIC
2 3 1 3 9 7 Yes
(Sabzali et al 2011)
BL-SEPIC
2 3 2 2 9 7 Yes
(Mahdavi & Farzanehfard 2010)
Buck-Boost
2 4 2 1 9 5 Yes
Vashist & Singh (2014)
Proposed PFC Cuk Converter 1 2 3 4 10 5 Yes

This would result in lesser switching losses which in turn increases

the efficiency of the proposed cuk converter. From the Table 3.1 and 3.2, It is
found that the conventional PFC converters utilize more number of switching
devices passive components which results higher power losses. Hence, in this
thesis a novel PFC cuk converter has been proposed for power factor
correction at the AC input side.
 57

3.3 PROPOSED PFC CUK CONVERTER DESIGN

Figure 3.5 shows the circuitry of the proposed bridgeless PFC cuk
converter design. The performance of the proposed topology is evaluated
based on component count, efficiency, THD and complexity. The proposed
converter consists of single input stage for both the positive and negative half
cycles of the input AC voltage. The converter has inherent high power factor
when operating in DCM because the line current is proportional to the input
voltage.

Figure 3.5 Proposed PFC cuk converter model

The proposed converter consists of one power switch, three

inductors (L, L01 and L02), two diodes (D1 and D2) and two capacitors (C01 and
C02). It is clearly observed that, the proposed converter model utilizes very
lesser devices when compared with the conventional Type-3 cuk converter
model. Thus, the proposed converter model is cost effective with reduced
switching losses when compared to conventional cuk converter.
 58

3.3.1 Operating Modes of the Proposed Converter

The operating modes of the proposed bridgeless PFC cuk converter

are divided into four modes such as Mode 1, Mode 2, Mode 3 and Mode 4.
The proposed PFC cuk converter consists of single input stage for both the
positive and negative half cycles of the input voltage. On the other hand, it
has two output stages connected to the switched input voltage: each stage
operates during one half cycles. The operating modes during the positive half
cycle are Mode 1 and Mode 2 and similarly for negative half cycle it is Mode
3 and Mode 4.

Mode 1: This mode is initiated in the positive half cycle of the AC

supply when the Switch ‘S’ is in ON condition. The inductance L is charged
and the ground is attained through the drain and source of the switch ‘S’ as
shown in Figure 3.6. The Switch ‘S’ represents the bidirectional switch with
drain ‘Dp’ and source ‘Sp’ during the positive cycle. Alternatively, the switch
conducts with drain ‘Dn’ and Source ‘Sn’ during the negative cycle. During the
circulating path, ‘CL1 – S – C01 – L01 – CL1’ generated between the first turn-
ON of the switch and the next turn-ON condition, the inductance L01 is
charged by the discharge of the inductance ‘L’ as shown in Figure 3.7(a).

Dp Sn

Sp Dn

Figure 3.6 Bidirectional switch ‘S’

 59

Mode 2: This mode occurs during positive cycle of the AC supply

when the switch ‘S’ is in OFF condition. The main inductance L is charged
and the energy is stored in the capacitor CL1 as the voltage. Then, the current
flows through the diode D1 is grounded via the Vac neutral. Similarly, during
the circulating path, ‘L01 – D1 – C01 – L01’ the inductance ‘L01’ is charged.
Then, the discharge of ‘L01’ is completed through the load RL with the current
flow along, ‘C01 – C02 – RL – C01’ as shown in Figure. 3.7(b). During the
connection with load, the capacitors C01 and C02 will be in series.

(a) Mode 1 (b) Mode 2

(c) Mode 3 (d) Mode 4

Figure 3.7 Modes of operation of the proposed bridgeless cuk converter

 60

Mode 3: This mode is initiated in the negative half cycle of the AC

supply and when the switch ‘S’ is in turn-on condition. The current flows
through the bidirectional switch ‘Dn’ and ‘Sn’. It charges the main inductance
‘L’ and gets grounded through the Vac neutral. During the circulating path,
‘ ’ the inductance ‘L02’ is charged by the discharge
of the inductance ‘L’ as illustrated in Figure 3.7(c).

Mode 4: This mode occurs during negative cycle of the AC supply

when the switch ‘S’ is in OFF condition. During this condition, the charge in
inductance ‘L’ and the supply voltage Vac are added together and the current
flows through the diode and stores the voltage in the capacitor .
Similarly, during the circulating path, ‘ ’ the inductance
‘ ’ is charged. Then, the discharge of ‘ ’ is completed through the load RL
with the current flow, ‘ ’ as shown in Figure 3.7 (d).
Similar to Mode 2 the capacitors and will be in series with the load.

For a supply voltage of with an rms value of 230 V, the average

voltage appearing at the input side is given by the Equation (3.6) (Singh &
Singh 2010),

2 2Vs
Vin (3.6)

The relation stating the voltage conversion ratio of the cuk

converter is given by the Equation (3.7) (Singh & Singh 2010),

Vdc
d (3.7)
Vdc Vin

where, d is the duty ratio of the cuk converter and Vdc is the DC-link voltage
or DC output voltage of the converter.
 61

The proposed cuk converter is designed for the DC-link voltage

varied from 200 V (Vdc min) to 425 V (Vdc max). Hence, the minimum and the
maximum duty ratio (dmin and dmax) corresponding to Vdc min and Vdc max are
calculated as 0.49 and 0.67 respectively. For all speed variations, the
minimum power is given in the Equation (3.8)

Pmin Vdc min Idc (3.8)

where, Vdc min is the minimum DC-link voltage

Idc is the DC-link current.

The minimum value of the input inductor ( ) is calculated at the

duty ratio of dmin such that the converter operates in DCM even at very low
duty ratio. At minimum duty ratio, the BLDC motor operates at and
. The value of inductance corresponding to is calculated by
the Equation (3.9).

1 dmin
Lmin RL (3.9)
2 fs

The value of output side inductors (L01,02) are calculated by the

Equations (3.10) and (3.11)

2
VSmin Vdcmax Vdcmax
L 01, 02 max (3.10)
Pmax 2 2VSmin f S 2VSmin Vdcmax

2
VSmin Vdcmin Vdcmin
L 01, 02min (3.11)
Pmin 2 2VSmin f S 2VSmin Vdcmin
 62

The critical values of the intermediate capacitors CL1 & CL2 are
calculated based on the maximum ripple in the intermediate capacitor which
occurs at the maximum supply voltage. Hence, the critical value of the
intermediate capacitances calculated at maximum DC-link voltage are given
by the Equations (3.12) and (3.13).

Pmax
CL1 , L2 (max ) 2 (3.12)
2 fs 2 Vs max Vdc max

Pmin
CL1 , L2 ( min ) 2 (3.13)
2 fs 2 Vs max Vdc min

The value of the DC-link capacitor is calculated at maximum value

of DC-link voltage as given in equation (3.14),

Pmax
C01,02max 2 (3.14)
Vdcmax

where, angular frequency and is the permitted ripple in DC-

link voltage. Further analysis are made by considering the value of ripple as
4% .

3.4 SIMULATION RESULTS AND DISCUSSION

The results obtained from the simulation studies of the proposed

bridgeless PFC are discussed in this section. The input to the proposed
converter is single phase 230 V, 50 Hz AC supply and the total period of
simulation is chosen to be 0.5 sec. The simulation parameters of the proposed
cuk converter system are furnished in Table 3.3.
 63

Table 3.3 Simulation parameters of the proposed BL PFC cuk converter

Description Value Unit

Bridgeless Cuk Converter
Input and Output Power 500 W
Output Current 1.5 A
Input inductor (L) 0.75 mH
Capacitor (CL1) 120 µF
Capacitor (CL2) 120 µF
Inductor (Lo1) 90 mH
Inductor (Lo2) 90 mH
Capacitor (C01) 30 µF
Capacitor (C02) 30 µF
Switching Frequency (fs) 25000 Hz

The simulated waveforms of the proposed cuk converter design are

shown in Figure 3.9. The parameters associated with the proposed cuk
converter such as source voltage, source current, diode currents, inductor
currents, switch current, switch voltage and capacitor currents are evaluated to
demonstrate its proper functioning. Figure 3.9 (a) and 3.9 (b) show the AC
source voltage and current waveforms of the proposed cuk converter,
respectively. The source voltage of the converter is observed to be 230 V and
the value of source current is 2.5 Amps. From the figure, it is found that the
source current is purely sinusoidal and in-phase with the supply voltage. The
(diodes D1 and D2) current waveforms of during both the positive and
negative half cycle of the input voltage are shown in Figure 3.9 (c) and (d).
The output inductors (ILo1 and ILo1) current during positive and negative half
cycles are also shown in Figure 3.9 (e) and (f).
 64

(a) AC Source voltage waveform

(b) AC Source current waveform

(c) Input diode (D1) current during positive cycle

 65

(d) Input diode (D2) current during negative cycle

(e) Output inductor currents (ILo1) during positive half cycle

(f) Output inductor currents (ILo2) during negative half cycle

Figure 3.8 (Continued)

 66

(g) Switch current

(h) Switch voltage

(i) Intermediate capacitor (CL1 and CL2) current

Figure 3.8 (Continued)

 67

(j) Voltage across the capacitor C01

(k) Voltage across the capacitor C02

(l) Efficiency of the Type 3 and proposed cuk converter

Figure 3.8 Simulated waveforms of proposed cuk converter

 68

Figure 3.8 (g) and (h) show the switch current and voltage waveforms,
respectively. The switch voltage of the converter is observed to be 670 V,
whereas the switch current is observed to be 25 Amps. The intermediate
capacitors (CL1 and CL2) current, voltage across the output capacitor C01 and
C02, efficiency of the converters are depicted in Figures 3.8 (i)-(l). Figure 3.8
(l). it is observed that the efficiency of proposed cuk converter is around 91%

From the simulation results it is observed that the proposed cuk

converter offers reduced switching stress and less ripple in the DC output.
The main drawback is found in conventional PFC Type-3 cuk converter is
that, the number of semiconductor devices utilized is 13 which results in
higher device losses. It is clearly observed from the discussion, that the
proposed converter design utilizes only 10 power utility devices which reduce
the device losses. Particularly, the number of switches utilized in the proposed
converter is one, where as in the conventional converters as in Table 3.2
utilizes more than one switch. This would also result in lesser switching
losses which in turn increases the efficiency of the proposed cuk converter.

3.5 SUMMARY

This chapter discusses about the conventional converter topologies

and its types. Comparative studies between bridged and bridgeless converters
are made in terms of number of active and passive devices and the importance
of bridgeless converter and their performance is investigated. This chapter
also discusses about the bridgeless cuk converter for PFC applications. In this
chapter, a conventional and novel PFC cuk converter design is thoroughly
analyzed. The validity and performance of the novel cuk converter topology is
verified by simulation results. The present research work aims to design a
bridgeless PFC cuk converter model with lesser power utility components.