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Nand Nor PDF
Nand Nor PDF
1
NAND Gates
S The basic positive logic NAND gate is denoted
by the following symbol:
• AND-Invert (NAND)
X
Y F( X , Y , Z ) = X ⋅ Y ⋅ Z
Z
2
NAND Function Implementation
S NAND gates can implement a simplified Sum-of-
Products form. Constructing two level NAND-NAND
gate circuit: A
B
G( A, B, C, D ) = A ⋅ B + C ⋅ D
C
D
S The first level is two 2-input NAND gates using AND-
Invert. The second level is one 2-input NAND gate
using Invert-OR. Using the NAND relationship, we
have:
G( A , B, C, D ) = A⋅B ⋅ C⋅D
= A⋅B + C⋅D
Logic and Computer Design Fundamentals
= A ⋅B + C⋅D
Chapter 2-Part 7 5
© 2001 Prentice Hall, Inc
3
NAND Implementation (Cont.)
S In the implementation, the bubbles are on opposite
ends of the same line.
S By X = X , they can be combined and deleted:
A
B
G(A,B,C,D)
C
D
S A sum-of-products (SOP) form results
S To implement an equation like: F(A,B,C) = A + BC, the
NAND for A degenerates to a NOT since there is only
one input
4
NAND-NAND Example
S Implement:y F( w , x , y , z ) = y z + w x + x y + yw z
1 1 1 1 1 0
1 1
1 3
1 2
0 1 3 2
1 0 0 1 1 4
0 5
0 7
1 6
4 5 7 6
x x
1 0 0 0 1 12 0 13 0 15 0 14
12 13 15 14
w w
1 1 0 0 1 8
1 9
0 11 0 10
8 9 11 10
z z
F(w,x,y,z) F’ (w,x,y,z)
5
NOR Gates
The basic positive logic NOR gate (Not-OR) is denoted
by the following symbol:
X
OR-Invert Y F(X, Y, Z) = X +Y+Z
(NOR) Z
NOR Gates
S The basic positive logic NOR gate is denoted by
the following symbol:
• OR-Invert (NOR)
X
Y F(X, Y, Z) = X +Y+Z
Z
S NOR comes from NOT OR, I. e., the OR
function with a NOT applied. We call this
symbol for a NOR gate an OR-Invert. The
small circle represents the invert function.
S If we apply DeMorgan's Law we get:
X +Y +Z = X Y Z
Logic and Computer Design Fundamentals Chapter 2-Part 7 12
© 2001 Prentice Hall, Inc
6
NOR Gates (Cont.)
S Applying DeMorgan's Law gives:
• Invert-AND (NOR)
X
Y F( X , Y , Z ) = X Y Z
Z
S We call this symbol for a NOR gate the Invert-
AND since all inputs are inverted, followed by the
AND function.
S Both symbols represent the NOR gate - it is
sometimes more logically descriptive to use one
form over the other.
S A NOR gate with one input degenerates to an
inverter.
Logic and Computer Design Fundamentals Chapter 2-Part 7 13
© 2001 Prentice Hall, Inc
7
Useful Transformations
From Involution (i.e. (A')' = A) and DeMorgan's Law, we
get the following useful equivalences:
Graphical Transformations
The relations from the previous slide lead to the
following transformations:
8
General Two-level Implementations
We need to consider whether the form of a two-level
implementation is to be:
1. SOP (AND-OR) or
2. POS (OR-AND).
9
Implementation Example 1
B
1
Implement the function in NOR-OR.
1 1 0
A 1 1 0 0
Implementation Example 2
B Implement the function in AND-NOR.
1 1 0 1
A 1 1 0 0
10
Multi-level NAND Implementations
S Add inverters in two-level
implementation into the cost picture
S Attempt to “combine” inverters to reduce
the term count
S Attempt to reduce literal + term count by
factoring expression into POSOP or
SOPOS
B F
11
Multilevel NAND Example 2
S F = AB + AD’ + BC + CD’
12