CMOS Logic Data ON Semicondutor PDF

DL131/D
Rev. 4, Mar-2000
CMOS Logic Data
ON Semiconductor
ON Semiconductor
CMOS Logic Data

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further
notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC
products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and
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DL131/D 03/00
DL131
REV 4
CMOS Logic Data
This book presents technical data for the broad line of CMOS logic integrated circuits and demonstrates ON Semicon-
ductor’s continued commitment to Metal–Gate CMOS. Complete specifications are provided in the form of data sheets.
In addition, a Product Selector Guide and a Handling and Design Guidelines chapter have been included to familiarize
the user with these circuits.
DL131/D
Rev. 4, March–2000
 SCILLC, 2000
Previous Edition  1991
“All Rights Reserved’’
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Center for ON Semiconductor Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
P.O. Box 5163, Denver, Colorado 80217 USA Email: ONlit–spanish@hibbertco.com
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
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Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada Toll Free from Hong Kong & Singapore:
001–800–4422–3781
N. American Technical Support: 800–282–9855 Toll Free USA/Canada Email: ONlit–asia@hibbertco.com
EUROPE: LDC for ON Semiconductor – European Support JAPAN: ON Semiconductor, Japan Customer Focus Center
German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time) 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549
Email: ONlit–german@hibbertco.com Phone: 81–3–5740–2745
French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time) Email: r14525@onsemi.com
Email: ONlit–french@hibbertco.com
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time) ON Semiconductor Website: http://onsemi.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 For additional information, please contact your local
*Available from Germany, France, Italy, England, Ireland Sales Representative.
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Table of Contents
Page
Chapter 1 — Master Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Alphanumeric Listing of All CMOS Part Numbers with Function and Page Number Information Provided
Chapter 2 — Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CMOS Selection Guide Sorted by Product Function
Chapter 3 — Reliability Audit Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Explanation of On Semiconductor’s Outgoing Product Performance Audit Program
Chapter 4 — B and UB Series Family Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Explanation of Standardized Specifications for the Product Family
Chapter 5 — CMOS Handling and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Handling Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input Protection Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Propagation Delay and Rise Time versus Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CMOS Latch Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter 6 — CMOS Logic Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

See the Master Index for Page Numbering Information
Chapter 7 — CMOS Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Optimizing the Long Term Reliability of Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Chapter 8 — Equivalent Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Chapter 9 — Packaging Information Including Surface Mounts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
ON Semiconductor Major Worldwide Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
ON Semiconductor Standard Document Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
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SCANSWITCH, SENSEFET, SLEEPMODE, SMALLBLOCK, SMARTDISCRETES, SMARTswitch, SUPERBRIDGES,
SuperLock, Surmetic, SWITCHMODE, Thermopad, Thermowatt, TMOS, TMOS & Design Device, TMOS Stylized, Unibloc,
UNIT/PAK, Uniwatt, WaveFET, Z–Switch and ZIP R TRIM are trademarks of Semiconductor Components Industries, LLC
(SCILLC).
HDTMOS and HVTMOS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
All other brand names and product names appearing in this publication are registered trademarks or trademarks of their
respective holders.
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CHAPTER 1
Master Index
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MASTER INDEX
Device Function Page

MC14001B Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14001UB Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MC14008B 4–Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
MC14011B Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14011UB Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MC14013B Dual D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
MC14014B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
MC14015B Dual 4–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
MC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
MC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
MC14018B Presettable Divide–by–N Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MC14020B 14–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
MC14023B Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14024B 7–Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
MC14025B Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14027B Dual J–K Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
MC14028B BCD–to–Decimal/Binary–to–Octal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
MC14040B 12–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
MC14043B Quad NOR R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
MC14044B Quad NAND R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
MC14046B Phase–Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
MC14051B 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MC14052B Dual 4–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MC14053B Triple 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MC14060B 14–Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
MC14067B 16–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
MC14069UB Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
MC14070B Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
MC14071B Quad 2–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14073B Triple 3–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14076B Quad D–Type Register with Tri–State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
MC14077B Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
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MC14081B Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14082B Dual 4–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14093B Quad 2–Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
MC14094B 8–Stage Shift/Store Register with Tri–State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
MC14099B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
MC14106B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
MC14174B Hex D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
MC14175B Quad D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
MC14490 Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
MC14503B Hex 3–State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
MC14511B BCD–to–7–Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
MC14512B 8–Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
MC14513B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . . . . . . . . . . . . 259
MC14514B 4–Bit Transparent Latch/4–to–16 Line Decoder (High) . . . . . . . . . . . . . . . . . . . . . . . . . . 268
MC14515B 4–Bit Transparent Latch/4–to–16 Line Decoder (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . 268
MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
MC14517B Dual 64–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
MC14521B 24–Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
MC14526B Presettable 4–Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
MC14528B Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
MC14532B 8–Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
MC14538B Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
MC14543B BCD–to–7–Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . . . . . . . . . . . . 354
MC14549B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
MC14551B Quad 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
MC14553B 3–Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
MC14555B Dual Binary to 1–of–4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . 383
MC14556B Dual Binary to 1–of–4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
MC14557B 1–to–64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
MC14562B 128–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
MC14569B Programmable Dual 4–Bit Binary/BCD Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 399
MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
MC14585B 4–Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
MC14598B 8–Bit Bus–Compatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
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CHAPTER 2
Product Selection Guide
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CMOS Selection Guide by Function
NAND Gates
MC14011B Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14011UB Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MC14023B Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
NOR Gates
MC14001B Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14001UB Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MC14025B Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AND Gates
MC14081B Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14073B Triple 3–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14082B Dual 4–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Complex Gates
MC14070B Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
MC14077B Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Inverters/Buffers/Level Translator
MC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
MC14069UB Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
MC14503B Hex 3–State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Decoders/Encoders
MC14028B BCD–to–Decimal/Binary–to–Octal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
MC14511B BCD–to–7–Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
MC14513B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . . . . . . . . . . . . 259
MC14543B BCD–to–7–Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . . . . . . . . . . . . 354
MC14514B 4–Bit Transparent Latch/4–to–16 Line Decoder (High) . . . . . . . . . . . . . . . . . . . . . . . . . . 268
MC14515B 4–Bit Transparent Latch/4–to–16 Line Decoder (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . 268
MC14532B 8–Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
MC14555B Dual Binary to 1–of–4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . 383
MC14556B Dual Binary to 1–of–4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Multiplexers/Demultiplexers/Bilateral Switches
MC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
MC14551B Quad 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
MC14053B Triple 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MC14052B Dual 4–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MC14067B 16–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
MC14051B 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MC14512B 8–Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Schmitt Triggers
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OR Gates
MC14071B Quad 2–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Flip–Flops/Latches
MC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
MC14043B Quad NOR R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
MC14044B Quad NAND R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
MC14076B Quad D–Type Register with Tri–State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
MC14175B Quad D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
MC14013B Dual D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
MC14027B Dual J–K Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
MC14174B Hex D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
MC14099B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
MC14598B 8–Bit Bus–Compatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Shift Registers
MC14015B Dual 4–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
MC14517B Dual 64–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
MC14562B 128–Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
MC14557B 1–to–64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
MC14094B 8–Stage Shift/Store Register with Tri–State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Counters
MC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
MC14018B Presettable Divide–by–N Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MC14020B 14–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
MC14024B 7–Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
MC14040B 12–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MC14060B 14–Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
MC14526B Presettable 4–Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
MC14553B 3–Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
MC14569B Programmable Dual 4–Bit Binary/BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Oscillators/Timers
MC14521B 24–Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Multivibrators
MC14528B Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
MC14538B Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Adders/Comparators
MC14008B 4–Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
MC14585B 4–Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Other Complex Functions
MC14046B Phase–Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
MC14490 Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
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CHAPTER 3
Reliability Audit Program
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RAP"
Reliability Audit Program
For Logic Integrated Circuits
1.0 INTRODUCTION
The Reliability Audit Program developed in March 1977 “Reliability and Quality Handbook” which contains data for
is the ON Semiconductor internal reliability audit which is all ON Semiconductor devices (HBD851/D).
designed to assess outgoing product performance under RAP is a system of environmental and electrical tests
accelerated stress conditions. Logic Reliability Engineering performed periodically on randomly selected samples of
has overall responsibility for RAP, including updating its standard products. Each sample receives the tests specified
requirements, interpreting its results, administration at in section 2.0. Frequency of testing is specified per internal
offshore locations, and monthly reporting of results. These document 12MRM15301A.
reports are available at all sales offices. Also available is the
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2.0 RAP TEST FLOW
Pull 500* piece sample from lot following Group A

acceptance.
45* 340 100
INITIAL
SEAL**
OP LIFE
40 HOURS
PTHB PTH*** TEMP CYCLES
48 HRS 48 HRS 40 CYCLES
INTERIM
ELECTRICAL
INTERIM
TEST
OP LIFE
210 HRS (ADDITIONAL)
INTERIM ADD 460 CYCLES
ELECTRICAL FINAL
INTERIM INTERIM #
TEST ELECTRICAL
ADD 500 CYCLES

FINAL
PTH INTERIM*
48 HRS TEST
(ADDITIONAL)
OP LIFE #
750 HRS
TEMP CYCLES #
(ADDITIONAL)
1000 CYCLES
(ADDITIONAL)
FINAL FINAL
ELECTRICAL ELECTRICAL
(48 HRS) (96 HRS) FINAL #
FINAL
ELECTRICAL
ELECTRICAL
(1000 HRS)
& SEAL**
(2000 CYCLES)
SCRAP SCRAP SCRAP
#One sample per month for FAST, LS, 10H, 10K, MG CMOS, and HSL CMOS.
* PTHB or PTH not required for hermetic products: reduce total sample size to 450 pcs.
** Seal (Fine & Gross Leak) required only for hermetic products.
*** PTH to be used when sockets for PTHB are not available.
3.0 TEST CONDITIONS AND COMMENTS

PTHB — 15 psig/121°C/100% RH at rated VCC or VEE — 3. Sampling to include all package types routinely.
to be performed on plastic encapsulated devices 4. Device types sampled will be by generic type within each
only. logic I/C product family (CMOS, TTL, etc.) and will
TEMP CYCLING — MIL–STD–883, Method 1010, include all assembly locations (Korea, Philippines,
Condition C, – 65°C/+ 150°C. Malaysia, etc.).
OP LIFE — MIL–STD–883, Method 1005, Condition C
v
5. 16 hrs. PTHB is equivalent to approximately 800 hours
(Power plus Reverse Bias), TA = 145°C. of 85°C/85% RH THB for VCC 15 V.
NOTES: 6. Only moisture related failures (like corrosion) are criteria
1. All standard 25°C dc and functional parameters will be for failure on PTHB test.
measured Go/No/Go at each readout. 7. Special device specifications (48A’s) for logic products
2. Any indicated failure is first verified and then submitted will reference 12MRM15301A as source of generic data
to the Product Analysis Lab for detailed analysis. for any customer required monthly audit reports.
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CHAPTER 4
B and UB Series Family Data
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B AND UB SERIES FAMILY DATA
The CMOS Devices in this volume which have a B or UB Devices with specialized inputs, such as oscillator
suffix meet the minimum values for the industry– inputs, have unique input specifications.
standardized* family specification. These standardized
values are shown in the Maximum Ratings and Electrical Input Voltage
Characteristics Tables. In addition to a standard minimum The input voltage specification is interpreted as the
specification for characteristics the B/UB devices feature: worstcase input voltage to produce an output level of “1” or
“0”. This “1” or “0” output level is defined as a deviation
• 3–18 volt operational limits
from the supply (VDD) and ground (VSS) levels. For a 5.0 V
• Capable of driving two low–power TTL loads or one
supply, this deviation is 0.5 V; for a 10 V supply, 1.0 V; and
low–power Schottky TTL load over the rated
for 15 V, 1.5 V. As an example, in a device operating at a 5.0
temperature range
V supply, the device with the input starting at ground is
• Direct Interface to High–Speed CMOS guaranteed to switch on or before 3.5 V and not to switch up
• Maximum input current of ± 1 µA at 15 volt power to 1.5 V. Switching and not switching are defined as within
supply over the temperature range 0.5 V of the ideal output level for the example with a 5.0 V
• Parameters specified at 5.0, 10, and 15 volt supply supply. The actual switching level referred to the input is
• Noise margins: B Series between 1.5 V and 3.5 V.
1.0 V min @ 5.0 V supply
2.0 V min @ 10 V supply Noise Margin
2.5 V min @ 15 V supply The values for input voltages and the defined output
deviations lead to the calculated noise margins. Noise
UB Series margin is defined as the difference between VIL or VIH and
0.5 V min @ 5.0 V supply Vout (output deviation). As an example, for a noninverting
1.0 V min @ 10 V supply buffer at VDD = 5.0 volts: VIL = 1.5 volts and Vout = 0.5
1.0 V min @ 15 V supply volts. Therefore, Noise Margin equals VIL – Vout = 1.0 volt.
The industry–standardized maximum ratings are shown at This figure is useful while cascading stages (See Figure 1).
the bottom of this page. Limits for the static characteristics With the input to the first stage at a worst–case voltage level
are shown in two formats: Table 1 is in the industry format (VIL = 1.5 V), the output is guaranteed to be no greater than
and Table 2 is in the equivalent ON Semiconductor format. 0.5 volts with a 5.0 volt supply. Since the maximum
The ON Semiconductor format is used throughout this data allowable logic 0 for the second stage is 1.5 volts, this 0.5
book. Additional specification values are shown on the volt output provides a 1.0 volt margin for noise to the next
individual data sheets. stage.
Switching characteristics for the B and UB series devices
are specified under the following conditions: Output Drive Current
Load Capacitance, CL, of 50 pF Devices in the B Series are capable of sinking a minimum
Input Voltage equal to VSS – VDD (Rail–to–Rail of 0.36 mA over the temperature range with a 5.0 V supply.
swing) This value guarantees that these CMOS devices will drive
Input pulse rise and fall times of 20 ns one low–power Schottky TTL input.
Propagation Delay times measured from 50% point of
B Series vs UB CMOS
input voltage to 50% point of output voltage
The primary difference between B series and UB series
Three different supply voltages: 5, 10, and 15 V
devices is that UB series gates and inverters are constructed
Exceptions to the B and UB Series Family with a single inverting stage between input and output. The
Specification decreased gain caused by using a single stage results in less
There are a number of devices which have a B or UB suffix noise immunity and a transfer characteristic that is less ideal.
whose inputs and/or outputs vary somewhat from the family The decreased gain is quite useful when CMOS Gates and
specification because of functional requirements. Some inverters are used in a “Linear” mode to form oscillators,
categories of notable exceptions are: monostables, or amplifiers. The decreased gain results in
increased stability and a “cleaner” output waveform. In
Devices with specialized outputs on the chip, such as
addition to linear operation, the UB gates and inverters offer
NPN emitter–follower drivers or transmission gates,
an increase in speed, since only a single stage is involved.
do not meet output specifications.
The B and UB series, and devices with no suffix can be
used interchangeably in digital circuits that interface to other
CMOS devices, such as High–Speed CMOS Logic.
* Specifications coordinated by EIA/JEDEC Solid–State Products Council.
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎ
ÎÎÎ
Parameters Value Unit
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
± 10
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Iin, lout Input or Output Current (DC or Transient), per Pin mA
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150 _C
ÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values values beyond which damage to the device may occur.
†Temperature Derating:
260 _C
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
5.0 V
VIL = 1.5 V Vout = 0.5 V Vout
FIRST STAGE VIL = 1.5 V SECOND STAGE

(NONINVERTING BUFFER) (NONINVERTING BUFFER)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Figure 1.
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications
ÎÎÎ
ELECTRICAL CHARACTERISTICS
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Limits
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
TLOW* + 25_C THIGH*
ÎÎÎÎÎÎÎÎÎ
Temp VDD
Parameter Range (Vdc) Conditions Min Max Min Max Min Max Units
ÎÎÎÎ
ÎÎÎÎÎÎ
IDD
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Quiescent
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Device Current
ÎÎÎ
ÎÎÎ
ÎÎÎ
Mil 5
10
15
Vin = VSS or VDD
0.25
0.5
1.0
0.25
0.5
1.0
7.5
15
30
µAdc
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
GATES
ÎÎÎ
ÎÎÎ
Comm 5
10
All valid input
combinations
1.0
2.0
1.0
2.0
7.5
15
µAdc
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 4.0 4.0 30
µAdc
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Mil 5 1.0 1.0 30
10 VIN = VSS or VDD 2.0 2.0 60
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 4.0 4.0 120
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
BUFFERS, Comm 5 All valid input 4 4.0 30 µAdc
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
FLIP–FLOPS 10 combinations 8 8.0 60
15 16 16.0 120
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Mil 5
10
15
VIN = VSS or VDD
5
10
20
5
10
20
150
300
600
µAdc
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
MSI
ÎÎÎ
Comm 5
10
All valid input
combinations
20
40
20
40
150
300
µAdc
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 80 80 600
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VOL Low–Level All 5 0.05 0.05 0.05 Vdc
Output Voltage 10 VIN = VSS or VDD 0.05 0.05 0.05
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 |IO| < 1 µA 0.05 0.05 0.05
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VOH High–Level All 5 4.95 4.95 4.95 Vdc
ÎÎÎÎ
ÎÎÎÎÎÎ
Output Voltage
ÎÎÎ
ÎÎÎ
10
ÎÎÎÎÎÎ
VIN = VSS or VDD
ÎÎÎ
9.95
ÎÎÎÎ
ÎÎÎ
9.95
ÎÎÎ
ÎÎÎ
9.95
ÎÎÎ
ÎÎÎ 15 |IO| < 1 µA 14.95 14.95 14.95
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20
Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications (continued)
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎTemp VDD TLOW*
Limits
+ 25_C THIGH*
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Parameter Range (Vdc) Conditions Min Max Min Max Min Max Units
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIL Input All 5 VO = 0.5V or 4.5V 1.5 1.5 1.5 Vdc
Low Voltage#
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10 VO = 1.0V or 9.0V 3.0 3.0 3.0
B Types 15 VO = 1.5V or 13.5V 4.0 4.0 4.0
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
|IO| < 1 µA
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIL Input All 5 VO = 0.5V or 4.5V 1.0 1.0 1.0
Low Voltage# 10 VO = 1.0V or 9.0V 2.0 2.0 2.0
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
UB Types
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
15 VO = 1.5V or 13.5V
|IO| < 1 µA
2.5 2.5 2.5
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIH Input All 5 VO = 0.5V or 4.5V 3.5 3.5 3.5 Vdc
High Voltage# 10 VO = 1.0V or 9.0V 7.0 7.0 7.0
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
B Types 15 VO = 1.5V or 13.5V 11.0 11.0 11.0
|IO| < 1 µA
ÎÎÎÎ
ÎÎÎÎÎÎ
VIH
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
Input
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
High Voltage# ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
All 5
10
VO = 0.5V or 4.5V
VO = 1.0V or 9.0V
4.0
8.0
4.0
8.0
4.0
8.0
Vdc
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
UB Types 15 VO = 1.5V or 13.5V 12.5 12.5 12.5
|IO| < 1 µA
ÎÎÎÎ
ÎÎÎÎÎÎ
IOL
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
Output Low
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Sink) Current ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Mil 5 VO = 0.4V,
VIN = 0 or 5V 0.64 0.51 0.36
mAdc
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10 VO = 0.5V,
VIN = 0 or 10V 1.6 1.3 0.9
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ 15 VO = 1.5V,
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIN = 0 or 15V 4.2 3.4 2.4
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Com 5 VO = 0.4V, mAdc
VIN = 0 or 5V 0.52 0.44 0.36
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10 VO = 0.5V,
VIN = 0 or 10V 1.3 1.1 0.9
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
15 VO = 1.5V,
VIN = 0 or 15V 3.6 3.0 2.4
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
IOH Output High Mil VO = 4.6V, mAdc
(Source) Current 5 VIN = 0 or 5V – 0.25 – 0.2 – 0.14
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VO = 9.5V,
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10 VIN = 0 or 10V – 0.62 – 0.5 – 0.35
VO = 13.5V,
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 VIN = 0 or 15V – 1.8 – 1.5 – 1.1
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Com VO = 4.6V, mAdc
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
5 VIN = 0 or 5V – 0.2 – 0.16 – 0.12
VO = 9.5V,
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10 VIN = 0 or 10V – 0.5 – 0.4 – 0.3
VO = 13.5V
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
IIN ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Input Current ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎMil
15
15
VIN = 0 or 15V
VIN = 0 or 15V
– 1.4
± 0.1
– 1.2
± 0.1
– 1.0
± 1.0 µAdc
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Comm 15 VIN = 0 or 15V ± 0.3 ± 0.3 ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Ioz 3–State Output Mil 15 VIN = 0 or 15V ± 0.4 ± 0.4 ± 12 µAdc
Leakage Current Comm 15 VIN = 0 or 15V ± 1.6 ± 1.6 ± 12 µAdc
ÎÎÎÎ
ÎÎÎÎÎÎ
CIN
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
per unit load ÎÎÎ
Input Capacitance
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
All — Any Input 7.5
* TLOW = – 55_C for Military temperature range device, – 40°C for Commercial temperature range device.
pF
THIGH = + 125_C for Military temperature range device, + 85_C for Commercial temperature range device.
#Applies for Worst Case input combinations.
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21
Table 2. ON Semiconductor Format for CMOS Industry B and UB Series Specifications
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ VDD – 55_C 25_C + 125_C
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Min Max Min Max Min Max Unit
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Voltage “0” Level VOL 5.0 — 0.05 — 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0.05 — 0.05
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0.05 — 0.05
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 — 9.95 —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ 15 14.95 — 14.95 — 14.95 —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage B Types “0” Level VIL Vdc
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 3.0 — 3.0
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 4.0 — 4.0
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 — 3.5 —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 — 7.0 —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 — 11 —
Input Voltage UB Types “0” Level VIL Vdc
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VO = 4.5 or 0.5 Vdc)
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
—
—
—
1.0
2.0
2.5
—
—
—
1.0
2.0
2.5
—
—
—
1.0
2.0
2.5
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH
5.0
10
4.0
8.0
—
—
4.0
8.0
—
—
4.0
8.0
—
—
Vdc
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VO = 1.5 or 13.5 Vdc)
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Output Drive Current B Gates
ÎÎÎ
IOH
15 12.5 — 12.5 — 12.5 —
mAdc
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 — – 0.36 —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 — – 2.4 —
ÎÎÎ
ÎÎÎ ÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
—
—
0.36
0.9
—
—
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 — 2.4 —
Output Drive Current UB Gates IOH mAdc
ÎÎÎ
ÎÎÎ ÎÎÎ
(VOH = 2.5 Vdc)
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Source 5.0
5.0
10
– 1.2
– 0.25
– 0.62
—
—
—
– 1.0
– 0.2
– 0.5
—
—
—
– 0.7
– 0.14
– 0.35
—
—
—
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL
15
5.0
– 1.8
0.64
—
—
– 1.5
0.51
—
—
– 1.1
0.36
—
—
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 — 2.4 —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current Other Devices IOH mAdc
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) Source 5.0 – 0.64 — – 0.51 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 — – 0.9 —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 — – 2.4 —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 — 0.36 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 — 0.9 —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ

ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Iin
15
15
4.2
—
—
± 0.1
3.4
—
—
± 0.1
2.4
—
—
± 1.0 µAdc
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance (Vin = 0) Cin — — — — 7.5 — — pF
µAdc
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Gate Quiescent Current IDD 5.0 — 0.25 — 0.25 — 7.5
(Per Package) 10 — 0.5 — 0.5 — 15
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 1.0 — 1.0 — 30
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Flip–Flop and Buffer Quiescent Current IDD 5.0 — 1.0 — 1.0 — 30 µAdc
(Per Package) 10 — 2.0 — 2.0 — 60
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 4.0 — 4.0 — 120
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
MSI Quiescent Current IDD 5.0 — 5.0 — 5.0 — 150 µAdc
(Per Package) 10 — 10 — 10 — 300
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ 15 — 20 — 20 — 600
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
LSI Quiescent Current IDD See Individual Data Sheets.
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CHAPTER 5
CMOS Handling and Design Guidelines
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HANDLING AND DESIGN GUIDELINES
HANDLING PRECAUTIONS a CMOS device, a resistor should be used in series
with the input. This resistor helps limit accidental
All MOS devices have insulated gates that are subject to
damage if the PC board is removed and brought into
voltage breakdown. The gate oxide for ON Semiconductor
contact with static generating materials. The limiting
CMOS devices is about 900 Å thick and breaks down at a
factor for the series resistor is the added delay. This is
gate–source potential of about 100 volts. To guard against
caused by the time constant formed by the series
such a breakdown from static discharge or other voltage
resistor and input capacitance. Note that the maximum
transients, the protection networks shown in Figures 1A and
input rise and fall times should not be exceeded. In
1B are used on each input to the CMOS device.
Figure 2, two possible networks are shown using a
Static damaged devices behave in various ways,
series resistor to reduce ESD (Electrostatic
depending on the severity of the damage. The most severely
Discharge) damage. For convenience, an equation for
damaged inputs are the easiest to detect because the input
added propagation delay and rise time effects due to
has been completely destroyed and is either shorted to VDD,
series resistance size is given.
shorted to VSS, or open–circuited. The effect is that the
5. All CMOS devices should be stored or transported in
device no longer responds to signals present at the damaged
materials that are antistatic. CMOS devices must not
input. Less severe cases are more difficult to detect because
be inserted into conventional plastic “snow”,
they show up as intermittent failures or as degraded
styrofoam, or plastic trays, but should be left in their
performance. Another effect of static damage is that the
original container until ready for use.
inputs generally have increased leakage currents.
6. All CMOS devices should be placed on a grounded
Although the input protection network does provide a
bench surface and operators should ground
great deal of protection, CMOS devices are not immune to
themselves prior to handling devices, since a worker
large static voltage discharges that can be generated during
can be statically charged with respect to the bench
handling. For example, static voltages generated by a person
surface. Wrist straps in contact with skin are strongly
walking across a waxed floor have been measured in the
recommended. See Figure 3 for an example of a
4 –15 kV range (depending on humidity, surface conditions,
typical work station.
etc.). Therefore, the following precautions should be
7. Nylon or other static generating materials should not
observed:
come in contact with CMOS devices.
1. Do not exceed the Maximum Ratings specified by the
8. If automatic handlers are being used, high levels of
data sheet.
static electricity may be generated by the movement
2. All unused device inputs should be connected to VDD
of the device, the belts, or the boards. Reduce static
or VSS.
build–up by using ionized air blowers or room
3. All low–impedance equipment (pulse generators,
humidifiers. All parts of machines which come into
etc.) should be connected to CMOS inputs only after
contact with the top, bottom, or sides of IC packages
the device is powered up. Similarly, this type of
must be grounded to metal or other conductive
equipment should be disconnected before power is
material.
turned off.
9. Cold chambers using CO2 for cooling should be
4. Circuit boards containing CMOS devices are merely
equipped with baffles, and the CMOS devices must be
extensions of the devices, and the same handling
contained on or in conductive material.
precautions apply. Contacting edge connectors wired
10. When lead–straightening or hand–soldering is
directly to device inputs can cause damage. Plastic
necessary, provide ground straps for the apparatus
wrapping should be avoided. When external
used and be sure that soldering ties are grounded.
connections to a PC board are connected to an input of
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INPUT PROTECTION NETWORK
VDD VDD
CMOS CMOS
TO CIRCUIT
INPUT INPUT
< 1500 Ω 300 Ω
VSS VSS
Figure 1a. Input Protection Network Figure 1b. Input Protection Network
Double Diode Triple Diode
11. The following steps should be observed during wave 13. The use of static detection meters for production line
solder operations: surveillance is highly recommended.
a. The solder pot and conductive conveyor system of 14. Equipment specifications should alert users to the
the wave soldering machine must be grounded to presence of CMOS devices and require
an earth ground. familiarization with this specification prior to
b. The loading and unloading work benches should performing any kind of maintenance or replacement
have conductive tops which are grounded to an of devices or modules.
earth ground. 15. Do not insert or remove CMOS devices from test
c. Operators must comply with precautions sockets with power applied. Check all power supplies
previously explained. to be used for testing devices to be certain there are no
d. Completed assemblies should be placed in voltage transients present.
antistatic containers prior to being moved to 16. Double check test equipment setup for proper polarity
subsequent stations. of VDD and VSS before conducting parametric or
12. The following steps should be observed during functional testing.
board–cleaning operations: 17. Do not recycle shipping rails or trays. Repeated use
a. Vapor degreasers and baskets must be grounded to causes deterioration of their antistatic coating.
an earth ground.
b. Brush or spray cleaning should not be used.
c. Assemblies should be placed into the vapor RECOMMENDED FOR READING:
degreaser immediately upon removal from the
antistatic container. “Total Control of the Static in Your Business”
d. Cleaned assemblies should be placed in antistatic
containers immediately after removal from the Available by writing to:
cleaning basket. 3M Company
e. High velocity air movement or application of Static Control Systems
solvents and coatings should be employed only P.O. Box 2963
when assembled printed circuit boards are Austin, Texas 78769–2963
grounded and a static eliminator is directed at the Or by Calling:
board. 1–800–328–1368
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25
VDD
CMOS D1 CMOS
TO OFF–BOARD R1 INPUT TO OFF–BOARD R2 INPUT
CONNECTION OR CONNECTION OR
OUTPUT OUTPUT
D2
Advantage: Requires minimal board area Advantage: R2 < R1 for the same VSS
level of protection.
Disadvantage: R1 > R2 for the same level of Impact on ac and dc
protection, therefore rise and fall characteristics is minimized
times, propagation delays, and output
drives are severely affected. Disadvantage: More board area, higher initial cost
Note: These networks are useful for protecting the following
A digital inputs and outputs C 3–state outputs
B analog inputs and outputs D bidirectional (I/O) ports
PROPAGATION DELAY AND RISE TIME

vs. SERIES RESISTANCE
R [ t
where: C@k
R = the maximum allowable series resistance in ohms
t = the maximum tolerable propagation delay or rise time in seconds
C = the board capacitance plus the driven device’s
= input capacitance in farads
k = 0.7 for propagation delay calculations
k = 2.3 for rise time calculations
Figure 2. Networks for Minimizing ESD and Reducing

CMOS Latch Up Susceptibility
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4 NOTES: 1. 1/16 inch conductive sheet stock covering bench
top work area.
2. Ground strap.
1 3. Wrist strap in contact with skin.
4. Static neutralizer. (Ionized air blower directed at
work.) Primarily for use in areas where direct
grounding is impractical.
2
5. Room humidifier. Primarily for use in areas where
5 the relative humidity is less than 45%. Caution:
building heating and cooling systems usually dry
the air causing the relative humidity inside of
3 buildings to be less than outside humidity.
RESISTOR =
1 MEGAOHM
Figure 3. Typical Manufacturing Work Station
POWER SUPPLIES the possibility of latch–up related failures. This system

protection can be provided by the power supply filter and/or
CMOS devices have low power requirements and the voltage regulator.
ability to operate over a wide range of supply voltages. CMOS devices can be used with battery or battery backup
These two characteristics allow CMOS designs to be systems. A few precautions should be taken when designing
implemented using inexpensive, conventional power battery–operated systems:
supplies, instead of switching power supplies and power 1. The recommended power supply voltage should be
supplies with cooling fans. In addition, batteries may be used observed. For battery backup systems such as the one
as either a primary power source or for emergency backup. in Figure 5, the battery voltage must be at least 3.7
The absolute maximum power supply voltage for 14000 Volts (3 Volts from the minimum power supply
Series Metal–gate CMOS is 18.0 Vdc. Figure 4 offers some voltage and 0.7 Volts to account for the voltage drop
insight as to how this specification was derived. In the across the series diode).
figure, VS is the maximum power supply voltage and IS is 2. Inputs that might go above the battery backup voltage
the sustaining current of the latch–up mode. The value of VS should either use a series resistor to limit the input
was chosen so that the secondary breakdown effect may be current to less than 10 mA or use the MC14049UB or
avoided. MC14050B high–to–low voltage translators.
In an ideal system design, a power supply should be 3. Outputs that are subject to voltage levels above VDD
designed to deliver only enough current to insure proper or below VSS should be protected with a series resistor
operation of all devices. The obvious benefit of this type to limit the current to less than 10 mA or with
design is cost savings; an added benefit is protection against clamping diodes.
IDD
LATCH
UP MODE
SECONDARY
BREAKDOWN
LOW CURRENT
JUNCTION
IS
AVALANCHE
VS VDD
VS = DATA SHEET MAXIMUM SUPPLY RATING
Figure 4. Secondary Breakdown Characteristics
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POWER SUPPLY
BATTERY BACKUP
LINE POWER ONLY BATTERY BACKUP RECHARGE
SYSTEM SYSTEM
MC14049UB
CMOS CMOS
MC14050B
SYSTEM SYSTEM
MC14049UB
MC14050B
Figure 5. Battery Backup Interface
INPUTS VDD = 5.0 Vdc
All inputs, while in the recommended operating range

(VSS < Vin < VDD) can be modeled as shown in Figure 6. For
Vout , OUTPUT VOLTAGE (V)

input voltages in this range, diodes D1 and D2 are modeled SINGLE INPUT NAND, AND
as resistors, representing the reverse bias impedance of the MULTIPLE INPUT NOR, OR
5.0
diodes. The maximum input current is worst case, 1 µA,
when the inputs are at VDD or VSS, and VDD = 15.0 V. This 4.0 SINGLE INPUT NOR, OR
model does not apply to inputs with pull–up or pull–down MULTIPLE INPUT NAND, AND
3.0
resistors.
2.0
1.0
VDD 0
0 1.0 2.0 3.0 4.0 5.0
R1 = R2 = HIGH Z
Vin, INPUT VOLTAGE (V)
R1
Figure 7. Typical Transfer Characteristics
for Buffered Devices
R2 7.5 pF For these reasons, all unused inputs should be connected

either to VDD or VSS. For applications with inputs going to
edge connectors, a 100 kilohm resistor to VSS should be
Figure 6. Input Model for VSS vV vVin DD
used, as well as a series resistor for static protection and
current limiting (Figure 8). The 100 kilohm resistor will help
eliminate any static charges that might develop on the
printed circuit board. See Figure 2 for other possible
protection arrangements.
When left open–circuited, the inputs may self–bias at or
near the typical switchpoint, where both the P–channel and FROM RS CMOS
N–channel transistors are conducting, causing excessive EDGE
DEVICE
current drain. Due to the high gain of the inverters (see CONNECTOR
Figure 7), the device may also go into oscillation from any 100 k
noise in the system. Since CMOS devices dissipate the most
power during switching, this oscillation can cause very large
current drain and undesired switching. Figure 8. External Protection
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For input voltages outside of the recommended operating lout = 0 µA. The output drives for all buffered CMOS devices
range, the CMOS input is modeled as in Figure 9. The are such that 1 LSTTL load can be driven across the full
resistor–diode protection network allows the user greater temperature range.
v v
freedom when designing a worst case system. The device CMOS outputs are limited to externally forced output
inputs are guaranteed to withstand voltages from VSS – 0.5 voltages of VSS – 0.5 V Vout VDD + 0.5 V. When
V to VDD + 0.5 V and a maximum current of 10 mA. With voltages are forced outside of this range, a silicon controlled
the above input ratings, most designs will require no special rectifier (SCR) formed by parasitic transistors can be
terminations or design considerations. triggered, causing the device to latch up. For more
information on this, see the explanation of CMOS Latch Up
in this section.
The maximum rated output current for most outputs is
D1 10 mA. The output short–circuit currents of these devices
1.5 k typically exceed these limits. Care must be taken not to
exceed the maximum ratings found on every data sheet.
For applications that require driving high capacitive loads
D2 7.5 pF
where fast propagation delays are needed (e.g., driving
power MOSFETs), two or more outputs on the same chip
may be externally paralleled.
Figure 9. Input Model for Vin > VDD or Vin < VSS
CMOS LATCH UP
Other specifications that should be noted are the Latch up will not be a problem for most designs, but the
maximum input rise and fall times. Figure 10 shows the designer should be aware of it, what causes it, and how to
oscillations that may result from exceeding the 15 µs prevent it.
maximum rise and fall time at VDD = 5.0 V, 5 µs at 10 V, or Figure 11 shows the cross–section of a typical CMOS
4 µs at 15 V. As the voltage passes through the switching inverter and Figure 12 shows the parasitic bipolar devices.
threshold region with a slow rise time, any noise that is on The circuit formed by the parasitic transistors and resistors
the input is amplified, and passed through to the output, is the basic configuration of a silicon controlled rectifier, or
causing oscillations. The oscillation may have a low enough SCR. In the latch up condition, transistors Q1 and Q2 are
frequency to cause succeeding stages to switch, giving turned ON, each providing the base current necessary for the
unexpected results. If input rise or fall times are expected to other to remain in saturation, thereby latching the devices in
exceed 15 µs at 5.0 V, 5 µs at 10 V, or 4 µs at 15 V, the ON state. Unlike a conventional SCR, where the device
Schmitt–trigger devices such as the MC14093B, is turned ON by applying a voltage to the base of the NPN
MC14584B, MC14106B, HC14, or HC132 are transistor, the parasitic SCR is turned ON by applying a
recommended for squaring–up these slow transitions. voltage to the emitter of either transistor. The two emitters
that trigger the SCR are the same point, the CMOS output.
Therefore, to latch up the CMOS device, the output voltage
VDD must be greater than VDD + 0.5 V or less than VSS – 0.5 V
and have sufficient current to trigger the SCR. The latch–up
Vin
mechanism is similar for the inputs.
VSS
Once a CMOS device is latched up, if the supply current
is not limited, the device will be destroyed. Ways to prevent
such occurrences are listed below:
VOH 1. Insure that inputs and outputs are limited to the
v
maximum rated values, as follows:
Vout – 0.5 V ≤ Vin or Vout
v
VDD + 0.5 V (referenced to
VSS) |Iin or Iout| 10 mA (unless otherwise indicated
VOL
on the data sheet)
2. If voltage transients of sufficient energy to latch up the
device are expected on the inputs or outputs, external
Figure 10. Maximum Rise and Fall Time Violations protection diodes can be used to clamp the voltage.
Another method of protection is to use a series resistor
OUTPUTS to limit the expected worst case current to the
All CMOS B–Series outputs are buffered to insure maximum rating of 10 mA. (See Figure 2).
consistent output voltage and current performance. All 3. Sequence power supplies so that the inputs or outputs
buffered outputs have guaranteed output voltages of VOL = of CMOS devices are not active before the supply pins
0.05 V and VOH = VDD – 0.05 V for Vin = VDD or VSS and are powered up (e.g., recessed edge connectors and/or
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series resistors may be used in plug–in board 5. Limit the available power supply current to the
applications). devices that are subject to latch–up conditions. This
4. Voltage regulating or filtering should be used in board can be accomplished with the power supply filtering
design and layout to insure that power–supply lines network or with a current–limiting regulator.
are free of excessive noise.
P–CHANNEL N–CHANNEL
INPUT
VDD VDD P–CHANNEL N–CHANNEL VSS

OUTPUT
OUTPUT OUTPUT
N+
FIELD OXIDE ÇÇÇ
P+ P+
FIELD OXIDE
N+
ÇÇ N+ P+
FIELD OXIDE
N – SUBSTRATE P – WELL
Figure 11. CMOS Wafer Cross Section
Q1
N–CHANNEL OUTPUT
N+ N+ N– N–SUBSTRATE RESISTANCE
VDD
VSS N–
P–
P+
VDD
VSS P–
P–WELL RESISTANCE P+
Q2 P–CHANNEL OUTPUT
Figure 12. Latch Up Circuit Schematic
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CHAPTER 6
CMOS Logic Data Sheets
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MC14001B Series
B-Suffix Series CMOS Gates

MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
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The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure MARKING
(Complementary MOS). Their primary use is where low power DIAGRAMS
dissipation and/or high noise immunity is desired. 14
• Supply Voltage Range = 3.0 Vdc to 18 Vdc PDIP–14
MC140XXBCP
• All Outputs Buffered P SUFFIX
CASE 646 AWLYYWW
• Capable of Driving Two Low–power TTL Loads or One Low–power 1
Schottky TTL Load Over the Rated Temperature Range. 14
• Double Diode Protection on All Inputs Except: Triple Diode SOIC–14
140XXB
Protection on MC14011B and MC14081B D SUFFIX AWLYWW
• Pin–for–Pin Replacements for Corresponding CD4000 Series B
CASE 751A
1
Suffix Devices 14
TSSOP–14 14
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
DT SUFFIX 0XXB
Symbol Parameter Value Unit CASE 948G ALYW
VDD DC Supply Voltage Range – 0.5 to +18.0 V 1
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V 14
(DC or Transient) SOEIAJ–14
F SUFFIX MC140XXB
Iin, Iout Input or Output Current ± 10 mA AWLYWW
CASE 965
(DC or Transient) per Pin
1
PD Power Dissipation, 500 mW
per Package (Note 2.) XX = Specific Device Code
A = Assembly Location
TA Ambient Temperature Range – 55 to +125 °C WL or L = Wafer Lot
Tstg Storage Temperature Range – 65 to +150 °C YY or Y = Year
WW or W = Work Week
TL Lead Temperature 260 °C
(8–Second Soldering)
DEVICE INFORMATION
1. Maximum Ratings are those values beyond which damage to the device
may occur. Device Description
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14001B Quad 2–Input NOR Gate
This device contains protection circuitry to guard against damage due to high MC14011B Quad 2–Input NAND Gate
static voltages or electric fields. However, precautions must be taken to avoid
MC14023B Triple 3–Input NAND Gate
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) vVDD.
MC14025B Triple 3–Input NOR Gate
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14071B Quad 2–Input OR Gate
either VSS or VDD). Unused outputs must be left open.
MC14073B Triple 3–Input AND Gate
MC14081B Quad 2–Input AND Gate
MC14082B Dual 4–Input AND Gate
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 39 of this data sheet.
 Semiconductor Components Industries, LLC, 2000 32 Publication Order Number:

March, 2000 – Rev. 1 MC14001B/D
MC14001B Series
LOGIC DIAGRAMS
NOR NAND OR AND
MC14001B MC14011B MC14071B MC14081B

Quad 2–Input NOR Gate Quad 2–Input NAND Gate Quad 2–Input OR Gate Quad 2–Input AND Gate
1 1 1 1
3 3 3 3
2 2 2 2
5 5 5 5
2 INPUT
4 4 4 4
6 6 6 6
8 8 8 8
10 10 10 10
9 9 9 9
12 12 12 12
11 11 11 11
13 13 13 13
MC14025B MC14023B MC14073B MC14082B

Triple 3–Input NOR Gate Triple 3–Input NAND Gate Triple 3–Input AND Gate Dual 4–Input AND Gate
1 1 1 2
2 9 2 9 2 9
3 1
8 8 8
4
3 INPUT
3 3 3 5
4 6 4 6 4 6 9
5 5 5
10 13
11 11 11 11
12 10 12 10 12 10 12
13 13 13 NC = 6, 8
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
PIN ASSIGNMENTS
MC14001B MC14011B MC14023B MC14025B
Quad 2–Input NOR Gate Quad 2–Input NAND Gate Triple 3–Input NAND Gate Triple 3–Input NOR Gate
IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD

IN 2A 2 13 IN 2D IN 2A 2 13 IN 2D IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C
OUTA 3 12 IN 1D OUTA 3 12 IN 1D IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C
OUTB 4 11 OUTD OUTB 4 11 OUTD IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C
IN 1B 5 10 OUTC IN 1B 5 10 OUTC IN 3B 5 10 OUTC IN 3B 5 10 OUTC
IN 2B 6 9 IN 2C IN 2B 6 9 IN 2C OUTB 6 9 OUTA OUTB 6 9 OUTA
VSS 7 8 IN 1C VSS 7 8 IN 1C VSS 7 8 IN 3A VSS 7 8 IN 3A
MC14071B MC14073B MC14081B MC14082B

Quad 2–Input OR Gate Triple 3–Input AND Gate Quad 2–Input AND Gate Dual 4–Input AND Gate
IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD OUTA 1 14 VDD
IN 2A 2 13 IN 2D IN 2A 2 13 IN 3C IN 2A 2 13 IN 2D IN 1A 2 13 OUTB
OUTA 3 12 IN 1D IN 1B 3 12 IN 2C OUTA 3 12 IN 1D IN 2A 3 12 IN 4B
OUTB 4 11 OUTD IN 2B 4 11 IN 1C OUTB 4 11 OUTD IN 3A 4 11 IN 3B
IN 1B 5 10 OUTC IN 3B 5 10 OUTC IN 1B 5 10 OUTC IN 4A 5 10 IN 2B
IN 2B 6 9 IN 2C OUTB 6 9 OUTA IN 2B 6 9 IN 2C NC 6 9 IN 1B
VSS 7 8 IN 1C VSS 7 8 IN 3A VSS 7 8 IN 1C VSS 7 8 NC
NC = NO CONNECTION
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MC14001B Series
ÎÎÎÎÎÎÎÎÎÎ
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
ÎÎÎÎ
ÎÎÎ
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ÎÎÎÎÎ ÎÎÎ
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ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
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Characteristic Symbol Vdc Min Max Min Typ (3.) Max Min Max Unit
ÎÎÎÎ
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ÎÎÎÎ
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ÎÎÎ
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Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
ÎÎÎÎ
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ÎÎÎ
ÎÎÎÎ
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ÎÎÎÎ
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Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
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ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
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Vin = 0 or VDD ÎÎÎ
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ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
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VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
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15 14.95 — 14.95 15 — 14.95 —
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Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ

ÎÎÎÎ
(VOL = 0.4 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ Sink IOL
15
5.0
– 4.2
0.64
—
—
– 3.4
0.51
– 8.8
0.88
—
—
– 2.4
0.36
—
— mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎ
Input Capacitance
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
Quiescent Current
ÎÎÎÎ ÎÎÎ ÎÎÎÎ
ÎÎÎ
(Per Package) ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
Total Supply Current (4.) (5.)
(Dynamic plus Quiescent,
ÎÎÎ
IT 5.0
10
IT = (0.3 µA/kHz) f + IDD/N
IT = (0.6 µA/kHz) f + IDD/N
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Per Gate, CL = 50 pF) 15 IT = (0.9 µA/kHz) f + IDD/N
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
4. The formulas given are for the typical characteristics only at 25_C.
5. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
per package.
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34
MC14001B Series
B–SERIES GATE SWITCHING TIMES
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Characteristic Symbol
VDD
Vdc Min Typ (7.) Max Unit
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Rise Time, All B–Series Gates
ÎÎÎÎ
ÎÎÎ
tTLH = (1.35 ns/pF) CL + 33 ns
tTLH
5.0 — 100 200
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH = (0.60 ns/pF) CL + 20 ns 10 — 50 100
tTLH = (0.40 ns/PF) CL + 20 ns 15 — 40 80
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Fall Time, All B–Series Gates
ÎÎÎÎ
ÎÎÎ
tTHL = (1.35 ns/pF) CL + 33 ns
tTHL
5.0 — 100 200
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.60 ns/pF) CL + 20 ns 10 — 50 100
tTHL = (0.40 ns/pF) CL + 20 ns 15 — 40 80
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
Propagation Delay Time
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
MC14001B, MC14011B only ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.90 ns/pF) CL + 80 ns 5.0 — 125 250
tPLH, tPHL = (0.36 ns/pF) CL + 32 ns 10 — 50 100
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
All Other 2, 3, and 4 Input Gates
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
8–Input Gates (MC14068B, MC14078B)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
14 VDD 20 ns 20 ns
VDD
INPUT 90%
INPUT 50%
PULSE 10% 0V
OUTPUT tPHL tPLH
GENERATOR
CL 90% VOH
* 50%
OUTPUT 10%
INVERTING VOL
tTHL tTLH
tPLH tPHL
7 VSS OUTPUT VOH
90%
NON–INVERTING 50%
*All unused inputs of AND, NAND gates must be connected to VDD. 10% VOL
All unused inputs of OR, NOR gates must be connected to VSS. tTLH tTHL
Figure 1. Switching Time Test Circuit and Waveforms
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35
MC14001B Series
CIRCUIT SCHEMATIC
NOR, OR GATES
MC14001B, MC14071B MC14025B

One of Four Gates Shown One of Three Gates Shown
VDD VDD
14 VDD
1, 6, 8, 13 1, 3, 11
*
2, 5, 9, 12 2, 4, 12
14 VDD
3, 4, 10, 11
VSS
7 VSS 9, 6, 10
VSS
VDD
*Inverter omitted in MC14001B
8, 5, 13
7 VSS
VSS
CIRCUIT SCHEMATIC
NAND, AND GATES
MC14023B, MC14073B MC14011B, MC14081B

One of Three Gates Shown One of Four Gates Shown
VDD 14 VDD
3, 4, 10, 11
2, 4, 12 14 VDD 2, 5, 9, 12
1, 3, 11 1, 6, 8, 13
VSS 7 VSS
* *Inverter omitted in MC14011B
VDD
9, 6, 10
8, 5, 13
7 VSS
VSS
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36
MC14001B Series
TYPICAL B–SERIES GATE CHARACTERISTICS
N–CHANNEL DRAIN CURRENT (SINK) P–CHANNEL DRAIN CURRENT (SOURCE)

5.0 – 10
– 9.0
4.0 – 8.0 TA = – 55°C
ID , DRAIN CURRENT (mA)

– 7.0
TA = – 55°C – 40°C
3.0 – 6.0
– 40°C
– 5.0
+ 85°C + 25°C + 25°C
2.0 – 4.0 + 85°C
+ 125°C
– 3.0 + 125°C
1.0 – 2.0
– 1.0
0 0
0 1.0 2.0 3.0 4.0 5.0 0 – 1.0 – 2.0 – 3.0 – 4.0 – 5.0
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)
Figure 2. VGS = 5.0 Vdc Figure 3. VGS = – 5.0 Vdc
20 – 50
18 – 45
TA = – 55°C
16 – 40
14 – 40°C – 35
12 + 25°C – 30 TA = – 55°C
+ 85°C
10 – 25 – 40°C
8.0 + 125°C – 20 + 25°C
+ 85°C
6.0 – 15
4.0 – 10 + 125°C
2.0 – 5.0
0 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 – 1.0 – 2.0 – 3.0 – 4.0 – 5.0 – 6.0 – 7.0 – 8.0 – 9.0 – 10
Figure 4. VGS = 10 Vdc Figure 5. VGS = – 10 Vdc
50 – 100
45 – 90
40 – 80
35 TA = – 55°C – 70
30 – 40°C – 60
TA = – 55°C
25 + 25°C – 50 – 40°C
20 + 85°C – 40 + 25°C
+ 125°C + 85°C
15 – 30
+ 125°C
10 – 20
5.0 – 10
0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 0 – 2.0 – 4.0 – 6.0 – 8.0 – 10 – 12 – 14 – 16 – 18 – 20
Figure 6. VGS = 15 Vdc Figure 7. VGS = – 15 Vdc

These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
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37
MC14001B Series
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS

V out , OUTPUT VOLTAGE (Vdc)

SINGLE INPUT NAND, AND SINGLE INPUT NAND, AND
5.0 MULTIPLE INPUT NOR, OR MULTIPLE INPUT NOR, OR
10
4.0 8.0
SINGLE INPUT NOR, OR SINGLE INPUT NOR, OR
3.0 MULTIPLE INPUT NAND, AND 6.0 MULTIPLE INPUT NAND, AND
2.0 4.0
1.0 2.0
0 0
0 1.0 2.0 3.0 4.0 5.0 0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)
Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc
16 DC NOISE MARGIN
SINGLE INPUT NAND, AND
14 MULTIPLE INPUT NOR, OR The DC noise margin is defined as the input voltage range
12 from an ideal “1” or “0” input level which does not produce
SINGLE INPUT NOR, OR output state change(s). The typical and guaranteed limit
10 MULTIPLE INPUT NAND, AND values of the input values VIL and VIH for the output(s) to
8.0
be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
6.0 in Figure 11.
Guaranteed minimum noise margins for both the “1” and
4.0
“0” levels =
2.0 1.0 V with a 5.0 V supply
0 2.0 V with a 10.0 V supply
0 2.0 4.0 6.0 8.0 10
2.5 V with a 15.0 V supply
Vin, INPUT VOLTAGE (Vdc)
Figure 10. VDD = 15 Vdc
Vout VDD Vout VDD
VO VO
VO VO
VDD VDD
0 Vin 0 Vin
VIL VIH VIL VIH

VSS = 0 VOLTS DC
(a) Inverting Function (b) Non–Inverting Function
Figure 11. DC Noise Immunity
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38
MC14001B Series
ORDERING & SHIPPING INFORMATION: ORDERING & SHIPPING INFORMATION:

Device Package Shipping Device Package Shipping
MC14001BCP PDIP–14 2000 Units per Box MC14071BCP PDIP–14 2000 Units per Box
MC14001BD SOIC–14 2750 Units per Box MC14071BD SOIC–14 55 Units per Rail
MC14001BDR2 SOIC–14 2500 Units / Tape & Reel MC14071BDR2 SOIC–14 2500 Units / Tape & Reel
MC14001BDT TSSOP–14 96 Units per Rail MC14071BDT TSSOP–14 96 Units per Rail
MC14001BDTR2 TSSOP–14 96 Units per Rail MC14071BDTR2 TSSOP–14 96 Units per Rail
MC14011BCP PDIP–14 2000 Units per Box MC14073BCP PDIP–14 2000 Units per Box
MC14011BD SOIC–14 2750 Units per Box MC14073BD SOIC–14 55 Units per Rail
MC14011BDR2 SOIC–14 2500 Units / Tape & Reel MC14073BDR2 SOIC–14 2500 Units / Tape & Reel
MC14011BDT TSSOP–14 96 Units per Rail
MC14011BDTEL TSSOP–14 2000 Units / Tape & Reel MC14081BCP PDIP–14 2000 Units per Box
MC14011BDTR2 TSSOP–14 50 Units per Rail MC14081BD SOIC–14 55 Units per Rail
MC14081BDR2 SOIC–14 2500 Units / Tape & Reel
MC14023BCP PDIP–14 2000 Units per Box MC14081BDT TSSOP–14 96 Units per Rail
MC14023BD SOIC–14 2750 Units per Box MC14081BDTR2 TSSOP–14 2500 Units / Tape & Reel
MC14082BCP PDIP–14 2000 Units per Box
MC14025BCP PDIP–14 2000 Units per Box MC14082BD SOIC–14 55 Units per Rail
MC14025BD SOIC–14 2750 Units per Box MC14082BDR2 SOIC–14 2500 Units / Tape & Reel
MC14025BDR2 SOIC–14 2500 Units / Tape & Reel For ordering information on the EIAJ version of the SOIC pack-
ages, please contact your local ON Semiconductor representa-
tive.
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39
MC14001UB, MC14011UB
UB-Suffix Series
CMOS Gates
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired. The UB set of http://onsemi.com
CMOS gates are inverting non–buffered functions.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc MC14001UB
• Linear and Oscillator Applications Quad 2–Input NOR Gate
• Capable of Driving Two Low–power TTL Loads or One Low–power MC14011UB
Schottky TTL Load Over the Rated Temperature Range
Quad 2–Input NAND Gate
• Double Diode Protection on All Inputs
• Pin–for–Pin Replacements for Corresponding CD4000 Series UB
Suffix Devices
MARKING
DIAGRAMS
14
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) PDIP–14
P SUFFIX MC140XXUBCP
Symbol Parameter Value Unit CASE 646 AWLYYWW
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V

(DC or Transient) 14
Iin, Iout Input or Output Current ± 10 mA SOIC–14
140XXU
(DC or Transient) per Pin D SUFFIX AWLYWW
CASE 751A
PD Power Dissipation, 500 mW 1
per Package (Note 2.)
TA Ambient Temperature Range – 55 to +125 °C
Tstg Storage Temperature Range – 65 to +150 °C XX = Specific Device Code
WL or L = Wafer Lot
YY or Y = Year
1. Maximum Ratings are those values beyond which damage to the device WW or W = Work Week
may occur.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid Device Package Shipping
high–impedance circuit. For proper operation, Vin and Vout should be constrained MC14001UBCP PDIP–14 2000/Box
MC14001UBD SOIC–14 55/Rail
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open. MC14001UBDR2 SOIC–14 2500/Tape & Reel
MC14011UBCP PDIP–14 2000/Box
MC14011UBD SOIC–14 55/Rail
MC14011UBDR2 SOIC–14 2500/Tape & Reel

March, 2000 – Rev. 3 MC14001UB/D
LOGIC DIAGRAMS
MC14001UB MC14011UB
Quad 2–Input Quad 2–Input
NOR Gate NAND Gate
1 1
3 3
2 2
5 5
4 4
6 6
8 8
10 10
9 9
12 12
11 11
13 13
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
PIN ASSIGNMENTS
MC14001UB MC14011UB
Quad 2–Input NOR Gate Quad 2–Input NAND Gate
IN 1A 1 14 VDD IN 1A 1 14 VDD
IN 2A 2 13 IN 2D IN 2A 2 13 IN 2D
OUTA 3 12 IN 1D OUTA 3 12 IN 1D
OUTB 4 11 OUTD OUTB 4 11 OUTD
IN 1B 5 10 OUTC IN 1B 5 10 OUTC
IN 2B 6 9 IN 2C IN 2B 6 9 IN 2C
VSS 7 8 IN 1C VSS 7 8 IN 1C
http://onsemi.com
41
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Vin = 0 or VDD
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 Vdc) 5.0 — 1.0 — 2.25 1.0 — 1.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 Vdc) 10 — 2.0 — 4.50 2.0 — 2.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 Vdc) 15 — 2.5 — 6.75 2.5 — 2.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 Vdc) “1” Level IIH 5.0 4.0 — 4.0 2.75 — 4.0 — Vdc
(VO = 1.0 Vdc) 10 8.0 — 8.0 5.50 — 8.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 Vdc) 15 12.5 — 12.5 8.25 — 12.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Total Supply Current (4.) (5.) IT 5.0 IT = (0.3 µA/kHz) f + IDD/N µAdc
(Dynamic plus Quiescent, 10 IT = (0.6 µA/kHz) f + IDD/N
ÎÎÎÎ
ÎÎÎ
Per Gate CL = 50 pF)
ÎÎÎ 15 IT = (0.8 µA/kHz) f + IDD/N
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
per package.
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42
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Min Typ (7.) Max Unit
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Rise Time tTLH ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 180
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Fall Time tTHL ns
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time tPLH, tPHL ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
20 ns 20 ns
VDD
14 INPUT VDD
90%
50%
PULSE INPUT OUTPUT 10% 0V
GENERATOR tPHL tPLH
* CL 90% VOH
OUTPUT 50%
INVERTING
10% VOL
7 VSS
*All unused inputs of AND, NAND gates must be tTHL tTLH
connected to VDD.
All unused inputs of OR, NOR gates must be
connected to VSS.
http://onsemi.com
43
MC14001UB CIRCUIT SCHEMATIC MC14011UB CIRCUIT SCHEMATIC

(1/4 of Device Shown)
VDD
3 14 10
14 VDD
1 8
2 9
3, 4, 10, 11
1, 6, 8, 13
2, 5, 9, 12
6 13 7 VSS
5 12
4 7 11
VSS
16 16
VDD = 15 Vdc TA = + 25°C VDD = 15 Vdc Unused input
14 Unused input 14 connected to
b
Vout , OUTPUT VOLTAGE (Vdc)

connected to a VSS.
I D, DRAIN CURRENT (mAdc)
12 VSS. 12
10 Vdc a One input only 10 Vdc a TA = + 125°C
10 b Both inputs 10
b TA = – 55°C
8.0 8.0 8.0
b a a b
6.0 6.0 6.0
5.0 Vdc 5.0 Vdc
15 Vdc
4.0 b a 4.0 4.0
a 10 Vdc a b
b
2.0 2.0 2.0
0 0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 0 2.0 4.0 6.0 8.0 10 12 14 16
Figure 2. Typical Voltage and Figure 3. Typical Voltage Transfer

Current Transfer Characteristics Characteristics versus
Temperature
0 10
c a 15 Vdc
b a
VGS = – 5.0 Vdc c
– 2.0 8.0
b VGS = 10 Vdc
a b
a TA = – 55°C
b TA = + 25°C c
– 4.0 6.0
c TA = + 125°C
a TA = – 55°C
c b TA = + 25°C
– 6.0 4.0 c TA = + 125°C
– 10 Vdc b
c a
– 8.0 b – 15 Vdc 2.0
b 5.0 Vdc
c
a a
– 10 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0 2.0 4.0 6.0 8.0 10
VDS, DRAIN VOLTAGE (Vdc) VDS, DRAIN VOLTAGE (Vdc)
Figure 4. Typical Output Source Figure 5. Typical Output Sink

Characteristics Characteristics
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44
MC14007UB
Dual Complementary Pair
Plus Inverter
The MC14007UB multi–purpose device consists of three
N–channel and three P–channel enhancement mode devices packaged
to provide access to each device. These versatile parts are useful in
inverter circuits, pulse–shapers, linear amplifiers, high input http://onsemi.com
impedance amplifiers, threshold detectors, transmission gating, and
functional gating. MARKING
DIAGRAMS
• Diode Protection on All Inputs 14
• Capable of Driving Two Low–power TTL Loads or One Low–power P SUFFIX MC14007UBCP
AWLYYWW
CASE 646
• Pin–for–Pin Replacement for CD4007A or CD4007UB
1
• This device has 2 outputs without ESD Protection. Anti–static 14

SOIC–14
precautions must be taken. 14007U
D SUFFIX AWLYWW
CASE 751A
1
14
TSSOP–14 14
Symbol Parameter Value Unit
DT SUFFIX 007U
VDD DC Supply Voltage Range – 0.5 to +18.0 V CASE 948G ALYW
(DC or Transient)
14
Iin, Iout Input or Output Current ± 10 mA SOEIAJ–14
(DC or Transient) per Pin F SUFFIX MC14007U
CASE 965 AWLYWW
1
Tstg Storage Temperature Range – 65 to +150 °C WL or L = Wafer Lot
YY or Y = Year
TL Lead Temperature 260 °C WW or W = Work Week
may occur. ORDERING INFORMATION
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Device Package Shipping
This device contains protection circuitry to guard against damage due to high MC14007UBCP PDIP–14 2000/Box
applications of any voltage higher than maximum rated voltages to this MC14007UBD SOIC–14 55/Rail
to the range VSS v (Vin or Vout) vVDD. MC14007UBDR2 SOIC–14 2500/Tape & Reel
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14007UBDT TSSOP–14 96/Rail
MC14007UBF SOEIAJ–14 See Note 1.
MC14007UBFEL SOEIAJ–14 See Note 1.
1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local
ON Semiconductor representative.

MC14007UB
PIN ASSIGNMENT
D–PB 1 14 VDD
S–PB 2 13 D–PA
GATEB 3 12 OUTC
S–NB 4 11 S–PC
D–NB 5 10 GATEC
GATEA 6 9 S–NC
VSS 7 8 D–NA
D = DRAIN
S = SOURCE
SCHEMATIC
14 13 2 1 11
6 12
7 8 3 4 5 10 9
VDD = PIN 14
VSS = PIN 7
A A
B 12 9
1 B
2
C 3
INPUT 4
VDD 5
14 C
11
13
INPUT OUTPUT CONDITION INPUT
6 8 10
1 A = C, B = OPEN
0 A = B, C = OPEN
7 VSS
Substrates of P–channel devices internally
connected to VDD; substrates of N–channel
devices internally connected to VSS.
Figure 1. Typical Application: 2–Input Analog Multiplexer
http://onsemi.com
46
MC14007UB
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 Vdc) 5.0 — 1.0 — 2.25 1.0 — 1.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 Vdc) 10 — 2.0 — 4.50 2.0 — 2.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 Vdc) 15 — 2.5 — 6.75 2.5 — 2.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 Vdc) “1” Level VIH 5.0 4.0 — 4.0 2.75 — 4.0 — Vdc
(VO = 1.0 Vdc) 10 8.0 — 8.0 5.50 — 8.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 Vdc) 15 12.5 — 12.5 8.25 — 12.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 5.0 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 1.0 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.5 — – 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 10 — – 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 1.0 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.5 — 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 10 — 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 0.25 — 0.0005 0.25 — 7.5
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current (5.) (6.) IT 5.0 IT = (0.7 µA/kHz) f + IDD/6 µAdc
IT = (1.4 µA/kHz) f + IDD/6
ÎÎÎÎ
ÎÎÎ
(Dynamic plus Quiescent, 10
Per Gate) (CL = 50 pF) 15 IT = (2.2 µA/kHz) f + IDD/6
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.
http://onsemi.com
47
MC14007UB
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH = (1.2 ns/pF) CL + 30 ns 5.0 — 90 180
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
10
15
—
—
45
35
90
70
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (1.2 ns/pF) CL + 15 ns 5.0 — 75 150
tTHL = (0.5 ns/pF) CL + 15 ns 10 — 40 80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.4 ns/pF) CL + 10 ns 15 — 30 60
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Turn–Off Delay Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ

ÎÎÎÎ
ÎÎÎ
tPLH = (1.5 ns/pF) CL + 35 ns
tPLH
5.0 —
—
60 125
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH = (0.2 ns/pF) CL + 20 ns 10 30 75
tPLH = (0.15 ns/pF) CL + 17.5 ns 15 — 25 55
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Turn–On Delay Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ

ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL = (1.0 ns/pF) CL + 10 ns
tPHL
5.0 — 60 125
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL = (0.3 ns/pF) CL + 15 ns 10 — 30 75
tPHL = (0.2 ns/pF) CL + 15 ns 15 — 25 55
7. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.
VDD = – VGS VDD = VGS
14
IOH VDS = VOH – VDD 14
IOL VDS = VOL
7 VSS
7 VSS
All unused inputs connected to ground. All unused inputs connected to ground.
0 20
a VGS = 15 Vdc
b
c
c
IOL , DRAIN CURRENT (mAdc)
IOH , DRAIN CURRENT (mAdc)
– 4.0 16
VGS = – 5.0 Vdc b a
10 Vdc
– 8.0 a TA = – 55°C a 12
b TA = + 25°C b c
c TA = + 125°C a TA = – 55°C
c b
– 12 8.0 b TA = + 25°C
b c TA = + 125°C
c
– 10 Vdc a – 15 Vdc a
– 16 4.0
a b 5.0 Vdc
c
– 20 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 –0 0 2.0 4.0 6.0 8.0 10
Figure 2. Typical Output Source Characteristics Figure 3. Typical Output Sink Characteristics
These typical curves are not guarantees, but are design aids.
Caution: The maximum current rating is 10 mA per pin.
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48
MC14007UB
VDD
20 ns 20 ns
0.01 µF VDD
90%
500 µF ID CERAMIC Vin 50%
10% VSS
14 tPHL tPLH
PULSE Vin VOH
Vout 90%
GENERATOR Vout 50%
7 VSS CL 10%
VOL
tTHL tTLH
Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms
APPLICATIONS
The MC14007UB dual pair plus inverter, which has VDD

14 OUT = A+B•C
access to all its elements offers a number of unique circuit
applications. Figures 1, 5, and 6 are a few examples of the
device flexibility.
13
+ VDD 11 2
2
DISABLE 3
10 12 1
B OUTPUT
1 8
11
9 7
5
INPUT 10 12 OUTPUT
3
C
9 4
8
6
A
DISABLE 6
7
Substrates of P–channel devices internally connected to VDD;
Substrates of N–channel devices internally connected to VSS.
INPUT DISABLE OUTPUT
1 0 0 Figure 6. AOI Functions Using Tree Logic
0 0 1
X 1 OPEN
X = Don’t Care
Figure 5. 3–State Buffer
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49
MC14008B
4-Bit Full Adder

The MC14008B 4–bit full adder is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. This device consists of four full adders with fast
internal look–ahead carry output. It is useful in binary addition and
other arithmetic applications. The fast parallel carry output bit allows
http://onsemi.com
high–speed operation when used with other adders in a system.
• Look–Ahead Carry Output
• Diode Protection on All Inputs MARKING
DIAGRAMS
• All Outputs Buffered
16
• Capable of Driving Two Low–power TTL Loads or One Low–power P SUFFIX MC14008BCP
AWLYYWW
Schottky TTL Load Over the Rated Temperature Range CASE 648
• Pin–for–Pin Replacement for CD4008B 1
16
SOIC–16
14008B
D SUFFIX AWLYWW
CASE 751B
Symbol Parameter Value Unit 1
VDD DC Supply Voltage Range – 0.5 to +18.0 V
F SUFFIX MC14008B
(DC or Transient) per Pin CASE 966

TA Ambient Temperature Range – 55 to +125 °C A = Assembly Location
WL or L = Wafer Lot
WW or W = Work Week
This device contains protection circuitry to guard against damage due to high MC14008BCP PDIP–16 2000/Box
applications of any voltage higher than maximum rated voltages to this MC14008BDR2 SOIC–16 2500/Tape & Reel
to the range VSS v (Vin or Vout) vVDD. MC14008BF SOEIAJ–16 See Note 1.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., 1. For ordering information on the EIAJ version of
either VSS or VDD). Unused outputs must be left open. the SOIC packages, please contact your local

March, 2000 – Rev. 3 MC14008B/D
MC14008B
TRUTH TABLE
(One Stage)
Cin B A Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
PIN ASSIGNMENT
A4 1 16 VDD
B3 2 15 B4
A3 3 14 Cout
B2 4 13 S4
A2 5 12 S3
B1 6 11 S2
A1 7 10 S1
VSS 8 9 Cin
BLOCK DIAGRAM
HIGH–SPEED
14 Cout
PARALLEL CARRY
B4 15 ADDER
13 S4
A4 1 4
C4
B3 2 ADDER
12 S3
A3 3 3
C3
B2 4 ADDER
11 S2
A2 5 2
C2
B1 6 ADDER
10 S1
A1 7 1
VDD = PIN 16
Cin 9 VSS = PIN 8
http://onsemi.com
51
MC14008B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Î
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150
(Per Package) 10 — 10 — 0.010 10 — 300
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
ÎÎÎÎ
ÎÎÎ
Total Supply Current (5.) (6.) IT 5.0 IT = (1.7 µA/kHz) f + IDD µAdc
IT = (3.4 µA/kHz) f + IDD
ÎÎÎÎ
ÎÎÎ
Per Package) 15 IT = (5.0 µA/kHz) f + IDD
ÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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52
MC14008B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
ÎÎÎÎ
ÎÎÎ
10
15
—
—
50
40
100
80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Sum in to Sum Out
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Sum In to Carry Out
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 220 ns
ÎÎÎÎ
ÎÎÎ
5.0
10
—
—
305
145
610
290
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Carry In to Sum Out
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Carry In to Carry Out
ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 85 ns 5.0 —
—
170 340
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 75 150
tPLH, tPHL = (0.5 ns/pF) CL + 30 ns —
15 55 110
VDD = – VGS Vout VDD = VGS Vout
16 16
B4 S4 B4 S4
A4 A4
B3 S3 B3 S3
A3 A3
B2 S2 B2 S2
A2 A2
B1 S1 IOH B1 S1 IOL
A1 A1
Cin Cout Cin Cout
EXTERNAL EXTERNAL
8 VSS POWER 8 VSS POWER
SUPPLY SUPPLY
Figure 1. Typical Source Current Figure 2. Typical Sink Current

Characteristics Test Circuit Characteristics Test Circuit
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53
MC14008B
VDD
16
B4 S4
A4
B3 S3
20 ns 20 ns A3
B2 S2
VDD A2
90% CL
Vin B1 S1
10% VSS CL
A1
PULSE CL
Cin Cout
GENERATOR CL
CL
8 VSS
500 µF IDD
Figure 3. Dynamic Power Dissipation Test Circuit and Waveform
VDD
16
B4 S4
A4
B3 S3
A3
B2 S2
A2
B1 S1 CL
A1 CL
PULSE CL
Cin Cout
GENERATOR CL
8 VSS CL
IDD
20 ns 20 ns
VDD
90%
Cin 50%
10% VSS
tPHL tPLH
90% VOH
S1 – S4 50%
10% VOL
tTHL tTLH
VOH
Cout 50%
VOL
tPLH tPHL
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54
MC14008B
Cout
B4
S4
A4
B3
S3
A3
B2
S2
A2
B1
S1
A1
Cin
Figure 5. Logic Diagram
TYPICAL APPLICATION
WORD A + B INPUTS
A1 B4 A1 B4 A1 B4 A1 B4
CHIP CHIP CHIP CHIP

Cin Cout Cin Cout Cin Cout Cin Cout
1 2 3 4
S1 S4 S1 S4 S1 S4 S1 S4
SUM OUTPUTS
Calculation of 16–bit adder speed:
tP total = tP (Sum to Carry) + tP (Carry to Sum) + 2 tP (Carry to Carry)
The guaranteed 16–bit adder speed at 10 V, 25°C, CL = 50 pF is:
tp total = 290 + 310 + 300 = 900 ns
Figure 6. Using the MC14008B in a 16–Bit Adder Configuration
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55
MC14013B
Dual Type D Flip-Flop

The MC14013B dual type D flip–flop is constructed with MOS
monolithic structure. Each flip–flop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register
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elements or as type T flip–flops for counter and toggle applications.
• Static Operation MARKING
• Diode Protection on All Inputs DIAGRAMS
• Supply Voltage Range = 3.0 Vdc to 18 Vdc 14
• Logic Edge–Clocked Flip–Flop Design

PDIP–14
P SUFFIX MC14013BCP
Logic state is retained indefinitely with clock level either high or low; CASE 646 AWLYYWW
information is transferred to the output only on the positive–going 1
edge of the clock pulse
14
• Capable of Driving Two Low–power TTL Loads or One Low–power SOIC–14
14013B
Schottky TTL Load Over the Rated Temperature Range D SUFFIX AWLYWW
• Pin–for–Pin Replacement for CD4013B CASE 751A
1
14
TSSOP–14 14
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) DT SUFFIX 013B
Symbol Parameter Value Unit CASE 948G ALYW

F SUFFIX MC14013B
CASE 965
1
per Package (Note 3.) A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
Tstg Storage Temperature Range – 65 to +150 °C WW or W = Work Week
may occur. Device Package Shipping
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14013BCP PDIP–14 2000/Box
This device contains protection circuitry to guard against damage due to high MC14013BD SOIC–14 55/Rail
MC14013BDT TSSOP–14 96/Rail
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14013BDTR2 TSSOP–14 2500/Tape & Reel
MC14013BF SOEIAJ–14 See Note 1.
MC14013BFEL SOEIAJ–14 See Note 1.


March, 2000 – Rev. 3 MC14013B/D
MC14013B
TRUTH TABLE
Inputs Outputs
Clock† Data Reset Set Q Q
0 0 0 0 1
1 0 0 1 0
X 0 0 Q Q No
Change
X X 1 0 0 1
X X 0 1 1 0
X X 1 1 1 1
X = Don’t Care
† = Level Change
PIN ASSIGNMENT
QA 1 14 VDD
QA 2 13 QB
CA 3 12 QB
RA 4 11 CB
DA 5 10 RB
SA 6 9 DB
VSS 7 8 SB
BLOCK DIAGRAM
S
5 D Q 1
3 C Q 2
R
S
9 D Q 13
11 C Q 12
R
10
VDD = PIN 14
VSS = PIN 7
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57
MC14013B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Î
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 2.0 — 0.004 2.0 — 60
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 4.0 — 0.006 4.0 — 120
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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58
MC14013B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Characteristic Symbol VDD Min Typ (8.) Max Unit
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
10
15
—
—
50
40
100
80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time tPLH ns
Clock to Q, Q tPHL
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 50 100
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Set to Q, Q
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
5.0
10
15
—
—
—
175
75
50
350
150
100
ÎÎÎÎÎ
Reset to Q, Q
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Setup Times (9.)
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tsu 5.0
10
40
20
20
10
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 15 7.5 —
Hold Times (9.)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
th 5.0 40 20 — ns
10 20 10 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 15 7.5 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Pulse Width tWL, tWH 5.0 250 125 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 100 50 —
15 70 35 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
Clock Pulse Frequency
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fcl 5.0
10
15
—
—
—
4.0
10
14
2.0
5.0
7.0
MHz
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Clock Pulse Rise and Fall Time
ÎÎÎÎ
ÎÎÎ
tTLH
tTHL
5.0
10
—
—
—
—
15
5.0
µs
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — — 4.0
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Set and Reset Pulse Width tWL, tWH 5.0 250 125 — ns
10 100 50 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 70 35 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Removal Times trem ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Set 5 80 0 —
10 45 5 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 35 5 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset 5 50 – 35 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 30 – 10 —
15 25 –5 —
9. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.
LOGIC DIAGRAM (1/2 of Device Shown)

S
C C Q
C C Q
C C
C C
C C
C
R
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59
MC14013B
20 ns 20 ns
VDD
90%
D 50%
10% 20 ns 20 ns
tsu (L) VSS
tsu (H) 90% VDD
th 20 ns SET OR
VDD 50%
90% RESET 10%
C 50% VSS
10% tw trem
VSS 20 ns 20 ns
tWH tWL 90% VDD
CLOCK 50%
1 10%
VSS
fcl
tPLH tPHL tPLH tw
VOH tPHL
90%
Q 50% VOH
10% VOL Q OR Q 50%
VOL
tTLH tTHL
Inputs R and S low.
Figure 1. Dynamic Signal Waveforms Figure 2. Dynamic Signal Waveforms

(Data, Clock, and Output) (Set, Reset, Clock, and Output)
TYPICAL APPLICATIONS
n–STAGE SHIFT REGISTER

1 2 nth
D D Q D Q D Q Q
C Q C Q C Q
CLOCK
BINARY RIPPLE UP–COUNTER (Divide–by–2n)

1 2 nth
D Q D Q D Q Q
CLOCK C Q C Q C Q
T FLIP–FLOP
MODIFIED RING COUNTER (Divide–by–(n+1))

1 2 nth
D Q D Q D Q Q
C Q C Q C Q
CLOCK
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60
MC14014B, MC14021B
8-Bit Static Shift Register

The MC14014B and MC14021B 8–bit static shift registers are
constructed with MOS P–channel and N–channel enhancement mode
devices in a single monolithic structure. These shift registers find
primary use in parallel–to–serial data conversion, synchronous and
asynchronous parallel input, serial output data queueing; and other
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general purpose register applications requiring low power and/or high
noise immunity.
MARKING
• Synchronous Parallel Input/Serial Output (MC14014B) DIAGRAMS
• Asynchronous Parallel Input/Serial Output (MC14021B) 16
• Synchronous Serial Input/Serial Output

PDIP–16
P SUFFIX MC140XXBCP
• Full Static Operation CASE 648 AWLYYWW
• “Q” Outputs from Sixth, Seventh, and Eighth Stages 1

• Double Diode Input Protection 16
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC–16
140XXB
• Capable of Driving Two Low–power TTL Loads or One Low–power D SUFFIX AWLYWW
CASE 751B
1
• MC14014B Pin–for–Pin Replacement for CD4014B
• MC14021B Pin–for–Pin Replacement for CD4021B 16
SOEIAJ–16
F SUFFIX MC140XXB
CASE 966 AWLYWW
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) 1

Symbol Parameter Value Unit XX = Specific Device Code
VDD DC Supply Voltage Range – 0.5 to +18.0 V A = Assembly Location
WL or L = Wafer Lot
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V YY or Y = Year
(DC or Transient) WW or W = Work Week
Iin, Iout Input or Output Current ± 10 mA
per Package (Note 3.) Device Package Shipping
TA Ambient Temperature Range – 55 to +125 °C MC14014BCP PDIP–16 2000/Box
Tstg Storage Temperature Range – 65 to +150 °C
MC14014BD SOIC–16 48/Rail
(8–Second Soldering) MC14014BDR2 SOIC–16 2500/Tape & Reel
2. Maximum Ratings are those values beyond which damage to the device MC14014BF SOEIAJ–16 See Note 1.
may occur.
3. Temperature Derating: MC14014BFEL SOEIAJ–16 See Note 1.
MC14021BCP PDIP–16 2000/Box
static voltages or electric fields. However, precautions must be taken to avoid MC14021BD SOIC–16 48/Rail
MC14021BDR2 SOIC–16 2500/Tape & Reel
either VSS or VDD). Unused outputs must be left open. MC14021BFEL SOEIAJ–16 See Note 1.


March, 2000 – Rev. 3 MC14014B/D
MC14014B, MC14021B
TRUTH TABLE
SERIAL OPERATION:
Q6 Q7 Q8
t Clock DS P/S t=n+6 t=n+7 t=n+8
n 0 0 0 ? ?
n+1 1 0 1 0 ?
n+2 0 0 0 1 0
n+3 1 0 1 0 1
X 0 Q6 Q7 Q8
PARALLEL OPERATION:
Clock
MC14014B MC14021B DS P/S Pn *Qn
X X 1 0 0
X X 1 1 1
*Q6, Q7, & Q8 are available externally
X = Don’t Care
PIN ASSIGNMENT
P8 1 16 VDD
Q6 2 15 P7
Q8 3 14 P6
P4 4 13 P5
P3 5 12 Q7
P2 6 11 DS
P1 7 10 C
VSS 8 9 P/S
LOGIC DIAGRAM
P1 P2 P3 P6 P7 P8
9 7 6 5 14 15 1
P/S
11
DS D Q D Q D Q D Q D Q D
C C C C Q C Q C Q
10
CLOCK
VDD = PIN 16 P4 = PIN 4

VSS = PIN 8 P5 = PIN 13 2 12 3
Q6 Q7 Q8
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62
MC14014B, MC14021B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Î
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 15 — 0.015 15 — 600
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
http://onsemi.com
63
MC14014B, MC14021B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
10
15
—
—
50
40
100
80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time (Clock to Q, P/S to Q) tPLH, ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL, tPLH = (1.7 ns/pF) CL + 315 ns tPHL 5.0 — 400 800
tPHL, tPLH = (0.66 ns/pF) CL + 137 ns 10 — 170 340
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Pulse Width tWH 5.0 400 150 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 175 75 —
15 135 40 —
ÎÎÎÎÎ
Clock Frequency
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fcl 5.0
10
—
—
3.0
6.0
1.5
3.0
MHz
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 8.0 4.0
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Parallel/Serial Control Pulse Width tWH 5.0 400 150 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 175 75 —
15 135 40 —
Setup Time
ÎÎÎÎÎ
ÎÎÎÎÎ
P/S to Clock ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tsu 5.0
10
200
100
100
50
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 80 40 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Hold Time th 5.0 20 – 2.5 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to P/S 10 20 – 10 —
15 25 0 —
Setup Time
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Data (Parallel or Serial) to
tsu 5.0
10
350
80
150
50
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock or P/S 15 60 30 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Hold Time th 5.0 45 0 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to Ds 10 35 0 —
15 35 5 —
Hold Time
ÎÎÎÎÎ
ÎÎÎÎÎ
Clock to Pn ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
th 5.0
10
50
45
25
20
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 45 20 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Clock Rise Time tr(cl) 5.0 — — 15 µs
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — — 5
15 — — 4
VDD Vout VDD Vout
P/S Q6 P/S Q6
PULSE PULSE
C C
GENERATOR GENERATOR
P6 Q7 P6 Q7
P7 P7
P8 IOH P8 IOL
DS Q8 DS Q8
EXTERNAL EXTERNAL
POWER POWER
SUPPLY SUPPLY
Preset output under test to a logic “1” level.
Figure 1. Output Source Current Test Circuit Figure 2. Output Sink Current Test Circuit
http://onsemi.com
64
MC14014B, MC14021B
VDD
500 µF ID
0.01 µF
CERAMIC
P/S
PULSE
C Q6
GENERATOR 1
P1
P2 CL
P3
P4 Q7
P5
P6 CL
P7
PULSE P8 Q8
DS
GENERATOR 2
CL
VSS
1
f
CLOCK 50%
DATA
Figure 3. Power Dissipation Test Circuit and Waveform
SW 1
VDD
PULSE 1 VDD
GENERATOR 1 20 ns 20 ns
PARALLEL OR VDD
2 90%
P/S SERIAL DATA
50%
C Q6 INPUT 10% VSS
P1 tsu
2 2 P2
PULSE tWH tTHL
P3
GENERATOR 2 VDD
1 1 P4 Q7 CLOCK OR P/S 90%
P5 INPUT 50%
10% VSS
P6 CL tWH tWL
P7 tPLH tPHL
P8 Q8 VOH
DS Q 90%
OUTPUT 50%
SWITCH POSITION 1 = PARALLEL IN 10% VOL
SWITCH POSITION 2 = SERIAL IN VSS
SW 2
tTLH tTHL
tWL = tWH = 50% DUTY CYCLE
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65
MC14015B
Dual 4-Bit Static

Shift Register
The MC14015B dual 4–bit static shift register is constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. It consists of two identical, independent
4–state serial–input/parallel–output registers. Each register has http://onsemi.com
independent Clock and Reset inputs with a single serial Data input.
The register states are type D master–slave flip–flops. Data is shifted MARKING
from one stage to the next during the positive–going clock transition. DIAGRAMS
Each register can be cleared when a high level is applied on the Reset 16
line. These complementary MOS shift registers find primary use in PDIP–16
P SUFFIX MC14015BCP
buffer storage and serial–to–parallel conversion where low power AWLYYWW
CASE 648
dissipation and/or noise immunity is desired.
1
• Diode Protection on All Inputs
• Logic Edge–Clocked Flip–Flop Design —

SOIC–16
14015B
D SUFFIX AWLYWW
Logic state is retained indefinitely with clock level either high or low; CASE 751B
information is transferred to the output only on the positive going 1
edge of the clock pulse.
•
16
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range. TSSOP–16 14
DT SUFFIX 015B
CASE 948F ALYW
1
Symbol Parameter Value Unit SOEIAJ–16
F SUFFIX MC14015B
VDD DC Supply Voltage Range – 0.5 to +18.0 V AWLYWW
CASE 966
(DC or Transient) 1
Iin, Iout Input or Output Current ± 10 mA A = Assembly Location

(DC or Transient) per Pin WL or L = Wafer Lot
YY or Y = Year
PD Power Dissipation, 500 mW WW or W = Work Week
TL Lead Temperature 260 °C Device Package Shipping
may occur. MC14015BD SOIC–16 48/Rail
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14015BDR2 SOIC–16 2500/Tape & Reel
This device contains protection circuitry to guard against damage due to high MC14015BDT TSSOP–16 2000/Tape & Reel

March, 2000 – Rev. 3 MC14015B/D
MC14015B
TRUTH TABLE
C D R Q0 Qn
0 0 0 Qn–1
1 0 1 Qn–1
X 0 No Change No Change
X X 1 0 0
X = Don’t Care
Qn = Q0, Q1, Q2, or Q3, as applicable.
Qn–1 = Output of prior stage.
PIN ASSIGNMENT
CB 1 16 VDD
Q3B 2 15 DB
Q2A 3 14 RB
Q1A 4 13 Q0B
Q0A 5 12 Q1B
RA 6 11 Q2B
DA 7 10 Q3A
VSS 8 9 CA
BLOCK DIAGRAM
Q0 5
7 D
Q1 4
Q2 3
9 C
R Q3 10
Q0 13
15 D
Q1 12
Q2 11
1 C
R Q3 2
14
VDD = PIN 16
VSS = PIN 8
http://onsemi.com
67
MC14015B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or .05 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Total Supply Current (5.) (6.) IT 5.0 IT = (1.2 µA/kHz)f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.4 µA/kHz)f + IDD
ÎÎÎÎ
Per Package)
ÎÎÎ ÎÎÎ
ÎÎÎ
buffers switching)
15 IT = (3.6 µA/kHz)f + IDD
IT(CL) = IT(50 pF) + (CL – 50) Vfk
http://onsemi.com
68
MC14015B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time tPLH, ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock, Data to Q tPHL
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset to Q
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Clock Pulse Width ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ tWH
15
5.0
—
400
120
185
170
— ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 175 85 —
15 135 55 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fcl 5.0
10
—
—
2.0
6.0
1.5
3.0
MHz
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 7.5 3.75
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Pulse Rise and Fall Times tTLH, tTHL 5.0 — — 15 µs
10 — — 5
ÎÎÎÎÎ
ÎÎÎÎÎ
Reset Pulse Width ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ tWH
15
5.0
—
400
—
200
4
— ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 160 80 —
15 120 60 —
Setup Time
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tsu 5.0
10
350
100
100
50
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 75 40 —
7. The formulas given are for typical characteristics only at 25_C.
VDD
0.01 µF
PULSE 500 µF ID CERAMIC
GENERATOR VDD
2
D Q0
Q1 CL
PULSE Q2 CL
GENERATOR C Q3
CL
1 R CL
VSS
1
f
CLOCK 50%
DATA
http://onsemi.com
69
MC14015B
tTLH tTHL
DATA VDD
90%
INPUT 50%
10% 0V
tsu
VDD tTLH t– tTHL
PULSE
GENERATOR D 90% VDD
Q0 CLOCK
2 CL 50%
Q1 INPUT 10%
SYNC CL 0V
PULSE Q2 tWH tWL
C Q3 CL tPLH tPHL
GENERATOR
1 R CL
90%
VSS 50%
Q0 10%
tWL = tWH = 50% Duty Cycle

tTLH = tTHL ≤ 20 ns tTLH tTHL
Figure 2. Switching Test Circuit and Waveforms
VDD
PULSE
CLOCK VDD
GENERATOR D Q0 50%
2 CL INPUT 0V
Q1 tsu
SYNC CL
PULSE Q2
C Q3 CL th
GENERATOR
1 R CL DATA VDD
50%
VSS INPUT 0V
Figure 3. Setup and Hold Time Test Circuit and Waveforms
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70
SINGLE BIT
VDD Q
RESET
CLOCK
DATA TO D OF
IN NEXT BIT
VSS
71
MC14015B
http://onsemi.com
CIRCUIT SCHEMATICS
DATA INPUT BUFFER RESET INPUT BUFFER CLOCK INPUT BUFFER

VDD VDD
VDD
RESET CLOCK CLOCK

DATA DATA TO RESET
TO 4 BITS IN TO 4 BITS
IN FIRST BIT IN
VSS VSS
VSS
MC14015B
LOGIC DIAGRAMS
SINGLE BIT
C C Q
TO D OF
DATA NEXT BIT
C C C C
C C
RESET
C
C
C
COMPLETE DEVICE
5 4 3 10
Q0 Q1 Q2 Q3
DATA INPUT BUFFER

D
7 D Q D Q D Q D Q
C Q C Q C Q C Q
CLOCK INPUT BUFFER R R R R
C
9
R
6
13 12 11 2
RESET INPUT BUFFER Q0 Q1 Q2 Q3
DATA INPUT BUFFER

D
15 D Q D Q D Q D Q
C Q C Q C Q C Q
CLOCK INPUT BUFFER R R R R
C
1
VDD = PIN 16
R VSS = PIN 8
14
RESET INPUT BUFFER
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72
MC14016B
Quad Analog Switch/

Quad Multiplexer
The MC14016B quad bilateral switch is constructed with MOS

monolithic structure. Each MC14016B consists of four independent
switches capable of controlling either digital or analog signals. The http://onsemi.com
quad bilateral switch is used in signal gating, chopper, modulator,
demodulator and CMOS logic implementation. MARKING
PDIP–14
• Linearized Transfer Characteristics P SUFFIX MC14016BCP
• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical CASE 646 AWLYYWW
• Pin–for–Pin Replacements for CD4016B, CD4066B (Note improved 1

transfer characteristic design causes more parasitic coupling 14
capacitance than CD4016) SOIC–14
• For Lower RON, Use The HC4016 High–Speed CMOS Device or D SUFFIX
14016B
AWLYWW
The MC14066B CASE 751A
• This Device Has Inputs and Outputs Which Do Not Have ESD 1
Protection. Antistatic Precautions Must Be Taken. 14

SOEIAJ–14
F SUFFIX MC14016B
CASE 965 AWLYWW
1
VDD DC Supply Voltage Range – 0.5 to +18.0 V WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
(DC or Transient)
Iin Input Current (DC or Transient) ± 10 mA
per Control Pin
ISW Switch Through Current ± 25 mA
Device Package Shipping
per Package (Note 3.) MC14016BCP PDIP–14 2000/Box
TA Ambient Temperature Range – 55 to +125 °C MC14016BD SOIC–14 55/Rail
(8–Second Soldering) MC14016BF SOEIAJ–14 See Note 1.
2. Maximum Ratings are those values beyond which damage to the device MC14016BFEL SOEIAJ–14 See Note 1.
may occur.
3. Temperature Derating: 1. For ordering information on the EIAJ version of
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C the SOIC packages, please contact your local

March, 2000 – Rev. 3 MC14016B/D
MC14016B
PIN ASSIGNMENT
IN 1 1 14 VDD
OUT 1 2 13 CONTROL 1
IN 2 4 11 IN 4
CONTROL 2 5 10 OUT 4
CONTROL 3 6 9 OUT 3
VSS 7 8 IN 3
BLOCK DIAGRAM
13
CONTROL 1 2
1 OUT 1
IN 1
5
CONTROL 2 3
4 OUT 2
IN 2
6
CONTROL 3 9
OUT 3
8
IN 3
12
CONTROL 4 10
OUT 4
11
IN 4
VDD = PIN 14
VSS = PIN 7
Control Switch
0 = VSS Off
1 = VDD On
LOGIC DIAGRAM
(1/4 OF DEVICE SHOWN)
OUT
CONTROL
LOGIC DIAGRAM RESTRICTIONS IN

VSS ≤ Vin ≤ VDD
VSS ≤ Vout ≤ VDD
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74
MC14016B
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
Î ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic Figure Symbol Vdc Min Max Min Typ (4.) Max Min Max Unit
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage 1 VIL 5.0 — — — 1.5 0.9 — — Vdc
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Control Input 10 — — — 1.5 0.9 — —
15 — — — 1.5 0.9 — —
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIH 5.0 — — 3.0 2.0 — — — Vdc
ÎÎ ÎÎ
10 — — 8.0 6.0 — — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — — 13 11 — — —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Control — Iin 15 — — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
Input Capacitance — Cin pF
Control — — — — 5.0 — — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
Switch Input — — — — 5.0 — — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
Switch Output — — — — 5.0 — — —
Feed Through — — — — 0.2 — — —
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
Quiescent Current
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Per Package) (5.) ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
2,3 IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
“ON” Resistance 4,5,6 RON — — Ohms
(VC = VDD, RL = 10 kΩ) — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(Vin = + 5.0 Vdc) — 600 — 300 660 — 840
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(Vin = – 5.0 Vdc) VSS = – 5.0 Vdc — 600 — 300 660 — 840
(Vin = ± 0.25 Vdc) 5.0 — 600 — 280 660 — 840
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Vin = + 7.5 Vdc)
ÎÎÎ ÎÎ
ÎÎÎ
(Vin = ± 0.25 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = – 7.5 Vdc) VSS = – 7.5 Vdc
7.5
—
—
—
360
360
360
—
—
—
240
240
180
400
400
400
—
—
—
520
520
520
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Vin = + 10 Vdc)
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
— 600 — 260 660 — 840
ÎÎ ÎÎ
(Vin = + 0.25 Vdc) VSS = 0 Vdc — 600 — 310 660 — 840
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = + 5.6 Vdc) 10 — 600 — 310 660 — 840
(Vin = + 15 Vdc) — 360 — 260 400 — 520
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(Vin = + 0.25 Vdc) VSS = 0 Vdc
ÎÎÎ
ÎÎÎ
— 360 — 260 400 — 520
ÎÎ ÎÎ
(Vin = + 9.3 Vdc) 15 — 360 — 300 400 — 520
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
∆ “ON” Resistance — ∆RON Ohms
Between any 2 circuits in a common
ÎÎÎ
package
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ ÎÎ
(VC = VDD)
(Vin = ± 5.0 Vdc, VSS = – 5.0 Vdc) 5.0 — — — 15 — — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = ± 7.5 Vdc, VSS = – 7.5 Vdc) 7.5 — — — 10 — — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input/Output Leakage Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
— — µAdc
ÎÎ ÎÎ
(VC = VSS)
(Vin = + 7.5, Vout = – 7.5 Vdc) 7.5 — ± 0.1 — ± 0.0015 ± 0.1 — ± 1.0
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = – 7.5, Vout = + 7.5 Vdc) 7.5 — ± 0.1 — ± 0.0015 ± 0.1 — ± 1.0
NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application.
5. For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e., the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.
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75
MC14016B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
VDD
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Characteristic Figure Symbol Vdc Min Typ (7.) Max Unit
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Propagation Delay Time (VSS = 0 Vdc) 7 tPLH, 5.0 — 15 45 ns
Vin to Vout tPHL 10 — 7.0 15
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VC = VDD, RL = 10 kΩ) 15 — 6.0 12
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Control to Output 8 tPHZ, ns
v
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(Vin 10 Vdc, RL = 10 kΩ) tPLZ, 5.0 — 34 90
tPZH, 10 — 20 45
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
tPZL 15 — 15 35
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Crosstalk, Control to Output (VSS = 0 Vdc) 9 — 5.0 — 30 — mV
(VC = VDD, Rin = 10 kΩ, Rout = 10 kΩ, 10 — 50 —
ÎÎÎ
f = 1.0 kHz)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Crosstalk between any two switches (VSS = 0 Vdc) — —
15
5.0
—
—
100
– 80
—
— dB
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(RL = 1.0 kΩ, f = 1.0 MHz,
+ V
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
crosstalk 20 log10 out1)
Vout2
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
Noise Voltage (VSS = 0 Vdc)
ÎÎÎÎ
(VC = VDD, f = 100 Hz)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
10,11 — 5.0
10
15
—
—
—
24
25
30
—
—
—
nV/√Cycle
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
(VC = VDD, f = 100 kHz)
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
5.0
10
—
—
12
12
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
15 — 15 —
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Second Harmonic Distortion (VSS = – 5.0 Vdc) — — 5.0 — 0.16 — %
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
RL = 10 kΩ, f = 1.0 kHz)
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Insertion Loss (VC = VDD, Vin = 1.77 Vdc, 12 — 5.0 dB
VSS = – 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)
+Iloss
ÎÎÎ
(RL = 1.0 kΩ)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
V
ÎÎÎÎ ÎÎÎÎ
20 log10 out)
ÎÎÎ
ÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
—
—
2.3
0.2
—
—
ÎÎÎ
(RL = 10 kΩ)
ÎÎÎ
(RL = 100 kΩ)
(RL = 1.0 MΩ)
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
—
—
0.1
0.05
—
—
ÎÎÎ
ÎÎÎ ÎÎÎÎ
Bandwidth (– 3.0 dB)
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VC = VDD, Vin = 1.77 Vdc, VSS = – 5.0 Vdc,
12,13 BW 5.0 MHz
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
RMS centered @ 0.0 Vdc)
(RL = 1.0 kΩ) — 54 —
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(RL = 10 kΩ) — 40 —
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(RL = 100 kΩ) — 38 —
(RL = 1.0 MΩ) — 37 —
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VSS = – 5.0 Vdc)
+
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vout
ÎÎÎÎ
OFF Channel Feedthrough Attenuation
ÎÎÎ
ÎÎÎÎ
— — 5.0 kHz
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VC = VSS, 20 log10 –50 dB)
Vin — 1250 —
(RL = 1.0 kΩ)
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
— 140 —
(RL = 10 kΩ)
— 18 —
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(RL = 100 kΩ)
— 2.0 —
(RL = 1.0 MΩ)
6. The formulas given are for typical characteristics only at 25_C.
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76
MC14016B
VC IS
Vin Vout
VIL: VC is raised from VSS until VC = VIL.

VIL: at VC = VIL: IS = ±10 µA with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS.
VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.
Figure 1. Input Voltage Test Circuit
10,000
VDD = 15 Vdc 10 Vdc
PD , POWER DISSIPATION (µW)

VDD TA = 25°C
5.0 Vdc
1000
ID
100
VDD Vout
TO ALL
10 k 10
PULSE 4 CIRCUITS CONTROL
GENERATOR INPUT
fc
VSS Vin 1.0

PD = VDD x ID 5.0 k 10 k 100 k 1.0 M 10 M 50 M
fc, FREQUENCY (Hz)
Figure 2. Quiescent Power Dissipation Figure 3. Typical Power Dissipation per Circuit
Test Circuit (1/4 of device shown)
TYPICAL RON versus INPUT VOLTAGE
700 700
RL = 10 kΩ VSS = 0 Vdc
600 TA = 25°C 600 RL = 10 kΩ
R ON, “ON” RESISTANCE (OHMS)
R ON, “ON” RESISTANCE (OHMS)
TA = 25°C
500 500
400 VC = VDD = 5.0 Vdc 400

VSS = – 5.0 Vdc VC = VDD = 10 Vdc
300 300
200 200 VC = VDD = 15 Vdc

VC = VDD = 7.5 Vdc
100 VSS = – 7.5 Vdc 100
0 0
– 10 – 8.0 – 4.0 0 4.0 8.0 10 0 2.0 6.0 10 14 18 20
Figure 4. VSS = – 5.0 V and – 7.5 V Figure 5. VSS = 0 V
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77
MC14016B
Vout
RL CL
Vin
Vout 20 ns 20 ns
RL VDD
Vin 90%
VC 50% 10%
VSS
tPLH tPHL
Vout 50%
Vin
Figure 6. RON Characteristics Figure 7. Propagation Delay Test Circuit

Test Circuit and Waveforms
Vout
VC RL CL
Vin VX
20 ns
VDD Vout
90%
VC 50%
10% VC 10 k 15 pF
VSS
tPZH tPHZ
Vin = VDD
90% Vx = VSS
Vout 10% Vin
tPZL tPLZ
90% 1k
Vout Vin = VSS
10%
Vx = VDD
Figure 8. Turn–On Delay Time Test Circuit Figure 9. Crosstalk Test Circuit
and Waveforms
35
30
VDD = 15 Vdc
NOISE VOLTAGE (nV/ CYCLE)
25
10 Vdc
20
5.0 Vdc
15
OUT QUAN–TECH 10
MODEL
VC = VDD
2283
5.0
IN OR EQUIV
0
10 100 1.0 k 10 k 100 k
f, FREQUENCY (Hz)
Figure 10. Noise Voltage Test Circuit Figure 11. Typical Noise Characteristics
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78
MC14016B
2.0
RL = 1 MΩ AND 100 kΩ
0
TYPICAL INSERTION LOSS (dB)
10 kΩ
– 2.0
1.0 kΩ
– 4.0 – 3.0 dB (RL = 1.0 MΩ )
Vout
– 6.0 – 3.0 dB (RL = 10 kΩ ) RL
VC
– 3.0 dB (RL = 1.0 kΩ )
– 8.0
– 10 + 2.5 Vdc
Vin 0.0 Vdc
– 12 – 2.5 Vdc
10 k 100 k 1.0 M 10 M 100 M
fin, INPUT FREQUENCY (Hz)
Figure 12. Typical Insertion Loss/Bandwidth Figure 13. Frequency Response Test Circuit
Characteristics
ON SWITCH
CONTROL
SECTION
OF IC
LOAD
V
SOURCE
Figure 14. ∆V Across Switch
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79
MC14016B
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Switch. The 0–to–5 The example shows a 5 Vp–p signal which allows no
V Digital Control signal is used to directly control a 5 Vp–p margin at either peak. If voltage transients above VDD
analog signal. and/or below VSS are anticipated on the analog channels,
The digital control logic levels are determined by VDD external diodes (Dx) are recommended as shown in Figure
and VSS. The VDD voltage is the logic high voltage; the VSS B. These diodes should be small signal types able to absorb
voltage is logic low. For the example, VDD = + 5 V logic high the maximum anticipated current surges during clipping.
at the control inputs; VSS = GND = 0 V logic low. The absolute maximum potential difference between
The maximum analog signal level is determined by VDD VDD and VSS is 18.0 V. Most parameters are specified up to
and VSS. The analog voltage must not swing higher than 15 V which is the recommended maximum difference
VDD or lower than VSS. between VDD and V SS.
+5 V
VDD VSS
+ 5.0 V
+5 V 5 Vp–p SWITCH
ANALOG SIGNAL IN
SWITCH 5 Vp–p
+ 2.5 V
OUT ANALOG SIGNAL
EXTERNAL
CMOS 0–TO–5 V DIGITAL
GND
DIGITAL CONTROL SIGNALS MC14016B
CIRCUITRY
Figure A. Application Example
VDD VDD
Dx Dx
SWITCH SWITCH
IN OUT
Dx Dx
VSS VSS
Figure B. External Germanium or Schottky Clipping Diodes
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80
MC14017B
Decade Counter
The MC14017B is a five–stage Johnson decade counter with
built–in code converter. High speed operation and spike–free outputs
are obtained by use of a Johnson decade counter design. The ten
decoded outputs are normally low, and go high only at their
appropriate decimal time period. The output changes occur on the
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positive–going edge of the clock pulse. This part can be used in
frequency division applications as well as decade counter or decimal
decode display applications. MARKING
DIAGRAMS
• Fully Static Operation
16
• DC Clock Input Circuit Allows Slow Rise Times PDIP–16
• Carry Out Output for Cascading P SUFFIX MC14017BCP
AWLYYWW
• Divide–by–N Counting
CASE 648
1
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
Schottky TTL Load Over the Rated Temperature Range SOIC–16
14017B
• Pin–for–Pin Replacement for CD4017B D SUFFIX AWLYWW
• Triple Diode Protection on All Inputs
CASE 751B
1
16
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) SOEIAJ–16
F SUFFIX MC14017B
Symbol Parameter Value Unit CASE 966 AWLYWW
1
(DC or Transient)
WL or L = Wafer Lot
Iin, Iout Input or Output Current ± 10 mA YY or Y = Year
(DC or Transient) per Pin WW or W = Work Week

Tstg Storage Temperature Range – 65 to +150 °C Device Package Shipping
TL Lead Temperature 260 °C MC14017BCP PDIP–16 2000/Box

may occur. MC14017BDR2 SOIC–16 2500/Tape & Reel
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14017BF SOEIAJ–16 See Note 1.
This device contains protection circuitry to guard against damage due to high MC14017BFEL SOEIAJ–16 See Note 1.
applications of any voltage higher than maximum rated voltages to this 1. For ordering information on the EIAJ version of the
high–impedance circuit. For proper operation, Vin and Vout should be constrained SOIC packages, please contact your local ON
Semiconductor representative.

March, 2000 – Rev. 3 MC14017B/D
MC14017B
PIN ASSIGNMENT
Q5 1 16 VDD
Q1 2 15 RESET
Q0 3 14 CLOCK
Q2 4 13 CE
Q6 5 12 Cout
Q7 6 11 Q9
Q3 7 10 Q4
VSS 8 9 Q8
FUNCTIONAL TRUTH TABLE BLOCK DIAGRAM

(Positive Logic)
CLOCK 14 Q0 3
Clock Decode Q1 2
Clock Enable Reset Output=n Q2 4
0 X 0 n Q3 7
X 1 0 n Q4 10
CLOCK
X X 1 Q0 13 Q5 1
ENABLE
0 0 n+1 Q6 5
X 0 n Q7 6
X 0 n Q8 9
1 0 n+1 Q9 11
X = Don’t Care. If n < 5 Carry = “1”, RESET 15 Cout 12
Otherwise = “0”.
VDD = PIN 16
VSS = PIN 8
LOGIC DIAGRAM
Q5 Q1 Q7 Q3 Q9
1 2 6 7 11
14
CLOCK
CLOCK 12
ENABLE C Q C Q C Q C Q C Q CARRY
13
C C C C C
D Q D Q D Q D Q D Q
R R R R R R R R R R
15
RESET
3 5 4 9 10
Q0 Q6 Q2 Q3 Q4
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82
MC14017B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — — —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
Total Supply Current (5.) (6.) IT = (0.27 µA/kHz) f + IDD µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
IT 5.0
(Dynamic plus Quiescent, 10 IT = (0.55 µA/kHz) f + IDD
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
http://onsemi.com
83
MC14017B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset to Decode Output tPHL
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.66 ns/PF) CL + 197 ns 10 — 230 460
ÎÎÎÎÎ
ÎÎÎÎÎ
Clock to Cout ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH,
tPHL
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to Decode Output tPHL
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Reset to Cout ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH = (1.7 ns/pF) CL + 315 ns 5.0 — 400 800
tPLH = (0.66 ns/pF) CL + 142 ns 10 — 175 350
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ tw(H)
15
5.0
—
250
125
125
250
— ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 100 50 —
15 75 35 —
ÎÎÎÎÎ
Clock Frequency
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fcl 5.0
10
—
—
5.0
12
2.0
5.0
MHz
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 16 6.7
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset Pulse Width tw(H) 5.0 500 250 — ns
10 250 125 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Reset Removal Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ trem
15
5.0
190
750
95
375
—
— ns
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 275 135 —
15 210 105 —
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Clock Input Rise and Fall Time
ÎÎÎ
tTLH,
tTHL
5.0
10 No Limit
—
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Enable Setup Time tsu 5.0 350 175 — ns
10 150 75 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 115 52 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Enable Removal Time trem 5.0 420 260 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 200 100 —
15 140 70 —
http://onsemi.com
84
MC14017B
VDD
Vout Output Output

VSS CLOCK Q0
Sink Drive Source Drive
ENABLE
Q1
Clock to
Q2 Decode desired
Q3 (S1 to A)
Outputs outputs
A Q4 (S1 to B)
VDD S1 ID
RESET Q5 Clock to 5
B Q6
VSS S1 Carry thru 9 S1 to A
Q7 (S1 to B)
Q8
VGS = VDD – VDD
Q9 EXTERNAL
CLOCK Cout POWER VDS = Vout Vout – VDD
SUPPLY
VSS
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD
0.01 µF
500 µF ID
CERAMIC
Q0
Q1
CLOCK Q2
ENABLE Q3
Q4
RESET Q5
Q6
PULSE fc Q7
CLOCK Q8
GENERATOR
Q9
Cout
VSS CL CL CL CL CL CL CL CL CL CL CL
Figure 2. Typical Power Dissipation Test Circuit
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85
MC14017B
Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
RESET RESET RESET

CLOCK CLOCK CLOCK
CE MC14017B CE MC14017B CE MC14017B
Q0 Q1 • • • Q8 Q9 Q0Q1 • • • Q8 Q9 Q1 • • • Q8 Q9
8 DECODED
9 DECODED 8 DECODED
OUTPUTS
OUTPUTS OUTPUTS
CLOCK
FIRST STAGE INTERMEDIATE STAGES LAST STAGE
Figure 3. Counter Expansion
Pcp Ncp 90% VDD

CLOCK 50%
10% VSS
trem tsu 20 ns 20 ns
CLOCK VDD
ENABLE VSS
trem 20 ns 20 ns 20 ns
RESET VDD
20 ns VSS
tPHL tPLH tPLH
Q0 VOH
tTLH VOL
tPLH tPHL
90% VOH
10% 50%
Q1 VOL
tPLH tPHL tTLH tTHL
VOH
Q2 VOL
tPLH tPHL tTLH tTHL
VOH
50%
Q3 VOL
tPLH tPHL tTLH tTHL
VOH
Q4 tTHL VOL
tPLH tPHL tTLH
tPHL
VOH
Q5 VOL
tPLH tPHL tTLH tTHL
90% VOH
Q6 10% VOL
tTHL tTHL
tPLH tPHL VOH
Q7 VOL
tTHL
tPLH VOH
Q8 VOL
tTLH tTHL
tPLH tPHL
VOH
Q9 VOL
tPHL tTLH tTHL tPHL
Cout tPLH VOH
VOL
tTHL
tTLH
Figure 4. AC Measurement Definition and Functional Waveforms
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86
MC14018B
Presettable Divide-By-N
Counter
The MC14018B contains five Johnson counter stages which are
asynchronously presettable and resettable. The counters are
synchronous, and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input. http://onsemi.com
Data on the Jam inputs will then be transferred to their respective Q
outputs (inverted). A logic 1 on the reset input will cause all Q outputs MARKING
to go to a logic 1 state. DIAGRAMS
Division by any number from 2 to 10 can be accomplished by 16
connecting appropriate Q outputs to the data input, as shown in the PDIP–16
Function Selection table. Anti–lock gating is included in the P SUFFIX MC14018BCP
CASE 648 AWLYYWW
MC14018B to assure proper counting sequence.
1
• Schmitt Trigger on Clock Input 16

• Capable of Driving Two Low–power TTL Loads or One Low–power SOIC–16
14018B
Schottky TTL Load Over the Rated Temperature Range D SUFFIX AWLYWW
• Pin–for–Pin Replacement for CD4018B
CASE 751B
1
16
F SUFFIX MC14018B
1
(DC or Transient)
WL or L = Wafer Lot

TA Ambient Temperature Range – 55 to +125 °C ORDERING INFORMATION
Tstg Storage Temperature Range – 65 to +150 °C Device Package Shipping

applications of any voltage higher than maximum rated voltages to this 1. For ordering information on the EIAJ version of
high–impedance circuit. For proper operation, Vin and Vout should be constrained the SOIC packages, please contact your local
to the range VSS v (Vin or Vout) vVDD. ON Semiconductor representative.

March, 2000 – Rev. 3 MC14018B/D
MC14018B
PIN ASSIGNMENT
Din 1 16 VDD
JAM 1 2 15 R
JAM 2 3 14 C
Q2 4 13 Q5
Q1 5 12 JAM 5
Q3 6 11 Q4
JAM 3 7 10 PE
VSS 8 9 JAM 4
FUNCTIONAL TRUTH TABLE

Preset Jam
Clock Reset Enable Input Qn
0 0 X Qn
0 0 X Dn *
X 0 1 0 1
X 0 1 1 0
X 1 X X 1
*Dn is the Data input for that stage. Stage 1
has Data brought out to Pin 1.
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88
MC14018B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Î
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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89
MC14018B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ VDD
All Types
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Rise and Fall Time tTLH, tTHL ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns 5.0 — 100 200
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns 10 — 50 100
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to Q tPHL
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset to Q ns
tPLH = (0.90 ns/pF) CL + 325 ns 5.0 — 370 740
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH = (0.36 ns/pF) CL + 132 ns 10 — 150 300
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH = (0.26 ns/pF) CL + 81 ns 15 — 100 200
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Preset Enable to Q ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Setup Time
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Data (Pin 1) to Clock ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tsu
5.0 200 0 —
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 100 0 —
15 80 0 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Jam Inputs to Preset Enable
ÎÎÎÎ
ÎÎÎ
5.0
10
200
100
0
0
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 80 0 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Data (Jam Inputs)–to–Preset th 5.0 540 270 — ns
Enable Hold Time 10 500 250 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 480 240 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 200 100 —
15 160 80 —
ÎÎÎÎÎ
Pulse Width ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
Reset or Preset Enable
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tWH 5.0
10
290
130
145
65
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 110 55 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Rise and Fall Time tTLH, tTHL 5.0 ns
10 No Limit
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Pulse Frequency fcl 5.0 — 2.5 1.25 MHz
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 6.5 3.25
15 — 8.0 4.0
20 ns 20 ns
VDD
90%
ANY INPUT 50%
10% VSS
tPLH tPHL
VOH
90%
ANY OUTPUT 50%
10% VOL
tTLH tTHL
Figure 1. Switching Time Waveforms
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90
MC14018B
1
CLOCK
0
1
RESET
0
1
PRESET ENABLE
0
1
JAM 1
0
JAM 2 1
0
1
TIMING DIAGRAM JAM 3 DON’T CARE
UNTIL PRESET ENABLE 0
(Q5 Connected to Data Input) 1
GOES HIGH
JAM 4 0
1
JAM 5 0
1
Q1
0
1
Q2
0
1
Q3
0
1
Q4 0
1
Q5
0
FUNCTION SELECTION
Connect
Counter Data Input
Mode (Pin 1) to: Comments
Divide by 10 Q5
Divide by 8 Q4
No external
Divide by 6 Q3
components needed.
Divide by 4 Q2
Divide by 2 Q1 LOGIC DIAGRAM
Divide by 9 Q5 • Q4 Gate package needed
Divide by 7 Q4 • Q3 to provide AND JAM 1 JAM 2 JAM 3 JAM 4 JAM 5
Divide by 5 Q3 • Q2 function. Counter 2 3 7 9 12
Divide by 3 Q2 • Q1 Skips all 1’s state
CLOCK
CLOCK 14
SHAPER
S S S S S
DATA 1 D Q D Q D Q D Q D Q
C C C C C
Q
R P R P R P R P R P
RESET 15
PRESET ENABLE 10
VDD = PIN 16
VSS = PIN 8
5 4 6 11 13
Q1 Q2 Q3 Q4 Q5
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91
MC14020B
14-Bit Binary Counter

The MC14020B 14–stage binary counter is constructed with MOS
monolithic structure. This part is designed with an input wave shaping
circuit and 14 stages of ripple–carry binary counter. The device
advances the count on the negative–going edge of the clock pulse.
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Applications include time delay circuits, counter controls, and
frequency–dividing circuits. MARKING
• Fully Static Operation DIAGRAMS
MC14020BCP
P SUFFIX
• Capable of Driving Two Low–power TTL Loads or One Low–power CASE 648 AWLYYWW
Schottky TTL Load Over the Rated Temperature Range 1
• Buffered Outputs Available from stages 1 and 4 thru 14
• Common Reset Line 16
SOIC–16
• Pin–for–Pin Replacement for CD4020B D SUFFIX
14020B
AWLYWW
CASE 751B
1
16
Symbol Parameter Value Unit TSSOP–16 14
DT SUFFIX 020B
VDD DC Supply Voltage Range – 0.5 to +18.0 V CASE 948F ALYW
1
(DC or Transient)
16
(DC or Transient) per Pin SOEIAJ–16
F SUFFIX MC14020B
PD Power Dissipation, 500 mW CASE 966 AWLYWW
1
YY or Y = Year
WW or W = Work Week
may occur.
3. Temperature Derating: ORDERING INFORMATION
static voltages or electric fields. However, precautions must be taken to avoid MC14020BCP PDIP–16 2000/Box
to the range VSS v (Vin or Vout) vVDD. MC14020BDR2 SOIC–16 2500/Tape & Reel
either VSS or VDD). Unused outputs must be left open. MC14020BDT TSSOP–16 96/Rail


March, 2000 – Rev. 3 MC14020B/D
MC14020B
PIN ASSIGNMENT
Q12 1 16 VDD
Q13 2 15 Q11
Q14 3 14 Q10
Q6 4 13 Q8
Q5 5 12 Q9
Q7 6 11 R
Q4 7 10 C
VSS 8 9 Q1
TRUTH TABLE
Clock Reset Output State
0 No Change
0 Advance to Next State
X 1 All Outputs are Low
X = Don’t Care
LOGIC DIAGRAM
Q1 Q4 Q5 Q12 Q13 Q14

9 7 5 1 2 3
CLOCK
10 C Q C Q C Q C Q C Q C Q
C Q C Q C Q C Q C Q C
R R R R R R
RESET
11
Q6 = PIN 4 Q9 = PIN 12 VDD = PIN 16

Q7 = PIN 6 Q10 = PIN 14 VSS = PIN 8
Q8 = PIN 13 Q11 = PIN 15
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93
MC14020B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
Total Supply Current (5.) (6.) IT = (0.42 µA/kHz)f + IDD µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
IT 5.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Per Package) 15 IT = (1.43 µA/kHz)f + IDD
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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94
MC14020B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to Q1 tPHL
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL, tPLH = (1.7 ns/pF) CL + 175 ns 5.0 — 260 520
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to Q14
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL, tPLH – (1.7 ns/pF) CL + 1735 ns 5.0 — 1820 3900
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
Reset to Qn ÎÎÎÎ

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL
5.0 — 370 740

ns
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPHL = (0.66 ns/pF) CL + 122 ns
ÎÎÎÎ
ÎÎÎ
10
15
—
—
155
115
310
230
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 165 55 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Clock Pulse Frequency ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ fcl
15
5.0
125
—
38
2.0
—
1.0 MHz
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 6.0 3.0
15 — 8.0 4.0
ÎÎÎÎÎ
Clock Rise and Fall Time
ÎÎÎÎ ÎÎÎ
ÎÎÎ
tTLH, tTHL 5.0
10 No Limit
—
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset Pulse Width tWL 5.0 3000 320 — ns
10 550 120 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ trem
15
5.0
420
130
80
65
—
— ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 50 25 —
15 30 15 —
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95
MC14020B
VDD VDD
0.01 µF
500 µF ID CERAMIC PULSE
C Q1
GENERATOR
Q4
Q CL
PULSE R n
C Q1 CL
GENERATOR CL
Q4 VSS
Qn CL
R
CL
CL 20 ns 20 ns
VSS
CLOCK 90%
50%
10%
20 ns 20 ns
VDD tWH
90% tPLH tPHL
CLOCK 50%
10% VSS Q 90%
50%
50% DUTY CYCLE 10%
tTLH tTHL
Figure 1. Power Dissipation Test Circuit Figure 2. Switching Time Test Circuit
and Waveform and Waveforms
1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16,384

CLOCK
RESET
Q1
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Figure 3. Timing Diagram
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96
MC14022B
Octal Counter
The MC14022B is a four–stage Johnson octal counter with built–in
code converter. High–speed operation and spike–free outputs are
obtained by use of a Johnson octal counter design. The eight decoded
outputs are normally low, and go high only at their appropriate octal
time period. The output changes occur on the positive–going edge of
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the clock pulse. This part can be used in frequency division
applications as well as octal counter or octal decode display
applications.
• Fully Static Operation MARKING
DIAGRAMS
• DC Clock Input Circuit Allows Slow Rise Times
16
• Carry Out Output for Cascading PDIP–16
• Supply Voltage Range = 3.0 Vdc to 18 Vdc P SUFFIX MC14022BCP
AWLYYWW
•
CASE 648
1
16
• Triple Diode Protection on All Inputs SOIC–16
14022B
D SUFFIX AWLYWW
CASE 751B
1
WL or L = Wafer Lot
VDD DC Supply Voltage Range – 0.5 to +18.0 V YY or Y = Year
WW or W = Work Week
(DC or Transient)
MC14022BD SOIC–16 2400/Box
may occur.

March, 2000 – Rev. 3 MC14022B/D
MC14022B
PIN ASSIGNMENT
Q1 1 16 VDD
Q0 2 15 R
Q2 3 14 C
Q5 4 13 CE
Q6 5 12 Cout
NC 6 11 Q4
Q3 7 10 Q7
VSS 8 9 NC
NC = NO CONNECTION
BLOCK DIAGRAM FUNCTIONAL TRUTH TABLE

(Positive Logic)
Q0 2 Clock
CLOCK 14
Q1 1
Clock Enable Reset Output=n
Q2 3
Q3 7 0 X 0 n
CLOCK X 1 0 n
13 Q4 11
ENABLE 0 0 n+1
Q5 4
Q6 5 X 0 n
Q7 10 1 0 n+1
RESET 15 Cout 12 X 0 n
VDD = PIN 16 X X 1 Q0
VSS = PIN 8 X = Don’t Care. If n < 4 Carry = 1,
Otherwise = 0.
NC = PIN 6, 9
LOGIC DIAGRAM
11 1 5 7
Q4 Q1 Q6 Q3
CLOCK
14
13 CARRY
CLOCK VDD C Q C Q C Q C Q 12
C C C C
ENABLE
D RQ D RQ D RQ D RQ
VSS
15
RESET
Q0 Q5 Q2 Q7
2 4 3 10
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98
MC14022B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Vin = 0 or VDD ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
Total Supply Current (4.) (5.) IT = (0.28 µA/kHz)f + IDD µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
IT 5.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Per Package) 15 IT = (0.85 µA/kHz)f + IDD
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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99
MC14022B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset to Decode Output tPHL
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Clock to Cout ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH,
tPHL
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to Decode Output tPHL
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Reset to Cout ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH = (1.7 ns/pF) CL + 315 ns 5.0 — 400 800
tPLH = (0.66 ns/pF) CL + 142 ns 10 — 175 350
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ tWH
15
5.0
—
250
125
125
250
— ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 100 50 —
15 75 35 —
ÎÎÎÎÎ
Clock Frequency
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fcl 5.0
10
—
—
5.0
12
2.0
5.0
MHz
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 16 6.7
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset Pulse Width tWH 5.0 500 250 — ns
10 250 125 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ trem
15
5.0
190
750
95
375
—
— ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 275 135 —
15 210 105 —
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Clock Input Rise and Fall Time
ÎÎÎ
tTLH, tTHL 5.0
10 No Limit
—
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Enable Setup Time tsu 5.0 350 175 — ns
10 150 75 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 115 52 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Enable Removal Time trem 5.0 420 260 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 200 100 —
15 140 70 —
http://onsemi.com
100
MC14022B
VDD
Output Output
Vout Sink Drive Source Drive
CLOCK Q0
VSS
ENABLE Q1 Clock to desired
VDD A Q2 Output
Q3 Outputs (S1 to A) (S1 to B)
RESET Q4 Clock to Q5
S1 Q5 ID Carry thru Q7 S1 to A
VSS B
Q6 (S1 to B)
Q7 VGS = VDD – VDD
CLOCK C
out
VDS = Vout Vout – VDD
EXTERNAL
VSS POWER
SUPPLY
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD
0.01 µF
500 µF ID
CERAMIC
Q0
Q1
CLOCK Q2
ENABLE
Q3
Q4
RESET Q5
Q6
PULSE fc Q7
CLOCK Cout
GENERATOR
VSS CL CL CL CL CL CL CL CL CL
Figure 2. Typical Power Dissipation Test Circuit
Figure 3 shows a technique for extending the number of decoded output states for the MC14022B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
R R R
C C C
CE MC14022B CE MC14022B CE MC14022B
Q0 Q1 • • • Q6 Q7 Q0 Q1 • • • Q6 Q7 Q1 • • • Q6 Q7
6 DECODED
7 DECODED 6 DECODED
OUTPUTS
OUTPUTS OUTPUTS
CLOCK
FIRST STAGE INTERMEDIATE STAGES LAST STAGE
Figure 3. Counter Expansion
http://onsemi.com
101
MC14022B
tWH
tWL 90% VDD
CLOCK 50%
10% VSS
trel tsu 20 ns
CLOCK 20 ns
VDD
ENABLE
VSS
trem 20 ns 20 ns 20 ns
VDD
RESET
VSS
tPHL tPLH tPLH
Q0 VOH
50%
VOL
tPLH tPHL tTHL
90% 50% VOH
Q1 10% VOL
tPLH tPHL tTLH
VOH
Q2 VOL
tPLH tPHL tTLH
VOH
Q3 VOL
tPLH tPHL tTLH
VOH
Q4 VOL
tPLH tPHL tTLH tPHL
VOH
Q5 VOL
tTLH tTHL tTLH tTHL
tPLH tPHL
VOH
Q6 VOL
tPLH tPHL
VOH
Q7 VOL
tPHL tTLH tTHL tPLH
Cout tPHL VOH
VOL
tTLH tTHL
Figure 4. AC Measurement Definition and Functional Waveforms
http://onsemi.com
102
MC14024B
7-Stage Ripple Counter

The MC14024B is a 7–stage ripple counter with short propagation
delays and high maximum clock rates. The Reset input has standard
noise immunity, however the Clock input has increased noise
immunity due to Hysteresis. The output of each counter stage is
buffered.
http://onsemi.com
• Output Transitions Occur on the Falling Edge of the Clock Pulse MARKING
• Supply Voltage Range = 3.0 Vdc to 18 Vdc DIAGRAMS
PDIP–14
Schottky TTL Load Over the Rated Temperature Range P SUFFIX MC14024BCP
• Pin–for–Pin Replacement for CD4024B CASE 646 AWLYYWW
14
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) SOIC–14
14024B
D SUFFIX AWLYWW
Symbol Parameter Value Unit CASE 751A

(DC or Transient)
SOEIAJ–14
Iin, Iout Input or Output Current ± 10 mA F SUFFIX MC14024B
(DC or Transient) per Pin CASE 965 AWLYWW

TA Ambient Temperature Range – 55 to +125 °C WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
2. Maximum Ratings are those values beyond which damage to the device ORDERING INFORMATION
may occur.
3. Temperature Derating: Device Package Shipping


March, 2000 – Rev. 3 MC14024B/D
MC14024B
TRUTH TABLE
Clock Reset State
0 0 No Change
0 1 All Outputs Low
1 0 No Change
1 1 All Outputs Low
0 No Change
1 All Outputs Low
0 Advance One Count
1 All Outputs Low
PIN ASSIGNMENT
CLOCK 1 14 VDD
RESET 2 13 NC
Q7 3 12 Q1
Q6 4 11 Q2
Q5 5 10 NC
Q4 6 9 Q3
VSS 7 8 NC
VDD = PIN 14
VSS = PIN 7
NC = NO CONNECTION
LOGIC DIAGRAM
1
CLOCK C Q C Q C Q C Q
R Q R Q R Q R Q
2
RESET
12 11 4 3
Q1 Q2 Q6 Q7
Q3 = PIN 9
Q4 = PIN 6
Q5 = PIN 5
http://onsemi.com
104
MC14024B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
http://onsemi.com
105
MC14024B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Propagation Delay Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ tPLH,
15 — 40 80
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to Q1 tPHL
ÎÎÎÎÎ
Clock to Q7
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
10
15
—
—
150
110
230
175
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
5.0
10
15
—
—
—
1000
400
300
2000
750
565
Reset to Qn
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0
10
—
—
500
250
800
400
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 165 60 —
15 125 40 —
ÎÎÎÎÎ
Reset Pulse Width
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tWH 5.0
10
600
350
375
200
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 260 150 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset Removal Time trem 5.0 625 250 — ns
10 190 75 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 145 50 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Input Rise and Fall Time tTLH, tTHL 5.0 — — 1.0 s
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — — 8.0 ms
15 — — 200 µs
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
Input Pulse Frequency
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fcl 5.0
10
15
—
—
—
2.5
8.0
12
1.0
3.0
4.0
MHz
http://onsemi.com
106
MC14024B
VDD VOL = Vout VDD VOH = Vout

VDD
C Qn C Qn
R IOH R IOL
EXTERNAL EXTERNAL
COUNT Qn TO A VSS POWER VSS POWER
LOGIC “1” LEVEL. SUPPLY SUPPLY

VDD
0.01 µF
500 µF ID CERAMIC
PULSE f
C Q1
GENERATOR CL
Q2
CL
Q3
CL
Q4
CL
Q5
CL
Q6
CL
R Q7
CL
VSS
Figure 3. Power Dissipation Test Circuit
http://onsemi.com
107
t WL
t WH
VDD
1 50% 2 4 8 16 32 64 128 255
CLOCK (1) VSS
t rem
RESET (2) VDD
50%
VSS
t PLH1 t PHL1 t R1
90% VOH
50%
Q1 (12) 10% VOL
t TLH t PHL2 t THL t R2
t PLH2
VOH
90%
50%
Q2 (11) 10% VOL
t PLH3
VOH
50%
Q3 (9) VOL
108
t PLH4 VOH
50%
MC14024B
http://onsemi.com
Q4 (6) VOL
t PLH5 VOH
Figure 4. Functional Waveforms

50%
Q5 (5) t PHL6 VOL
t TLH t THL t R6
t PLH6
90% VOH
50%
10%
Q6 (4) VOL
t PLH7 VOH
Q7 (3) VOL
t TLH t THL
Input t TLH and t THL = 20 ns

MC14027B
Dual J-K Flip-Flop

The MC14027B dual J–K flip–flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip–flop. These devices may be
used in control, register, or toggle functions.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc http://onsemi.com
• Logic Swing Independent of Fanout
• Logic Edge–Clocked Flip–Flop Design — MARKING
Logic state is retained indefinitely with clock level either high or low; DIAGRAMS
information is transferred to the output only on the positive–going 16
edge of the clock pulse PDIP–16
AWLYYWW
CASE 648
1
16
SOIC–16
14027B
D SUFFIX AWLYWW
CASE 751B
F SUFFIX MC14027B
CASE 966
WL or L = Wafer Lot
WW or W = Work Week
applications of any voltage higher than maximum rated voltages to this MC14027BD SOIC–16 2400/Box


March, 2000 – Rev. 3 MC14027B/D
MC14027B
TRUTH TABLE
Inputs Outputs*
C† J K S R Qn‡ Qn+1 Qn+1
1 X 0 0 0 1 0
X 0 0 0 1 1 0
0 X 0 0 0 0 1
X 1 0 0 1 0 1
1 1 0 0 Qo Qo Qo
X X 0 0 X Qn Qn No
Change
X X X 1 0 X 1 0
X X X 0 1 X 0 1
X X X 1 1 X 1 1
X = Don’t Care ‡ = Present State
† = Level Change * = Next State
PIN ASSIGNMENT
QA 1 16 VDD
QA 2 15 QB
CA 3 14 QB
RA 4 13 CB
KA 5 12 RB
JA 6 11 KB
SA 7 10 JB
VSS 8 9 SB
BLOCK DIAGRAM
S
6 J Q 1
3 C
5 K Q 2
R
4
S
10 J Q 15
13 C
11 K Q 14
R
12
VDD = PIN 16
VSS = PIN 8
http://onsemi.com
110
MC14027B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Î
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 2.0 — 0.004 2.0 — 60
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 4.0 — 0.006 4.0 — 120
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
http://onsemi.com
111
MC14027B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Propagation Delay Times** ÎÎÎ
ÎÎÎÎ
ÎÎÎ tPLH,
15 — 40 80
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to Q, Q tPHL
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
10
15
—
—
75
50
150
100
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Set to Q, Q
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0 — 175 350
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset to Q, Q
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0 — 350 450
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Setup Times tsu 5.0 140 70 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 50 25 —
15 35 17 —
Hold Times
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
th 5.0
10
15
140
50
35
70
25
17
—
—
—
ns
ÎÎÎÎÎ
Clock Pulse Width
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tWH, tWL 5.0
10
330
110
165
55
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 75 38 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 9.0 4.5
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Pulse Rise and Fall Time tTLH, tTHL
15
5.0
—
—
13
—
6.5
15 µs
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — — 5.0
15 — — 4.0
Removal Times
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
trem
5 90 10 —
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Set 10 45 5 —
15 35 3 —
ÎÎÎÎÎ
Reset ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
5
10
50
25
– 30
– 15
—
—
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 20 – 10 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Set and Reset Pulse Width tWH 5.0 250 125 — ns
10 100 50 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 70 35 —
http://onsemi.com
112
MC14027B
20 ns 20 ns
VDD
90%
J 50%
10% VSS
20 ns 20 ns
VDD
K 90%
tsu 50%
10% VSS
tsu th
20 ns 20 ns
90% VDD
C 50%
10% VSS 20 ns 20 ns
tWH tWL 90% VDD
1 SET OR 50%
fcl RESET 10% VSS
tPLH tPHL tw trem
VOH 20 ns 20 ns
90% VDD
Q 50% 90%
CLOCK 50%
10% VOL 10% VSS
tTLH tTHL tw
tPLH
tPHL
Inputs R and S low. VOH
For the measurement of tWH, I/fcl, and PD Q or Q 50%
the Inputs J and K are kept high. VOL
Figure 1. Dynamic Signal Waveforms Figure 2. Dynamic Signal Waveforms

(J, K, Clock, and Output) (Set, Reset, Clock, and Output)
LOGIC DIAGRAM
S
Q
C
J
C
C
C
K C C
C C
R
Q
C
C C
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113
MC14028B
BCD-To-Decimal Decoder
Binary-To-Octal Decoder
The MC14028B decoder is constructed so that an 8421 BCD code
on the four inputs provides a decimal (one–of–ten) decoded output,
while a 3–bit binary input provides a decoded octal (one–of–eight)
code output with D forced to a logic “0”. Expanded decoding such as http://onsemi.com
binary–to–hexadecimal (one–of–16), etc., can be achieved by using
other MC14028B devices. The part is useful for code conversion,
MARKING
address decoding, memory selection control, demultiplexing, or
DIAGRAMS
readout decoding.
16
• Diode Protection on All Inputs PDIP–16
CASE 648 AWLYYWW
• Positive Logic Design
16
• Low Outputs on All Illegal Input Combinations SOIC–16
• Similar to CD4028B. D SUFFIX
14028B
AWLYWW
CASE 751B
1

F SUFFIX MC14028B
VDD DC Supply Voltage Range – 0.5 to +18.0 V CASE 966 AWLYWW
1
(DC or Transient)
WL or L = Wafer Lot
PD Power Dissipation, 500 mW YY or Y = Year
per Package (Note 3.) WW or W = Work Week

(8–Second Soldering) Device Package Shipping
may occur.
3. Temperature Derating: MC14028BD SOIC–16 2400/Box
static voltages or electric fields. However, precautions must be taken to avoid MC14028BF SOEIAJ–16 See Note 1.
high–impedance circuit. For proper operation, Vin and Vout should be constrained MC14028BFEL SOEIAJ–16 See Note 1.

March, 2000 – Rev. 3 MC14028B/D
MC14028B
PIN ASSIGNMENT
Q4 1 16 VDD
Q2 2 15 Q3
Q0 3 14 Q1
Q7 4 13 B
Q9 5 12 C
Q5 6 11 D
Q6 7 10 A
VSS 8 9 Q8
TRUTH TABLE
D C B A Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 0 0 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 0 0 0 1 0 0
0 0 1 1 0 0 0 0 0 0 1 0 0 0
0 1 0 0 0 0 0 0 0 1 0 0 0 0
0 1 0 1 0 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 0 1 0 0 0 0 0 0
0 1 1 1 0 0 1 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 1 0 0 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0 0 0 0
BLOCK DIAGRAM
10 A Q0 3
Q1 14
3–BIT Q2 2
BINARY 13 B Q3 15 OCTAL
8421 DECODED
INPUTS Q4 1 DECIMAL
BCD OUTPUTS
Q5 6 DECODED
INPUTS
OUTPUTS
12 C Q6 7
Q7 4
Q8 9
11 D Q9 5
VDD = PIN 16
VSS = PIN 8
http://onsemi.com
115
MC14028B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Voltage “0” Level 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 VOL 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH
5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIL
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIH
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) IOH 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink
IOL
5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc
ÎÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
ÎÎÎÎ
ÎÎÎ
IT 5.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Output Rise and Fall Time

ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH,
tTHL 5.0 — 100 200
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH,
tPHL 5.0 — 300 600
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
http://onsemi.com
116
MC14028B
20 ns 20 ns
Inputs B, C, and D VDD All outputs connected
switching in respect 90% to respective CL loads.
INPUT A 50%
to a BCD code. f in respect to a system
10%
VSS clock.
1/f
20 ns 20 ns
VDD
INPUT C 90%
50%
10%
VSS
Inputs A, B, and D low. tPLH tPHL
VOH
90%
Q4 50%
10%
VOL
tTLH tTHL
Figure 1. Dynamic Signal Waveforms
LOGIC DIAGRAM
Q0
Q1
A
Q2
Q3
B
Q4
Q5
C
Q6
Q7
D
Q8
Q9
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117
MC14028B
APPLICATIONS INFORMATION INPUTS

D C B A
Expanded decoding can be performed by using the
MC14028B and other CMOS Integrated Circuits. The
circuit in Figure 2 converts any 4–bit code to a decimal or
hexadecimal code. The accompanying table shows the input
binary combinations, the associated “output numbers” that D C B A D C B A
go “high” when selected, and the “redefined output MC14028B MC14028B
numbers” needed for the proper code. For example: For the Q9 Q0 Q9 Q0
combination DCBA = 0111 the output number 7 is redefined
for the 4–bit binary, 4–bit gray, excess–3, or excess–3 gray 15 –8 15 –0
codes as 7, 5, 4, or 2, respectively. Figure 3 shows a 6–bit
OUTPUT NUMBERS
binary 1–of–64 decoder using nine MC14028B circuits and
two MC14069UB inverters. Figure 2. Code Conversion Circuit and Truth Table
The MC14028B can be used in decimal digit displays,
such as, neon readouts or incandescent projection indicators
as shown in Figure 4.
Code and Redefined

Output Numbers
Hexadecimal Decimal
Excess–3
Excess–3
Inputs Output Numbers
Binary
Aiken
4–Bit
4–Bit
Gray
Gray
4221
D C B A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 3 0 2 2
0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 2 0 3 3
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 4 7 1 4 4
0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 5 6 2 3
0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 6 4 3 1 4
0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 7 5 4 2
1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 8 15 5
1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 9 14 6 5
1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 10 12 7 9 6
1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 11 13 8 5
1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 12 8 9 5 6
1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 13 9 6 7 7
1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 11 8 8 8
1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 10 7 9 9
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118
MC14028B
INPUTS
A B C D E F INHIBIT
(NO SELECTION)
A B C –D
MC14028B
Q0 Q9
A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D
MC14028B MC14028B MC14028B MC14028B MC14028B MC14028B MC14028B MC14028B
Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9 Q0 Q9
0 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63
*1/6 MC14069UB 64 OUTPUTS (SELECTED OUTPUT IS HIGH)
Figure 3. Six–Bit Binary 1–of–64 Decoder
APPROPRIATE APPROPRIATE
Q0 VOLTAGE VOLTAGE
A Q1 NEON INCANDESCENT
Q2 DISPLAY DISPLAY
B Q3
Q4 OR
MC14028B Q5
C Q6
Q7 0
Q8 9 9 2 1 0
D Q9
Figure 4. Decimal Digit Display Application
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119
MC14029B
Binary/Decade Up/Down
Counter
The MC14029B Binary/Decade up/down counter is constructed

with MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. The counter consists of type D flip–flop
stages with a gating structure to provide toggle flip–flop capability. http://onsemi.com
The counter can be used in either Binary or BCD operation. This
complementary MOS counter finds primary use in up/down and
MARKING
difference counting and frequency synthesizer applications where low
DIAGRAMS
power dissipation and/or high noise immunity is desired. It is also
16
useful in A/D and D/A conversion and for magnitude and sign
PDIP–16
generation. P SUFFIX MC14029BCP
AWLYYWW
• Diode Protection on All Inputs CASE 648
• Internally Synchronous for High Speed

• Logic Edge–Clocked Design — Count Occurs on Positive Going
16
SOIC–16
Edge of Clock 14029B
D SUFFIX
•
AWLYWW
Asynchronous Preset Enable Operation CASE 751B
• Pin for Pin Replacement for CD4029B 16
SOEIAJ–16
F SUFFIX MC14029B
CASE 966 AWLYWW

WL or L = Wafer Lot
PD Power Dissipation, 500 mW ORDERING INFORMATION
TL Lead Temperature 260 °C MC14029BD SOIC–16 2400/Box
may occur. MC14029BF SOEIAJ–16 See Note 1.
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14029BFEL SOEIAJ–16 See Note 1.

static voltages or electric fields. However, precautions must be taken to avoid ON Semiconductor representative.

March, 2000 – Rev. 3 MC14029B/D
MC14029B
PIN ASSIGNMENT
PE 1 16 VDD
TRUTH TABLE
Q3 2 15 CLK
Preset
P3 3 14 Q2
Carry In Up/Down Enable Action
P0 4 13 P2
1 X 0 No Count
Cin 5 12 P1
0 1 0 Count Up
0 0 0 Count Down Q0 6 11 Q1
X X 1 Preset Cout 7 10 U/D
X = Don’t Care VSS 8 9 B/D
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ – 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Vin = VDD or 0 ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“0” Level
ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
http://onsemi.com
121
MC14029B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
All Types
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clk to Q tPHL
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clk to Cout tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPHL 5.0 — 250 500
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Cin to Cout tPLH, ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
PE to Q tPLH, ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 80 160
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
PE to Cout tPLH, ns
tPLH, tPHL = (1. 7 ns/pF) CL + 465 ns tPHL 5.0 — 320 640
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 105 210
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Pulse Width tW(cl) 5.0 180 90 — ns
10 80 40 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 60 30 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 8.0 4.0
15 — 10 5.0
ÎÎÎÎÎ
Preset Removal Time
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
The Preset Signal must be low prior to a positive–going
trem 5.0
10
160
80
80
40
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
transition of the clock. 15 60 30 —
µs
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Rise and Fall Time tr(cl) 5.0 — — 15
tf(cl) 10 — — 5
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — — 4
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Carry In Setup Time tsu 5.0 150 75 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 60 30 —
15 40 20 —
ÎÎÎÎÎ
ÎÎÎÎ
Up/Down Setup Time
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0
10
15
340
140
100
170
70
50
—
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Binary/Decade Setup Time
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0
10
320
140
160
70
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 100 50 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Preset Enable Pulse Width tW 5.0 130 65 — ns
10 70 35 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 50 25 —
http://onsemi.com
122
MC14029B
VDD
500 pF ID 0.01 µF
CERAMIC
PE Q0
Cin
B/D Q1
PULSE U/D
CLK Q2
GENERATOR CL
P0
P1 Q3 CL
P2 CL
P3 Cout CL
CL
20 ns 20 ns
VDD
50% 90%
CLK 10%
VSS
VARIABLE
WIDTH
VDD
PE Q0
PROGRAMMABLE Cin
PULSE B/D Q1
GENERATOR U/D
CLK Q2
P0 CL
P1 Q3 CL
P2 CL
P3 Cout CL
CL
VSS
tW
tsu trem
CARRY IN OR 1/fcl
VDD
UP/DOWN 50%
OR BINARY/DECADE VSS
VDD
CLOCK 50%
VSS
tW VDD
PRESET ENABLE
VSS
20 ns
Cout ONLY tTLH
VOH
Q0 OR CARRY OUT 90% 10% 90%
10% VOL
tPLH
tTHL tPHL tPLH
http://onsemi.com
123
MC14029B
TIMING DIAGRAM
CLOCK
CARRY IN
UP/DOWN
BINARY/DECADE
PE
P0
P1
P2
P3
Q0
Q1
Q2
Q3
CARRY OUT
COUNT 0 1 2 3 4 5 6 7 8 9 8 7 6 5 4 3 2 1 0 0 9 6 7 0
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
Cout MC14029B Cin Cout Cin Cout MC14029B Cin
U/D U/D MC14029B U/D
MSD LSD
B/D PE B/D PE B/D PE OUTPUT
P3 P2 P1 P0 CLK P3 P2 P1 P0 CLK P3 P2 P1 P0 CLK
VDD VDD VDD VDD

“1” “2” “3”
INPUT
CLOCK
CLOCK
Cout 1 (LSD)
Cout 2
Cout 3 (MSD)
PE
123
122
121
120
101
100
123
122
119
99
10
11
COUNT
9
1
0
*tW ^ 900 ns @ VDD = 5 V

Figure 3. Divide by N BCD Down Counter and Timing Diagram
(Shown for N = 123)
http://onsemi.com
124
9 4 P0 12 P1 13 P2 3 P3
BINARY/DECADE
1
PRESET ENABLE
5 PE P0 PE P1 PE P2 PE P3
CARRY IN TE Q0 TE Q1 TE Q2 TE Q3
125
7
CLK Q0 CLK Q1 CLK Q2 CLK Q3 CARRY OUT

MC14029B
LOGIC DIAGRAM
http://onsemi.com
10
UP/DOWN
15
CLOCK
6 Q0 1 Q1 14 Q2 2 Q3
MC14040B
12-Bit Binary Counter

The MC14040B 12–stage binary counter is constructed with MOS
monolithic structure. This part is designed with an input wave shaping
circuit and 12 stages of ripple–carry binary counter. The device
advances the count on the negative–going edge of the clock pulse.
http://onsemi.com
Applications include time delay circuits, counter controls, and
frequency–driving circuits. MARKING
• Fully Static Operation DIAGRAMS

PDIP–16
P SUFFIX MC14040BCP
• Capable of Driving Two Low–power TTL Loads or One Low–power CASE 648 AWLYYWW

• Common Reset Line 16
• Pin–for–Pin Replacement for CD4040B SOIC–16
14040B
D SUFFIX AWLYWW
CASE 751B
1
Symbol Parameter Value Unit TSSOP–16 14
VDD DC Supply Voltage Range – 0.5 to +18.0 V DT SUFFIX 040B
CASE 948F ALYW
(DC or Transient) 1
Iin, Iout Input or Output Current ± 10 mA 16
(DC or Transient) per Pin SOEIAJ–16
F SUFFIX MC14040B
PD Power Dissipation, 500 mW AWLYWW
per Package (Note 3.) CASE 966
TA Ambient Temperature Range – 55 to +125 °C 1
Tstg Storage Temperature Range – 65 to +150 °C A = Assembly Location

WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
may occur.
3. Temperature Derating: ORDERING INFORMATION
static voltages or electric fields. However, precautions must be taken to avoid MC14040BCP PDIP–16 2000/Box
high–impedance circuit. For proper operation, Vin and Vout should be constrained MC14040BD SOIC–16 2400/Box


March, 2000 – Rev. 3 MC14040B/D
MC14040B
PIN ASSIGNMENT
Q12 1 16 VDD
Q6 2 15 Q11
Q5 3 14 Q10
Q7 4 13 Q8
Q4 5 12 Q9
Q3 6 11 R
Q2 7 10 C
VSS 8 9 Q1
TRUTH TABLE
0 No Change
0 Advance to next state
X 1 All Outputs are low
X = Don’t Care
LOGIC DIAGRAM
Q1 Q2 Q3 Q10 Q11 Q12

9 7 6 14 15 1
CLOCK
C Q C Q C Q C Q C Q C
R R R R R R
RESET
11
Q4 = PIN 5 Q7 = PIN 4 VDD = PIN 16

Q6 = PIN 2 Q9 = PIN 12
http://onsemi.com
127
MC14040B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc
ÎÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
ÎÎÎÎ
ÎÎÎ
IT 5.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
http://onsemi.com
128
MC14040B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
TTLH, TTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
TTLH, TTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
TTLH, TTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time tPLH,
Clock to Q1 tPHL ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL, tPLH = (1.7 ns/pF) CL + 315 ns 5.0 — 260 520
tPHL, tPLH = (0.66 ns/pF) CL + 137 ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 115 230
Clock to Q12
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0
10
—
—
1625
720
3250
1440
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ tPHL
15 — 500 1000
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset to Qn
tPHL = (1.7 ns/pF) CL + 485 ns 5.0 — 370 740
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPHL = (0.86 ns/pF) CL + 182 ns
ÎÎÎÎ
ÎÎÎ
10
15
—
—
155
115
310
230
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 150 55 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 115 38 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 7.0 3.5
15 — 10.0 4.5
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH, tTHL 5.0
10
15
No Limit
ns
ÎÎÎÎÎ
Reset Pulse Width
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tWH 5.0
10
960
360
320
120
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 270 80 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset Removal Time trem 5.0 130 65 — ns
10 50 25 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 30 15 —
VDD
VDD
0.01 µF PULSE
500 µF ID C Q1
CERAMIC GENERATOR
Q2
Q CL
R n CL
PULSE
C Q1 CL
GENERATOR VSS
Q2
Q CL
R n CL
VSS CL
20 ns 20 ns
CLOCK
90%
50%
10%
20 ns 20 ns tWH
tPLH tPHL
VDD
CLOCK 90%
50% Q 90%
10% VSS 50%
10%
50% DUTY CYCLE tTLH tTHL
http://onsemi.com
129
MC14040B
1 2 4 8 16 32 64 128 256 512 1024 2048 4096

CLOCK
RESET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
TIME–BASE GENERATOR outputs Q5, Q10, Q11, and Q12 division by 3600 is
A 60 Hz sinewave obtained through a 1.0 Megohm accomplished. The MC14012B decodes the counter
resistor connected directly to a standard 120 Vac power line outputs, produces a single output pulse, and resets the binary
is applied to the clock input of the MC14040B. By selecting counter. The resulting output frequency is 1.0 pulse/minute.
VDD
1.0 M MC14040B
C Q5 1.0 PULSE/MINUTE
≥ 20 pF Q10 OUTPUT
1/2 1/2
120 Vac MC14012B MC14012B
Q11
60 Hz
R Q12
VSS
http://onsemi.com
130
MC14042B
Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity
http://onsemi.com
input. Information present at the data input is transferred to outputs Q
and Q during the clock level which is determined by the polarity input.
When the polarity input is in the logic “0” state, data is transferred MARKING
during the low clock level, and when the polarity input is in the logic DIAGRAMS
“1” state the transfer occurs during the high clock level. 16
PDIP–16
• Buffered Data Inputs P SUFFIX MC14042BCP
AWLYYWW
• Common Clock CASE 648
• Clock Polarity Control 1
• Q and Q Outputs 16
• Double Diode Input Protection SOIC–16
14042B
• Supply Voltage Range = 3.0 Vdc to 1 8 Vdc D SUFFIX AWLYWW
•
CASE 751B
1
16
SOEIAJ–16
F SUFFIX MC14042B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) CASE 966 AWLYWW
1
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V WL or L = Wafer Lot
(DC or Transient) YY or Y = Year
Iin, Iout Input or Output Current ± 10 mA WW or W = Work Week
per Package (Note 3.) ORDERING INFORMATION
TA Ambient Temperature Range – 55 to +125 °C Device Package Shipping
Tstg Storage Temperature Range – 65 to +150 °C MC14042BCP PDIP–16 2000/Box
2. Maximum Ratings are those values beyond which damage to the device MC14042BDR2 SOIC–16 2500/Tape & Reel
may occur.
3. Temperature Derating: MC14042BF SOEIAJ–16 See Note 1.
MC14042BFR1 SOEIAJ–16 See Note 1.
applications of any voltage higher than maximum rated voltages to this MC14042BFR2 SOEIAJ–16 See Note 1.
to the range VSS v (Vin or Vout) vVDD. 1. For ordering information on the EIAJ version of
Unused inputs must always be tied to an appropriate logic voltage level (e.g., the SOIC packages, please contact your local
either VSS or VDD). Unused outputs must be left open. ON Semiconductor representative.

March, 2000 – Rev. 3 MC14042B/D
MC14042B
PIN ASSIGNMENT
Q3 1 16 VDD
Q0 2 15 Q3
Q0 3 14 D3
D0 4 13 D2
CLOCK 5 12 Q2
POLARITY 6 11 Q2
D1 7 10 Q1
VSS 8 9 Q1
TRUTH TABLE
Clock Polarity Q
0 0 Data
1 0 Latch
1 1 Data
0 1 Latch
LOGIC DIAGRAM
D0 LATCH Q0
5 4 2
CLOCK 1
Q0
POLARITY 3
6
D1 LATCH Q1
7 10
2
Q1
9
D2 LATCH Q2
13 11
3
Q2
12
VDD = PIN 16
VSS = PIN 8
D3 LATCH Q3
14 1
4
Q3
15
http://onsemi.com
132
MC14042B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
1.0
2.0
—
—
0.002
0.004
1.0
2.0
—
—
30
60
µAdc
ÎÎÎÎ
ÎÎÎ
15 — 4.0 — 0.006 4.0 — 120
ÎÎÎÎ
ÎÎÎ
IT 5.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs all
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
http://onsemi.com
133
MC14042B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time, D to Q, Q tPLH, no
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time, Clock to Q, Q tPLH, ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Pulse Width tWH ns
5.0 300 150 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
10
15
100
80
50
40
—
—
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Pulse Rise and Fall Time tTLH, µs
tTHL 5.0 — — 15
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
10
15
—
—
—
—
5.0
4.0
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Hold Time th ns
5.0 100 50 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 50 25 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 40 20 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Setup Time tsu ns
5.0 50 0 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 30 0 —
15 25 0 —
VDD
1
16
f
20 ns 20 ns
5 90%
CLOCK Q0 2 50%
6 10%
Q0 3 DATA INPUT
POLARITY tPLH tPHL
PULSE 4 Q1 10
D0 Q1 9 90%
GENERATOR 1 50%
7 Q2 11 10%
D1 Q OUTPUT
13 Q2 12 tTLH tTHL
D2
14 Q3 1 tPHL
D3 Q3 15 Q OUTPUT
90%
50%
10%
8 VSS
For Power Dissipation test, each output tTHL tTLH
is loaded with capacitance CL.
Figure 1. AC and Power Dissipation Test Circuit and Timing Diagram

(Data to Output)
http://onsemi.com
134
MC14042B
VDD
16
PULSE 5
CLOCK Q0 2
GENERATOR 1
6 Q0 3
POLARITY
4 Q1 10
PULSE
D0 Q1 9
GENERATOR 2 7
D1 Q2 11
13 Q2 12
D2 Q3 1
14
D3 Q3 15
NOTE: CL connected to output under test. 8 VSS
20* ns 20 ns
90%
50%
CLOCK INPUT 10% tWH
P.G. 1 20 ns
90%
50%
DATA INPUT tsu th
P.G. 2
tPLH
Q OUTPUT 90%
50%
10%
*Input clock rise time is 20 ns except for maximum rise time test.
Figure 2. AC Test Circuit and Timing Diagram

(Clock to Output)
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135
MC14043B, MC14044B
CMOS MSI
Quad R–S Latches
The MC14043B and MC14044B quad R–S latches are constructed
with MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. Each latch has an independent Q output http://onsemi.com
and set and reset inputs. The Q outputs are gated through three–state
buffers having a common enable input. The outputs are enabled with a MARKING
logical “1” or high on the enable input; a logical “0” or low DIAGRAMS
disconnects the latch from the Q outputs, resulting in an open circuit at 16
the Q outputs. PDIP–16
P SUFFIX MC140XXBCP
• Double Diode Input Protection CASE 648 AWLYYWW
• Three–State Outputs with Common Enable 1
• Outputs Capable of Driving Two Low–power TTL Loads or One
16
Low–Power Schottky TTL Load Over the Rated Temperature Range
SOIC–16
• Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX
140XXB
AWLYWW
CASE 751B
1
16
SOEIAJ–16
Symbol Parameter Value Unit F SUFFIX MC140XXB
CASE 966 AWLYWW
(DC or Transient)
XX = Specific Device Code
Iin, Iout Input or Output Current ± 10 mA A = Assembly Location
YY or Y = Year
WW or W = Work Week
Tstg Storage Temperature Range – 65 to +150 °C ORDERING INFORMATION

may occur. MC14043BD SOIC–16 2400/Box
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14043BDR2 SOIC–16 2500/Tape & Reel
This device contains protection circuitry to guard against damage due to high MC14043BF SOEIAJ–16 See Note 1.
applications of any voltage higher than maximum rated voltages to this MC14043BFEL SOEIAJ–16 See Note 1.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14044BD SOIC–16 2400/Box


March, 2000 – Rev. 3 MC14043B/D
MC14043B, MC14044B
PIN ASSIGNMENT
MC14043B MC14044B
Q3 1 16 VDD Q3 1 16 VDD
Q0 2 15 R3 NC 2 15 S3
R0 3 14 S3 S0 3 14 R3
S0 4 13 NC R0 4 13 Q0
E 5 12 S2 E 5 12 R2
S1 6 11 R2 R1 6 11 S2
R1 7 10 Q2 S1 7 10 Q2
VSS 8 9 Q1 VSS 8 9 Q1
NC = NO CONNECTION
MC14043B MC14044B
4 4
S0 2 R0 13
Q0 Q0
3 3
R0 S0
6 6
S1 9 R1 9
Q1 Q1
7 VDD = PIN 16 7 VDD = PIN 16

R1 S1
VSS = PIN 8 VSS = PIN 8
12 NC = PIN 13 12 NC = PIN 2
S2 10 R2 10
Q2 Q2
11 11
R2 S2
14 14
S3 1 TRUTH TABLE R3 1 TRUTH TABLE
Q3 Q3
S R E Q S R E Q
X X 0 High X X 0 High
15 Impedance Impedance
15
R3 0 0 1 No Change S3 0 0 1 0
0 1 1 0 0 1 1 1
5 1 0 1 1 5 1 0 1 0
ENABLE 1 1 1 1 1 1 1 No Change
ENABLE
X = Don’t Care X = Don’t Care
http://onsemi.com
137
MC14043B, MC14044B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
1.0
2.0
—
—
0.002
0.004
1.0
2.0
—
—
30
60
µAdc
ÎÎÎÎ
ÎÎÎ
15 — 4.0 — 0.006 4.0 — 120
ÎÎÎÎ
ÎÎÎ
IT 5.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs all
buffers switching)
ÎÎÎÎ
ÎÎÎÎ
Current ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
Three–State Output Leakage
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0
µAdc
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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138
MC14043B, MC14044B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tTLH = (1.35 ns/pF) CL + 32.5 ns
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
5.0
10
15
—
—
—
100
50
40
200
100
80
ÎÎÎÎÎ
Output Fall Time
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (1.35 ns/pF) CL + 32.5 ns
tTHL
5.0 — 100 200
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.60 ns/pF) CL + 20 ns 10 — 50 100
tTHL = (0.40 ns/pF) CL + 20 ns 15 — 40 80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH = (0.90 ns/pF) CL + 130 ns 5.0 — 175 350
tPLH = (0.36 ns/pF) CL + 57 ns 10 — 75 175
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH = (0.26 ns/pF) CL + 47 ns 15 — 60 120
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL = (0.90 ns/pF) CL + 130 ns tPHL 5.0 — 175 350 ns
tPHL = (0.90 ns/pF) CL + 57 ns 10 — 75 175
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Set, Set Pulse Width ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tW
15
5.0
—
200
60
80
120
— ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 100 40 —
15 70 30 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Reset, Reset Pulse Width
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tW 5.0
10
15
200
100
70
80
40
30
—
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Three–State Enable/Disable Delay
ÎÎÎÎ
ÎÎÎ
tPLZ,
tPHZ,
5.0
10
—
—
150
80
300
160
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPZL, 15 — 55 110
tPZH
AC WAVEFORMS
MC14043B MC14044B
20 ns 20 ns 20 ns 20 ns
VDD VDD
90% 90%
50% 50%
SET 10% SET 10%
VSS VSS
20 ns 20 ns 20 ns 20 ns
VDD
90% 90% VDD
50% 50%
RESET 10% RESET 10%
VSS VSS
tTHL tTLH
tTLH tTHL
VOH VOH
90% 90%
Q 10% 50% Q 50%
VOL 10% VOL
tPHL tPLH
tPLH tPHL
http://onsemi.com
139
MC14043B, MC14044B
THREE–STATE ENABLE/DISABLE DELAYS

Set, Reset, Enable, and Switch Conditions for 3–State Tests VDD
MC14043B MC14044B
Test Enable S1 S2 Q S R S R
tPZH Open Closed A VDD VSS VSS VDD S1
tPZL Closed Open B VSS VDD VDD VSS TO

1k
OUTPUT
tPHZ Open Closed A VDD VSS VSS VDD UNDER CL
TEST 50 pF
tPLZ Closed Open B VSS VDD VDD VSS
S2
VSS
VDD
ENABLE 50%
VSS
tPZH VDD
90%
QA 10%
tPHZ VOL
tPZL
tPLZ VOH
QB
10%
VSS
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140
MC14046B
Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators,
a voltage–controlled oscillator (VCO), source follower, and zener
diode. The comparators have two common signal inputs, PCAin and
PCBin. Input PCAin can be used directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small voltage
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signals. The self–bias circuit adjusts small voltage signals in the linear
region of the amplifier. Phase comparator 1 (an exclusive OR gate) MARKING
provides a digital error signal PC1out, and maintains 90° phase shift at DIAGRAMS
the center frequency between PCAin and PCBin signals (both at 50% 16
duty cycle). Phase comparator 2 (with leading edge sensing logic) PDIP–16
P SUFFIX MC14046BCP
provides digital error signals, PC2out and LD, and maintains a 0° AWLYYWW
phase shift between PCA in and PCBin signals (duty cycle is CASE 648
immaterial). The linear VCO produces an output signal VCOout 1
whose frequency is determined by the voltage of input VCOin and the 16
capacitor and resistors connected to pins C1A, C1B, R1, and R2. The 14046B
SOIC–16
source–follower output SFout with an external resistor is used where DW SUFFIX
the VCOin signal is needed but no loading can be tolerated. The inhibit CASE 751G
input Inh, when high, disables the VCO and source follower to AWLYYWW
minimize standby power consumption. The zener diode can be used to 1
assist in power supply regulation. 16
Applications include FM and FSK modulation and demodulation, SOEIAJ–16
frequency synthesis and multiplication, frequency discrimination, F SUFFIX MC14046B
tone decoding, data synchronization and conditioning, CASE 966 AWLYWW
voltage–to–frequency conversion and motor speed control.
1
• Buffered Outputs Compatible with MHTL and Low–Power TTL A = Assembly Location
• Diode Protection on All Inputs WL or L = Wafer Lot
YY or Y = Year
• Supply Voltage Range = 3.0 to 18 V WW or W = Work Week
• Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited ORDERING INFORMATION
• Phase Comparator 2 switches on Rising Edges and is not Duty Cycle Device Package Shipping
Limited
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) MC14046BDW SOIC–16 2350/Box
MC14046BDWR2 SOIC–16 1000/Tape & Reel
Vin Input Voltage Range (All Inputs) – 0.5 to VDD + 0.5 V
Iin DC Input Current, per Pin ± 10 mA
TA Operating Temperature Range – 55 to +125 °C
This device contains protection circuitry to guard
Tstg Storage Temperature Range – 65 to +150 °C against damage due to high static voltages or electric
2. Maximum Ratings are those values beyond which damage to the device fields. However, precautions must be taken to avoid ap-
may occur. plications of any voltage higher than maximum rated
3. Temperature Derating: voltages to this high–impedance circuit. For proper
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C operation, Vin and Vout should be constrained to the
range VSS v v
(Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused out-
puts must be left open.

March, 2000 – Rev. 5 MC14046B/D
MC14046B
BLOCK DIAGRAM PIN ASSIGNMENT
SELF BIAS PHASE LD 1 16 VDD

PCAin 14 2 PC1out
CIRCUIT COMPARATOR 1 PC1out 2 15 ZENER
PHASE 13 PC2out
PCBin 3 14 PCAin
PCBin 3 COMPARATOR 2 1 LD
VOLTAGE 4 VCOout VCOout 4 13 PC2out
VCOin 9 11 R1
CONTROLLED INH 5 12 R2
12 R2
VDD = PIN 16 OSCILLATOR 6 C1A
(VCO) 7 C1B C1A 6 11 R1
VSS = PIN 8
C1B 7 10 SFout
INH 5 SOURCE FOLLOWER 10 SFout
VSS 15 ZENER VSS 8 9 VCOin
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
VDD – 55_C 25_C 125_C
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Min Max Min Typ Max Min Max Unit
VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Voltage “0” Level
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Input Voltage (4.) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ “0” Level VIL
15 14.95 — 14.95 15 — 14.95 —
Vdc
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 13.5 or 1.5 Vdc)
(VO = 0.5 or 4.5 Vdc) ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ “1” Level VIH
15
5.0
—
3.5
4.0
—
—
3.5
6.75
2.75
4.0
—
—
3.5
4.0
— Vdc
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Output Drive Current
ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOH = 2.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ Source
IOH
5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
mAdc
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎ
Input Current
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Input Capacitance ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Iin
Cin
15
—
—
—
± 0.1
—
—
—
± 0.00001
5.0
± 0.1
7.5
—
—
± 1.0
—
µAdc
pF
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
Quiescent Current
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) Inh = PCAin = VDD,
Zener = VCOin = 0 V, PCBin = VDD
IDD 5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
or 0 V, Iout = 0 µA
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Total Supply Current (5.) IT 5.0 IT = (1.46 µA/kHz) f + IDD mAdc
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Inh = “0”, fo = 10 kHz, CL = 50 pF, 10
R
R1 = 1.0 MΩ, R2 = RSF = ∞, 15 IT = (4.37 µA/kHz) f + IDD
ÎÎÎ
ÎÎÎ
ÎÎÎ
and 50% Duty Cycle)
4. Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level = 1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
ǒ Ǔ ǒ Ǔ
5. To Calculate Total Current in General:
IT [ 2.2 x VDD
VCOin – 1.65
R1
+
VDD – 1.35 3/4
R2
+ 1.6 x
VCOin – 1.65 3/4
RSF
+ 1 x 10–3 (CL + 9) VDD f +
1 x 10–1 VDD2 ǒ 100% Duty Cycle of PCAin

100
Ǔ + IQ where: IT in µA, CL in pF, VCOin, VDD in Vdc, f in kHz, and
R1, R2, RSF in MΩ, CL on VCOout.
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142
MC14046B
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25°C)
ÎÎÎ VDD
Minimum Maximum
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Device Typical Device Units
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 350
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 150
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 110
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 175
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 75
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 37 55
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
PHASE COMPARATORS 1 and 2
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Resistance — PCAin Rin 5.0 1.0 2.0 — MΩ
10 0.2 0.4 —
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
— PCBin ÎÎÎ
ÎÎÎÎ
ÎÎÎ Rin
15
15
0.1
150
0.2
1500
—
— MΩ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
Minimum Input Sensitivity
ÎÎÎÎ
AC Coupled — PCAin ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
C series = 1000 pF, f = 50 kHz
Vin 5.0
10
15
—
—
—
200
400
700
300
600
1050
mV p–p
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
DC Coupled — PCAin, PCBin
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
— 5 to 15 See Noise Immunity
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VOLTAGE CONTROLLED OSCILLATOR (VCO)
Maximum Frequency fmax 5.0 0.5 0.7 — MHz
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
(VCOin = VDD, C1 = 50 pF
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
R1 = 5.0 kΩ, and R2 = ∞)
ÎÎÎ
10
15
1.0
1.4
1.4
1.9
—
—
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Temperature — Frequency Stability — 5.0 — 0.12 — %/_C
(R2 = ∞ ) 10 — 0.04 —
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 0.015 —
ÎÎÎÎ
ÎÎÎÎÎ
Linearity (R2 = ∞ )
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VCOin = 2.5 V ± 0.3 V, R1 > 10 kΩ)
(VCOin = 5.0 V ± 2.5 V, R1 > 400 kΩ)
—
5.0
10
—
—
1.0
1.0
—
—
%
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VCOin = 7.5 V ± 5.0 V, R1 ≥ 1000 kΩ) 15 — 1.0 —
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Duty Cycle — 5 to 15 — 50 — %
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Resistance — VCOin Rin 15 150 1500 — MΩ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
SOURCE–FOLLOWER
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Offset Voltage — 5.0 — 1.65 2.2 V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VCOin minus SFout, RSF > 500 kΩ) 10 — 1.65 2.2
15 — 1.65 2.2
Linearity
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VCOin = 2.5 V ± 0.3 V, RSF > 50 kΩ)
(VCOin = 5.0 V ± 2.5 V, RSF > 50 kΩ)
—
5.0 — 0.1 —
%
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 0.6 —
(VCOin = 7.5 V ± 5.0 V, RSF > 50 kΩ) 15 — 0.8 —
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ZENER DIODE
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
Zener Voltage (Iz = 50 µA)
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Dynamic Resistance (Iz = 1.0 mA)
6. The formula given is for the typical characteristics only.
VZ
RZ
—
—
6.7
—
7.0
100
7.3
—
V
Ω
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143
MC14046B
PHASE COMPARATOR 1
Input Stage
00 01
X X
11 10
PCAin PCBin
PC1out 0 1
PHASE COMPARATOR 2
Input Stage
X X 00 00 00
01 10 10 01 01 10
PCAin PCBin
11 11 11
3–State
PC2out 0 1
Output Disconnected
LD (Lock Detect) 0 1 0
Refer to Waveforms in Figure 3.
Figure 1. Phase Comparators State Diagrams
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Using Phase Comparator 1 Using Phase Comparator 2
No signal on input PCAin.
VCO in PLL system adjusts to center
frequency (f0).
VCO in PLL system adjusts to minimum
frequency (fmin).
Phase angle between PCAin and PCBin. 90° at center frequency (f0), approaching Always 0_ in lock (positive rising edges).
0_ and 180° at ends of lock range (2fL)
Locks on harmonics of center frequency. Yes No
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Signal input noise rejection. High Low
Lock frequency range (2fL).
The frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2fL = full VCO frequency range = fmax – fmin.
Capture frequency range (2fC).
The frequency range of the input signal on which the loop will lock if it was initially
out of lock.
Depends on low–pass filter characteristics fC = fL
v
(see Figure 3). fC fL
Center frequency (f0). The frequency of VCOout, when VCOin = 1/2 VDD
VCO output frequency (f). 1
fmin = (VCO input = VSS)
R2(C1 + 32 pF)
Note: These equations are intended to be 1
fmax = + fmin (VCO input = VDD)
a design guide. Since calculated component
R1(C1 + 32 pF)
values may be in error by as much as a
v v
factor of 4, laboratory experimentation may Where: 10K R1 1M
v v
be required for fixed designs. Part to part 10K R2 1M
v v
frequency variation with identical passive
100pF C1 .01 µF
components is typically less than ± 20%.
Figure 2. Design Information
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144
MC14046B
9 SOURCE 10 SFout
FOLLOWER
VCOin RSF
PCAin 14 EXTERNAL
PHASE 2 OR 13 9 VCO 4 VCOout
@ FREQUENCY f′ 3 LOW–PASS
COMPARATOR PC1out 11 12 6 7 @ FREQUENCY Nf′ = f
FILTER
PCBin OR CIA CIB
PC2out R1 R2
CI
EXTERNAL
÷N
COUNTER
Typical Low–Pass Filters
Ǹ
Typically:
+ fmax
(a) R3 (a) R3
OUTPUT OUTPUT R4 C2 6N – N
INPUT INPUT 2 pD f
2 p fL
C2
2fC [p
1
R3 C2
R4
(R3 ) 3, 000W) C2 + 100N Df – R4 C2
fmax2
C2
∆ f = fmax – fmin
NOTE: Sometimes R3 is split into two series resistors each R3 ÷ 2. A capacitor CC is then placed from the midpoint to ground. The value for
CC should be such that the corner frequency of this network does not significantly affect ωn. In Figure B, the ratio of R3 to R4 sets the
damping, R4 ^
(0.1)(R3) for optimum results.
LOW–PASS FILTER
Ǹ Ǹ
Filter A Filter B
Definitions: N = Total division ratio in feedback loop
KfKVCO KfKVCO
wn + wn +
Kφ = VDD/π for Phase Comparator 1
Kφ = VDD/4 π for Phase Comparator 2 NR3C2 NC2(R3 R4) )
2 p D fVCO
+
z + 2K NKwn
KVCO
VDD – 2 V
2 p fr z + 0.5 wn ) KfKNVCO)
for a typical design ωn ^ 10
(at phase detector input) f VCO
(R3C2
^ R3C2S ) 1
+ R3C21S ) 1 F(s) +
ζ 0.707
S(R3C2 ) R4C2) ) 1
F(s)
Waveforms
Phase Comparator 1 Phase Comparator 2

VDD VDD
PCAin PCAin
VSS VSS
VOH VOH
PCBin PCBin
VOL VOL
VOH VOH
PC1out LD
VOL VOL
VOH VOH
VCOin PC2out
VOL VOL
VOH
VCOin
VOL
Note: for further information, see:
(1) F. Gardner, “Phase–Lock Techniques”, John Wiley and Son, New York, 1966.
(2) G. S. Moschytz, “Miniature RC Filters Using Phase–Locked Loop”, BSTJ, May, 1965.
(3) Garth Nash, “Phase–Lock Loop Design Fundamentals”, AN–535, Motorola Inc.
(4) A. B. Przedpelski, “Phase–Locked Loop Design Articles”, AR254, reprinted by Motorola Inc.
Figure 3. General Phase–Locked Loop Connections and Waveforms
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145
MC14049B, MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting
Hex Buffer are constructed with MOS P–Channel and N–Channel
enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power
dissipation and/or high noise immunity is desired. These devices
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provide logic level conversion using only one supply voltage, VDD.
The input–signal high level (VIH) can exceed the VDD supply MARKING
voltage for logic level conversions. Two TTL/DTL loads can be driven DIAGRAMS
16
v
when the devices are used as a CMOS–to–TTL/DTL converter (VDD
= 5.0 V, VOL 0.4 V, IOL ≥ 3.2 mA). PDIP–16
MC140XXBCP
P SUFFIX
Note that pins 13 and 16 are not connected internally on these AWLYYWW
CASE 648
devices; consequently connections to these terminals will not affect
1
circuit operation. 16
• High Source and Sink Currents SOIC–16
140XXB
D SUFFIX
• High–to–Low Level Converter CASE 751B
AWLYWW
• Supply Voltage Range = 3.0 V to 18 V 1 16

• VIN can exceed VDD
TSSOP–16 14
• Meets JEDEC B Specifications DT SUFFIX 0XXB
• Improved ESD Protection On All Inputs CASE 948F ALYW

16
F SUFFIX MC140XXB
CASE 966
Vin Input Voltage Range – 0.5 to +18.0 V
(DC or Transient) 1
Vout Output Voltage Range – 0.5 to VDD + 0.5 V A = Assembly Location
(DC or Transient) WL or L = Wafer Lot
YY or Y = Year
Iin Input Current ± 10 mA
WW or W = Work Week
Iout Output Current ± 45 mA ORDERING INFORMATION
PD Power Dissipation, mW
(Plastic) 825
(SOIC) 740 MC14049BD SOIC–16 2400/Box
TA Ambient Temperature Range – 55 to +125 °C MC14049BDR2 SOIC–16 2500/Tape & Reel

Tstg Storage Temperature Range – 65 to +150 °C MC14049BF SOEIAJ–16 See Note 1.
2. Maximum Ratings are those values beyond which damage to the device MC14050BD SOIC–16 2400/Box
may occur.
3. Temperature Derating: See Figure 3. MC14050BDR2 SOIC–16 2500/Tape & Reel
This device contains protection circuitry to protect the inputs against damage MC14050BDTEL TSSOP–16 2000/Tape & Reel
due to high static voltages or electric fields referenced to the VSS pin only. Extra
precautions must be taken to avoid applications of any voltage higher than the
maximum rated voltages to this high–impedance circuit. For proper operation, the
ranges VSS ≤ Vin ≤ 18 V and VSS ≤ Vout ≤ VDD are recommended.

March, 2000 – Rev. 3 MC14049B/D
MC14049B, MC14050B
PIN ASSIGNMENT
VDD 1 16 NC
OUTA 2 15 OUTF
INA 3 14 INF
OUTB 4 13 NC
INB 5 12 OUTE
OUTC 6 11 INE
INC 7 10 OUTD
VSS 8 9 IND
LOGIC DIAGRAM
MC14049B MC14050B
3 2 3 2
5 4 5 4
7 6 7 6
9 10 9 10
11 12 11 12
14 15 14 15
NC = PIN 13, 16 NC = PIN 13, 16

VSS = PIN 8 VSS = PIN 8
VDD = PIN 1 VDD = PIN 1
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147
MC14049B, MC14050B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C + 25_C + 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ
Vin = 0 ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 1.6 — – 1.25 – 2.5 — – 1.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.30 – 2.6 — – 1.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.7 — – 3.75 – 10 — – 3.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 10 — 8.0 16 — 6.6 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Î
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 30 — 24 40 19 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance (Vin = 0) Cin — — — — 10 20 — — pF
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current (Per Package) IDD 5.0 — 1.0 — 0.002 1.0 — 30 µAdc
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10 — 2.0 — 0.004 2.0 — 60
15 — 4.0 — 0.006 4.0 — 120
ÎÎÎÎ
ÎÎÎ
(Dynamic plus Quiescent, ÎÎÎ
ÎÎÎ
IT 5.0
10
µAdc
ÎÎÎÎ
ÎÎÎ
per package) 15
ÎÎÎÎ
ÎÎÎ
buffers switching
5. The formulas given are for the typical characteristics only at + 25_C
IT(CL) = IT(50 pF) + (CL – 50) Vfk
Where: IT is in µA (per Package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency and k = 0.002.
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148
MC14049B, MC14050B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
AC SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = + 25_C)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH = (0.7 ns/pF) CL + 65 ns 5.0 — 100 160
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH = (0.25 ns/pF) CL + 37.5 ns 10 — 50 80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH = (0.2 ns/pF) CL + 30 ns 15 — 40 60
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.2 ns/pF) CL + 30 ns 5.0 — 40 60
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.06 ns/pF) CL + 17 ns 10 — 20 40
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.04 ns/pF) CL + 13 ns 15 — 15 30
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH = (0.33 ns/pF) CL + 63.5 ns 5.0 — 80 140
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH = (0.19 ns/pF) CL + 30.5 ns 10 — 40 80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH = (0.06 ns/pF) CL + 27 ns 15 — 30 60
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time tPHL ns
tPHL = (0.2 ns/pF) CL + 30 ns 5.0 — 40 80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL = (0.1 ns/pF) CL + 15 ns 10 — 20 40
tPHL = (0.05 ns/pF) CL + 12.5 ns 15 — 15 30
8. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14049B MC14050B MC14049B MC14050B

VDD VDD VDD VDD
1 1 1 1
IOH IOL IOL IOH

VOH VOL VOL VOH
VSS 8 VSS 8 VSS VSS
8 8
VDS = VOH – VDD VDD = VOL
0 160
I OH , OUTPUT SOURCE CURRNT (mAdc)
VGS = 15 Vdc
I OL, OUTPUT SINK CURRENT (mAdc)
VGS = 5.0 Vdc

– 10
120
– 20
VGS = 10 Vdc
80
– 30 VGS = 10 Vdc
MAXIMUM CURRENT LEVEL
40
– 40 VGS = 15 Vdc
MAXIMUM CURRENT LEVEL VGS = 5.0 Vdc
– 50 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0 2.0 4.0 6.0 8.0 10
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149
MC14049B, MC14050B
1200
PD , MAXIMUM POWER DISSIPATION (mW)

1100
1000
900
825
800
PER PACKAGE
740
700
600
500 (P) PDIP
400
300 (D) SOIC
200 175 mW (P)
100 120 mW (D)
0
25 50 75 100 125 150 175
TA, AMBIENT TEMPERATURE (°C)
Figure 3. Ambient Temperature Power Derating
20 ns 20 ns
VDD
INPUT 90%
50%
VDD 10% VSS
tPHL tPLH
1
# 90% VOH
OUTPUT
PULSE 50%
MC14049B
GENERATOR 10%
Vin Vout VOL
tPLH tTHL tTLH
8 VSS CL tPHL tPHL
VOH
OUTPUT 90%
MC14050B 50%
# Invert on MC14049B only 10% VOL
tTLH tTHL
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150
MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logic–level conversion using only one
http://onsemi.com
supply voltage, VDD. The input–signal high level (VIH) can exceed the
VDD supply voltage for logic–level conversions. Two TTL/DTL MARKING
v
Loads can be driven when the device is used as CMOS–to–TTL/DTL DIAGRAMS
converters (VDD = 5.0 V, VOL 0.4 V, IOL ≥ 3.2 mA). Note that pins 16
13 and 16 are not connected internally on this device; consequently PDIP–16
connections to these terminals will not affect circuit operation. P SUFFIX MC14049UBCP
AWLYYWW
• High Source and Sink Currents
CASE 648
1
• High–to–Low Level Converter
• Supply Voltage Range = 3.0 V to 18 V 16
• Meets JEDEC UB Specifications

SOIC–16
D SUFFIX
14049U
•
AWLYWW
VIN can exceed VDD CASE 751B
• Improved ESD Protection on All Inputs 1
16
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) TSSOP–16 14

DT SUFFIX 049U
CASE 948F ALYW
1
Vin Input Voltage Range – 0.5 to +18.0 V
SOEIAJ–16
Vout Output Voltage Range – 0.5 to VDD +0.5 V MC14049U
F SUFFIX
(DC or Transient) AWLYWW
CASE 966
Iin Input Current ± 10 mA
1
Iout Output Current +45 mA A = Assembly Location
YY or Y = Year
PD Power Dissipation, mW WW or W = Work Week
Plastic 825
SOIC 740 ORDERING INFORMATION
(8–Second Soldering) MC14049UBD SOIC–16 2400/Box
2. Maximum Ratings are those values beyond which damage to the device MC14049UBDR2 SOIC–16 2500/Tape & Reel
may occur.
3. Temperature Derating: MC14049UBDT TSSOP–16 96/Rail
All Packages: See Figure 4.
MC14049UBDTR2 TSSOP–16 2500/Tape & Reel
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the VSS pin, only. Extra precautions MC14049UBF SOEIAJ–16 See Note 1.
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this high–impedance circuit. For proper operation, the ranges VSS v MC14049UBFEL SOEIAJ–16 See Note 1.
Vin v 18 V and VSS v Vout v VDD are recommended.

MC14049UB
PIN ASSIGNMENT LOGIC DIAGRAM CIRCUIT SCHEMATIC

MC14049UB (1/6 OF CIRCUIT SHOWN)
VDD 1 16 NC
VDD
3 2
OUTA 2 15 OUTF
INA 3 14 INF
5 4 MC14049UB
OUTB 4 13 NC
INB 5 12 OUTE 7 6
OUTC 6 11 INE
INC 7 10 OUTD 9 10
VSS 8 9 IND
11 12
NC = NO CONNECTION NC = PIN 13, 16
VSS = PIN 8
14 15 VSS
VDD = PIN 1
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 Vdc) 5.0 — 1.0 — 2.25 1.0 — 1.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 Vdc) 10 — 2.0 — 4.50 2.0 — 2.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 Vdc) 15 — 2.5 — 6.75 2.5 — 2.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 Vdc) 5.0 4.0 — 4.0 2.75 — 4.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 Vdc) 10 8.0 — 8.0 5.50 — 8.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 Vdc) 15 12.5 — 12.5 8.25 — 12.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 1.6 — – 1.25 – 2.5 — – 1.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.6 — – 1.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.7 — – 3.75 – 10 — – 3.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 10 — 8.0 16 — 6.6 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Î
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 30 — 24 40 — 19 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance (Vin = 0) Cin — — — — 10 20 — — pF
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 1.0 — 0.002 1.0 — 30 µAdc
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 2.0 — 0.004 2.0 — 60
15 — 4.0 — 0.006 4.0 — 120
ÎÎÎÎ
ÎÎÎ
(Dynamic plus Quiescent, ÎÎÎ
ÎÎÎ
IT 5.0
10
µAdc
ÎÎÎÎ
ÎÎÎ
Per Package) 15
ÎÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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152
MC14049UB
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH = (0.8 ns/pF) CL + 60 ns 5.0 — 100 160
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH = (0.3 ns/pF) CL + 35 ns 10 — 50 100
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTLH = (0.27 ns/pF) CL + 26.5 ns 15 — 40 60
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.3 ns/pF) CL + 25 ns 5.0 — 40 60
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.12 ns/pF) CL + 14 ns 10 — 20 40
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.1 ns/pF) CL + 10 ns 15 — 15 30
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH = (0.38 ns/pF) CL + 61 ns 5.0 — 80 120
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH = (0.20 ns/pF) CL + 30 ns 10 — 40 65
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH = (0.11 ns/pF) CL + 24.5 ns 15 — 30 50
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL = (0.38 ns/pF) CL + 11 ns 5.0 — 30 60
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL = (0.12 ns/PF) CL + 9 ns 10 — 15 30
tPHL = (0.11 ns/pF) CL + 4.5 ns 15 — 10 20
18
VDD = 15 Vdc
15
VDD = 10 Vdc
10 – 55°C
VDD = 5 Vdc
5
+125°C
5 10 15 18
Figure 1. Typical Voltage Transfer Characteristics versus Temperature
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153
MC14049UB
VDD VDD
1 1
IOH IOL
VOH VOL
VSS 8 VSS
8
VDS = VOH – VDD VDD = VOL
0 160
I OH , OUTPUT SOURCE CURRNT (mAdc)
VGS = 15 Vdc
I OL, OUTPUT SINK CURRENT (mAdc)

VGS = 5.0 Vdc
– 10
120
– 20
VGS = 10 Vdc
80
– 30 VGS = 10 Vdc
MAXIMUM CURRENT LEVEL
40
– 40 VGS = 15 Vdc
MAXIMUM CURRENT LEVEL VGS = 5.0 Vdc
– 50 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0 2.0 4.0 6.0 8.0 10
VDD
1
PULSE
Vout
1200 GENERATOR
Vin
PD , MAXIMUM POWER DISSIPATION (mW)
1100
8 VSS CL
1000
900
825
800 20 ns 20 ns
PER PACKAGE
740
700
VDD
600 INPUT 90%
500 (P) PDIP 50%
400 10% VSS
300 (D) SOIC tPHL tPLH
200 175 mW (P) 90% VOH
100 120 mW (D) OUTPUT
50%
0 10%
25 50 75 100 125 150 175 VOL
tTHL tTLH
Figure 4. Ambient Temperature Power Derating Figure 5. Switching Time Test Circuit
and Waveforms
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154
MC14051B, MC14052B,
MC14053B
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitally–controlled analog switches. The MC14051B effectively http://onsemi.com
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
MARKING
impedance and very low OFF leakage current. Control of analog
DIAGRAMS
signals up to the complete supply voltage range can be achieved.
16
• Triple Diode Protection on Control Inputs PDIP–16
• Switch Function is Break Before Make P SUFFIX MC140XXBCP
AWLYYWW
•
CASE 648
Supply Voltage Range = 3.0 Vdc to 18 Vdc
1
• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V
Note: VEE must be VSS v 16
• Linearized Transfer Characteristics SOIC–16
140XXB
• Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical D SUFFIX AWLYWW
CASE 751B
• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053 1
• For 4PDT Switch, See MC14551B
• For Lower RON, Use the HC4051, HC4052, or HC4053 High–Speed 16
CMOS Devices TSSOP–16 14
DT SUFFIX 0XXB
MAXIMUM RATINGS (Note 1.) CASE 948F ALYW
1
VDD DC Supply Voltage (Referenced – 0.5 to +18.0 V
to VEE, VSS ≥ VEE) 16
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V SOEIAJ–16
(DC or Transient) (Referen– F SUFFIX MC140XXB
ced to VSS for Control Inputs CASE 966 AWLYWW
and VEE for Switch I/O)
1
Iin Input Current (DC or Transient) ± 10 mA
per Control Pin
ISW Switch Through Current ± 25 mA XX = Specific Device Code
PD Power Dissipation, 500 mW WL or L = Wafer Lot
per Package (Note 2.) YY or Y = Year
WW or W = Work Week
(8–Second Soldering) ORDERING INFORMATION
1. Maximum Ratings are those values beyond which damage to the device See detailed ordering and shipping information in the package
may occur. dimensions section on page 163 of this data sheet.
either VSS, VEE or VDD). Unused outputs must be left open.

March, 2000 – Rev. 3 MC14051B/D
MC14051B, MC14052B, MC14053B
MC14051B MC14052B MC14053B

8–Channel Analog Dual 4–Channel Analog Triple 2–Channel Analog
Multiplexer/Demultiplexer Multiplexer/Demultiplexer Multiplexer/Demultiplexer
6 INHIBIT 6 INHIBIT 6 INHIBIT

11 A CONTROLS 10 A 11 A X 14
CONTROLS X 13 CONTROLS
10 B 9 B 10 B
9 C 12 X0 9 C
13 X0 14 X1 12 X0 Y 15 COMMONS
COMMONS
14 X1 15 X2 13 X1 OUT/IN
X 3 OUT/IN
15 X2 SWITCHES 11 X3 SWITCHES 2 Y0
COMMON
SWITCHES 12 X3 IN/OUT 1 Y0 IN/OUT 1 Y1
OUT/IN Y 3 Z 4
IN/OUT 1 X4 5 Y1 5 Z0
5 X5 2 Y2 3 Z1
2 X6 4 Y3
4 X7
VDD = PIN 16 VDD = PIN 16 VDD = PIN 16

VSS = PIN 8 VSS = PIN 8 VSS = PIN 8
VEE = PIN 7 VEE = PIN 7 VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.
PIN ASSIGMENT
MC14051B MC14052B MC14053B
X4 1 16 VDD Y0 1 16 VDD Y1 1 16 VDD
X6 2 15 X2 Y2 2 15 X2 Y0 2 15 Y
X 3 14 X1 Y 3 14 X1 Z1 3 14 X
X7 4 13 X0 Y3 4 13 X Z 4 13 X1
X5 5 12 X3 Y1 5 12 X0 Z0 5 12 X0
INH 6 11 A INH 6 11 X3 INH 6 11 A
VEE 7 10 B VEE 7 10 A VEE 7 10 B
VSS 8 9 C VSS 8 9 B VSS 8 9 C
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MC14051B, MC14052B, MC14053B
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
– 55_C 25_C 125_C
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Characteristic Symbol VDD Test Conditions Min Max Min Typ (3.) Max Min Max Unit
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎ
Power Supply VoltageÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
VDDÎÎ
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
ÎÎ
— VDD – 3.0 ≥ VSS ≥ VEE 3.0 18 3.0 — 18 3.0 18 V
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Range
µA
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Quiescent Current Per IDD 5.0 Control Inputs: — 5.0 — 0.005 5.0 — 150
Package 10 Vin = VSS or VDD, — 10 — 0.010 10 — 300
v
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
15 Switch I/O: VEE VI/O — 20 — 0.015 20 — 600
v VDD, and ∆Vswitch
ÎÎÎÎÎÎÎÎ
ÎÎ v
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ 500 mV (4.)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎ
ID(AV)
5.0 TA = 25_C only (The
(0.07 µA/kHz) f + IDD
µA
ÎÎ ÎÎ
(Dynamic Plus 10 channel component,
Typical (0.20 µA/kHz) f + IDD
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Quiescent, Per Package 15 (Vin – Vout)/Ron, is
not included.)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
Low–Level Input Voltage
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎ
VIL
ÎÎÎÎÎ
5.0
10
15
Ron = per spec,
Ioff = per spec
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
V
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
High–Level Input Voltage
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
VIH 5.0 Ron = per spec, 3.5 — 3.5 2.75 — 3.5 — V
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎ
10
15
Ioff = per spec 7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ± 0.00001 ± 0.1 — 1.0 µA
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE)
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Recommended VI/O — Channel On or Off 0 VDD 0 — VDD 0 VDD VPP
Peak–to–Peak Voltage
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Into or Out of the Switch
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Recommended Static or ∆Vswitch — Channel On 0 600 0 — 600 0 300 mV
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Dynamic Voltage Across
the Switch (4.) (Figure 5)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Output Offset Voltage
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VOO
ÎÎ — Vin = 0 V, No Load — — — 10 — — — µV
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ON Resistance v
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Ron 5.0 ∆Vswitch 500 mV (4.) — 800 — 250 1050 — 1200 Ω
ÎÎ ÎÎ ÎÎ
10 Vin = VIL or VIH — 400 — 120 500 — 520
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
15 (Control), and Vin = — 220 — 80 280 — 300
0 to VDD (Switch)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
∆ON Resistance Between
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
∆Ron 5.0 — 70 — 25 70 — 135 Ω
ÎÎ ÎÎ ÎÎ
Any Two Channels in the 10 — 50 — 10 50 — 95
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Same Package 15 — 45 — 10 45 — 65
± 100 ± 0.05 ± 100 ± 1000
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Off–Channel Leakage Ioff 15 Vin = VIL or VIH — — — nA
Current (Figure 10) (Control) Channel to
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Channel or Any One
Channel
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Capacitance, Switch I/O
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
CI/O — Inhibit = VDD — — — 10 — — — pF
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Capacitance, Common O/I
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
CO/I
ÎÎÎ
ÎÎÎ
— Inhibit = VDD pF
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎ
(MC14051B)
(MC14052B)
(MC14053B)
—
—
—
—
—
—
—
—
—
60
32
17
—
—
—
—
—
—
—
—
—
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Capacitance, Feedthrough
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
CI/O
ÎÎÎ
ÎÎÎ
— Pins Not Adjacent — — — 0.15 — — — pF
ÎÎ
(Channel Off)
ÎÎ ÎÎ — Pins Adjacent — — — 0.47 — —
3. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
—
4. For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the
Maximum Ratings are exceeded. (See first page of this data sheet.)
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MC14051B, MC14052B, MC14053B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ELECTRICAL CHARACTERISTICS (5.) (CL = 50 pF, TA = 25_C) (VEE
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VSS unless otherwise indicated)
VDD – VEE Typ (6.)
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc All Types Max Unit
Propagation Delay Times (Figure 6) tPLH, tPHL ns
MC14051
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Switch Input to Switch Output (RL = 10 kΩ)
ÎÎÎ
tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns 5.0 35 90
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns 15 12 30
MC14052 ns
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns
ÎÎÎ
5.0
10
15
30
12
10
75
30
25
ÎÎÎÎÎ
MC14053
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns 5.0 25 65
ns
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns 10 8.0 20
tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns 15 6.0 15
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Inhibit to Output (RL = 10 kΩ, VEE = VSS)
ÎÎÎÎÎ
ÎÎÎ
Output “1” or “0” to High Impedance, or
High Impedance to “1” or “0” Level
tPHZ, tPLZ,
tPZH, tPZL
ns
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MC14051B 5.0 350 700
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
10 170 340
15 140 280
ÎÎÎÎÎ
MC14052B
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
5.0
10
15
300
155
125
600
310
250
ns
ÎÎÎÎÎ
MC14053B
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
5.0
10
275
140
550
280
ns
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
15 110 220
Control Input to Output (RL = 10 kΩ, VEE = VSS) tPLH, tPHL ns
MC14051B
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
5.0
10
15
360
160
120
720
320
240
ÎÎÎÎÎ
MC14052B
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
5.0
10
325
130
650
260
ns
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
15 90 180
MC14053B 5.0 300 600 ns
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
10
15
120
80
240
160
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Second Harmonic Distortion — 10 0.07 — %
(RL = 10KΩ, f = 1 kHz) Vin = 5 VPP
ÎÎÎÎÎ
Bandwidth (Figure 7)
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, CL = 50pF
20 Log (Vout/Vin) = – 3 dB)
BW 10 17 — MHz
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Off Channel Feedthrough Attenuation (Figure 7)
ÎÎÎÎÎ
ÎÎÎ
RL = 1KΩ, Vin = 1/2 (VDD – VEE) p–p
fin = 4.5 MHz — MC14051B
— 10 – 50 — dB
ÎÎÎÎÎ
fin = 30 MHz — MC14052B
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
fin = 55 MHz — MC14053B
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Channel Separation (Figure 8) — 10 – 50 — dB
(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p,
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
fin = 3.0 MHz
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Crosstalk, Control Input to Common O/I (Figure 9) — 10 75 — mV
(R1 = 1 kΩ, RL = 10 kΩ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Control tTLH = tTHL = 20 ns, Inhibit = VSS)
6. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.
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MC14051B, MC14052B, MC14053B
VDD VDD VDD

IN/OUT OUT/IN
VEE
VDD
LEVEL
CONVERTED
IN/OUT OUT/IN
CONTROL
CONTROL
VEE
Figure 1. Switch Circuit Schematic
TRUTH TABLE 16 VDD

Control Inputs
INH 6 BINARY TO 1–OF–8
Select ON Switches A 11 LEVEL
DECODER WITH
Inhibit C* B A MC14051B MC14052B MC14053B B 10 CONVERTER
C 9 INHIBIT
0 0 0 0 X0 Y0 X0 Z0 Y0 X0
0 0 0 1 X1 Y1 X1 Z0 Y0 X1 8 VSS 7 VEE
0 0 1 0 X2 Y2 X2 Z0 Y1 X0 X0 13
0 0 1 1 X3 Y3 X3 Z0 Y1 X1 X1 14
0 1 0 0 X4 Z1 Y0 X0 X2 15
0 1 0 1 X5 Z1 Y0 X1 X3 12 3 X
0 1 1 0 X6 Z1 Y1 X0 X4 1
0 1 1 1 X7 Z1 Y1 X1 X5 5
1 x x x None None None X6 2
*Not applicable for MC14052 X7 4
x = Don’t Care
Figure 2. MC14051B Functional Diagram
16 VDD
16 VDD
INH 6 BINARY TO 1–OF–4
LEVEL
A 10 DECODER WITH INH 6 BINARY TO 1–OF–2
CONVERTER A 11 LEVEL
B 9 INHIBIT DECODER WITH
B 10 CONVERTER
C 9 INHIBIT
8 VSS 7 VEE
X0 12 8 VSS 7 VEE
X1 14
13 X
X2 15 X0 12
14 X
X3 11 X1 13
Y0 1 Y0 2
15 Y
Y1 5 Y1 1
3 Y
Y2 2 Z0 5
4 Z
Y3 4 Z1 3
Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram
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MC14051B, MC14052B, MC14053B
TEST CIRCUITS
ON SWITCH
CONTROL A
PULSE
SECTION B
GENERATOR
OF IC C
LOAD Vout
V CL
INH RL
SOURCE
VDD VEE VEE VDD
Figure 5. ∆V Across Switch Figure 6. Propagation Delay Times,

Control and Inhibit to Output
A, B, and C inputs used to turn ON

or OFF
the switch under test. RL
A
B A
C B ON
Vout
C
VSS INH RL CL = 50 pF
INH OFF
Vout
Vin RL CL = 50 pF
VDD – VEE
2 VDD – VEE Vin
2
Figure 7. Bandwidth and Off–Channel Figure 8. Channel Separation

Feedthrough Attenuation (Adjacent Channels Used For Setup)
OFF CHANNEL UNDER TEST

VDD
VEE
A CONTROL
B SECTION OTHER
C CHANNEL(S)
Vout OF IC VEE
INH RL CL = 50 pF VDD
R1
VEE
COMMON
VDD
Figure 9. Crosstalk, Control Input to Figure 10. Off Channel Leakage

Common O/I
NOTE: See also Figures 7 and 8 in the MC14016B

data sheet.
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MC14051B, MC14052B, MC14053B
VDD KEITHLEY 160

DIGITAL
MULTIMETER
10 k
1 kΩ
VDD RANGE X–Y
PLOTTER
VEE = VSS
Figure 11. Channel Resistance (RON) Test Circuit
TYPICAL RESISTANCE CHARACTERISTICS

350 350
300 300
R ON , “ON” RESISTANCE (OHMS)

250 250
200 200
150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
– 55°C – 55°C
50 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD = 7.5 V, VEE = – 7.5 V Figure 13. VDD = 5.0 V, VEE = – 5.0 V
700 350
TA = 25°C
600 300
RON , “ON” RESISTANCE (OHMS)
500 250 VDD = 2.5 V
400 200
300 150
TA = 125°C 5.0 V
200 100
25°C 7.5 V
100 – 55°C 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Figure 14. VDD = 2.5 V, VEE = – 2.5 V Figure 15. Comparison at 25°C, VDD = – VEE
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MC14051B, MC14052B, MC14053B
Figure A illustrates use of the on–chip level converter peak. If voltage transients above VDD and/or below VEE are
detailed in Figures 2, 3, and 4. The 0–to–5 V Digital Control anticipated on the analog channels, external diodes (Dx) are
signal is used to directly control a 9 Vp–p analog signal. recommended as shown in Figure B. These diodes should be
The digital control logic levels are determined by VDD small signal types able to absorb the maximum anticipated
and VSS. The VDD voltage is the logic high voltage; the VSS current surges during clipping.
voltage is logic low. For the example, VDD = + 5 V = logic The absolute maximum potential difference between
high at the control inputs; VSS = GND = 0 V = logic low. VDD and VEE is 18.0 V. Most parameters are specified up to
The maximum analog signal level is determined by VDD 15 V which is the recommended maximum difference
and VEE. The VDD voltage determines the maximum between VDD and V EE.
recommended peak above VSS. The VEE voltage Balanced supplies are not required. However, VSS must
determines the maximum swing below VSS. For the be greater than or equal to VEE. For example, VDD = + 10
example, VDD – VSS = 5 V maximum swing above VSS ; V, VSS = + 5 V, and VEE – 3 V is acceptable. See the Table
VSS – VEE = 5 V maximum swing below VSS. The example below.
shows a ± 4.5 V signal which allows a 1/2 volt margin at each
+5 V –5 V
VDD VSS VEE
+ 4.5 V
ANALOG SIGNAL I/O COMMON 9 Vp–p
GND
MC14051B O/I ANALOG SIGNAL
MC14052B
EXTERNAL MC14053B
CMOS – 4.5 V
DIGITAL
CIRCUITRY 0–TO–5 V DIGITAL INHIBIT,
CONTROL SIGNALS A, B, C
VDD VDD
DX DX
ANALOG COMMON
I/O O/I
DX DX
VEE VEE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
POSSIBLE SUPPLY CONNECTIONS
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ Control Inputs
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
VDD
ÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
In Volts
VSS
ÎÎÎÎÎÎÎÎÎ
In Volts
VEE
In Volts
Logic High/Logic Low
In Volts
Maximum Analog Signal Range
In Volts
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
+8 0 –8 + 8/0 + 8 to – 8 = 16 Vp–p
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
+5 0 – 12 + 5/0 + 5 to – 12 = 17 Vp–p
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
+5 0 0 + 5/0 + 5 to 0 = 5 Vp–p
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
+5
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
0 –5 + 5/0 + 5 to – 5 = 10 Vp–p
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
+ 10
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
+5 –5 + 10/ + 5 + 10 to – 5 = 15 Vp–p
http://onsemi.com
162
MC14051B, MC14052B, MC14053B
ORDERING & SHIPPING INFORMATION: ORDERING & SHIPPING INFORMATION:

Device Package Shipping MC14053BCP PDIP–16 2000 Units per Box
MC14051BCP PDIP–16 2000 Units per Box MC14053BD SOIC–16 48 Units per Rail
MC14051BD SOIC–16 48 Units per Rail MC14053BDR2 SOIC–16 2500 Units / Tape & Reel
MC14051BDR2 SOIC–16 2500 Units / Tape & Reel MC14053BDT TSSOP–16 96 Units per Rail
MC14051BDT TSSOP–16 96 Units per Rail MC14053BDTEL TSSOP–16 2000 Units / Tape & Reel
MC14051BDTEL TSSOP–16 2000 Units / Tape & Reel MC14053BDTR2 TSSOP–16 2500 Units / Tape & Reel
MC14051BDTR2 TSSOP–16 2500 Units / Tape & Reel MC14053BF SOEIAJ–16 See Note 7.
MC14051BF SOEIAJ–16 See Note 7. MC14053BFEL SOEIAJ–16 See Note 7.
MC14051BFEL SOEIAJ–16 See Note 7. 7. For ordering information on the EIAJ version of the SOIC
packages, please contact your local ON Semiconductor rep-
resentative.
MC14052BCP PDIP–16 2000 Units per Box
MC14052BD SOIC–16 48 Units per Rail
MC14052BDT TSSOP–16 96 Units per Rail
MC14052BDTR2 TSSOP–16 2500 Units / Tape & Reel
http://onsemi.com
163
MC14060B
14-Bit Binary Counter and

Oscillator
The MC14060B is a 14–stage binary ripple counter with an on–chip
oscillator buffer. The oscillator configuration allows design of either
RC or crystal oscillator circuits. Also included on the chip is a reset
function which places all outputs into the zero state and disables the http://onsemi.com
oscillator. A negative transition on Clock will advance the counter to
the next state. Schmitt trigger action on the input line permits very MARKING
slow input rise and fall times. Applications include time delay circuits, DIAGRAMS
16
counter controls, and frequency dividing circuits.
PDIP–16
• Fully static operation P SUFFIX MC14060BCP
AWLYYWW
• Diode Protection on All Inputs CASE 648
• Supply Voltage Range = 3.0 V to 18 V

1

Schottky TTL Load Over the Rated Temperature Range SOIC–16
14060B
• Buffered Outputs Available from Stages 4 Through 10 and
D SUFFIX
CASE 751B
AWLYWW
12 Through 14 1
• Common Reset Line
16
TSSOP–16 14
DT SUFFIX 060B
CASE 948F ALYW
VDD DC Supply Voltage Range – 0.5 to +18.0 V SOEIAJ–16

F SUFFIX MC14060B
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V CASE 966 AWLYWW
(DC or Transient)
1
(DC or Transient) per Pin A = Assembly Location
WL or L = Wafer Lot
(8–Second Soldering) Device Package Shipping
2. Maximum Ratings are those values beyond which damage to the device MC14060BCP PDIP–16 2000/Box
may occur.
3. Temperature Derating: MC14060BD SOIC–16 2400/Box
static voltages or electric fields. However, precautions must be taken to avoid MC14060BDT TSSOP–16 96/Rail
MC14060BDTR2 TSSOP–16 2500/Tape & Reel


March, 2000 – Rev. 3 MC14060B/D
MC14060B
PIN ASSIGNMENT
Q12 1 16 VDD
Q13 2 15 Q10
Q14 3 14 Q8
Q6 4 13 Q9
Q5 5 12 RESET
Q7 6 11 CLOCK
Q4 7 10 OUT 1
VSS 8 9 OUT 2
TRUTH TABLE
L No Change
L Advance to next state
X H All Outputs are low
X = Don’t Care
LOGIC DIAGRAM
OUT 2
9 Q4 Q5 Q12 Q13 Q14
OUT 1 7 5 1 2 3
10
CLOCK
C Q C Q C Q C Q C Q C Q
R R R R R R
RESET
12
Q6 = PIN 4 Q8 = PIN 14 Q10 = PIN 15 VDD = PIN 16
http://onsemi.com
165
MC14060B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
“0” Level
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
V
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — V
10 9.95 — 9.95 10 — 9.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL V
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 V) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 V) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 V) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 V) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — V
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 V) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 V) 15 11.0 — 11.0 8.25 — 11.0 —
ÎÎÎÎ
ÎÎÎ
Input Voltage
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VO = 4.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“0” Level
ÎÎÎ
ÎÎÎ
(For Input 11
VIL
5.0 — 1.0 — 2.25 1.0 — 1.0
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 Vdc) and Output 10) 10 — 2.0 — 4.50 2.0 — 2.0
(VO = 13.5 Vdc) 15 — 2.5 — 6.75 2.5 — 2.5
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VO = 0.5 Vdc)
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VO = 1.0 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
“1” Level
ÎÎÎ
VIH 5.0
10
4.0
8.0
—
—
4.0
8.0
2.75
5.50
—
—
4.0
8.0
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 Vdc) 15 12.5 — 12.5 8.25 — 12.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mA
(VOH = 2.5 V) (Except Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOH = 4.6 V)
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 V)
(VOH = 13.5 V)
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Pins 9 and 10)
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 V)
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 V) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mA
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 V) 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µA
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF
µA
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Total Supply Current (5.) (6.) IT 5.0 IT = (0.25 µA/kHz) f + IDD µA
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs,
all buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
http://onsemi.com
166
MC14060B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Rise Time (Counter Outputs) tTLH 5.0 — 40 200 ns
10 — 25 100
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 20 80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Fall Time (Counter Outputs) tTHL 5.0 — 50 200 ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 30 100
15 — 20 80
ÎÎÎÎÎ
ÎÎÎÎÎ
Clock to Q4 ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH
tPHL
5.0
10
—
—
415
175
740
300
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 125 200
µs
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to Q14 5.0 — 1.5 2.7
10 — 0.7 1.3
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 0.4 1.0
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Pulse Width twH 5.0 100 65 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 40 30 —
15 30 20 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
fφ 5.0
10
—
—
5
14
3.5
8
MHz
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 17 12
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Rise and Fall Time tTLH 5.0 ns
tTHL 10 No Limit
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset Pulse Width tw 5.0 120 40 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 60 15 —
15 40 10 —
Reset to On ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL 5.0
10
15
—
—
—
170
80
60
350
160
100
ns
VDD
VDD
PULSE CLOCK
500 µF ID 0.01 µF Q4
GENERATOR
NC OUT1 Q5
NC OUT2
Qn CL
R CL
PULSE CLOCK
Q4 VSS CL
GENERATOR
NC OUT1 Q5
NC OUT2 Qn CL
R 20 ns 20 ns
CL
VSS CL 90%
CLOCK
50%
10%
tWH
20 ns 20 ns tPLH tPHL
VDD
90% 90%
50% 50%
CLOCK 10% Q
VSS 10%
50% DUTY CYCLE tTLH tTHL
http://onsemi.com
167
MC14060B
CLOCK 11
f [ 2.3 R1tcCtc
if 1 kHz ≤ f ≤ 100 kHz
RESET 10 OUT 1 9 OUT 2 and 2Rtc < RS < 10Rtc
Rtc (f in Hz, R in ohms, C in farads)
The formula may vary for other frequencies. Recommended
maximum value for the resistors in 1 MΩ.
RS Ctc
Figure 3. Oscillator Circuit Using RC Configuration
TYPICAL RC OSCILLATOR CHARACTERISTICS
8.0 100
VDD = 10 V
VDD = 15 V 50
f, OSCILLATOR FREQUENCY (kHz)

4.0 f AS A FUNCTION
FREQUENCY DEVIATION (%)
20
OF RTC
0 10 (C = 1000 pF)
(RS ≈ 2RTC)
1.0 V 5
– 4.0
2 f AS A FUNCTION
OF C
– 8.0 1 (RTC = 56 kΩ)
5.0 V
0.5 (RS = 120 k)
– 12
RTC = 56 kΩ RS = 0, f = 10.15 kHz @ VDD = 10, TA = 25°C 0.2
C = 1000 pF RS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
– 16 0.1
– 55 – 25 0 25 50 75 100 125 1.0 k 10 k 100 k 1.0 M
TA, AMBIENT TEMPERATURE (°C) RTC, RESISTANCE (OHMS)
0.0001 0.001 0.01 0.1
C, CAPACITANCE (µF)
Figure 4. RC Oscillator Stability Figure 5. RC Oscillator Frequency as a
Function of RTC and C
ÎÎÎ
ÎÎÎ
ÎÎÎ
CLOCK
11 ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ Characteristic
500 kHz 32 kHz
Circuit Circuit Unit
RESET 10 OUT 1 9 OUT 2 ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Crystal Characteristics
Resonant Frequency 500 32 kHz
ÎÎÎ
ÎÎÎ
ÎÎÎ
18M Equivalent Resistance, RS 1.0 6.2 kΩ
RO
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
External Resistor/Capacitor Values
RO
CT
47
82
750
82
kΩ
pF
ÎÎÎ
ÎÎÎ
ÎÎÎ
CS CT CS 20 20 pF
Figure 6. Typical Crystal Oscillator Circuit ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Frequency Stability
Frequency Changes as a
Function of VDD (TA = 25_C)
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
VDD Change from 5.0 V to 10 V
VDD Change from 10 V to 15 V
+ 6.0
+ 2.0
+ 2.0
+ 2.0
ppm
ppm
ÎÎÎ
ÎÎÎ
ÎÎÎ
Frequency Change as a Function
of Temperature (VDD = 10 V)
ÎÎÎ
ÎÎÎ
ÎÎÎ
TA Change from – 55_C to + 100 + 120 ppm
+ 25_C Complete Oscillator (8.)
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
TA Change from + 25_C to
+ 125_C Complete Oscillator (8.)
– 160 – 560 ppm
8. Complete oscillator includes crystal, capacitors, and resistors.

Figure 7. Typical Data for Crystal Oscillator Circuit
http://onsemi.com
168
MC14066B
Quad Analog Switch/Quad

Multiplexer
The MC14066B consists of four independent switches capable of

controlling either digital or analog signals. This quad bilateral switch
is useful in signal gating, chopper, modulator, demodulator and
CMOS logic implementation. http://onsemi.com
The MC14066B is designed to be pin–for–pin compatible with the
MC14016B, but has much lower ON resistance. Input voltage swings MARKING
as large as the full supply voltage can be controlled via each DIAGRAMS
independent control input. 14
PDIP–14
• Triple Diode Protection on All Control Inputs P SUFFIX MC14066BCP
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 646 AWLYYWW
• Linearized Transfer Characteristics 1
• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical 14
• Pin–for–Pin Replacement for CD4016, CD4016, MC14016B

SOIC–14
D SUFFIX
14066B
•
AWLYWW
For Lower RON, Use The HC4066 High–Speed CMOS Device CASE 751A
1
14
TSSOP–14 14
CASE 948G ALYW
14
F SUFFIX MC14066B
Iin Input Current (DC or Transient) ± 10 mA CASE 965 AWLYWW
per Control Pin
1
ISW Switch Through Current ± 25 mA
TA Ambient Temperature Range – 55 to +125 °C WW or W = Work Week

TL Lead Temperature 260 °C ORDERING INFORMATION
may occur. MC14066BCP PDIP–14 2000/Box
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14066BD SOIC–14 55/Rail
This device contains protection circuitry to guard against damage due to high MC14066BDR2 SOIC–14 2500/Tape & Reel
static voltages or electric fields. However, precautions must be taken to avoid 96/Rail
MC14066BDT TSSOP–14
MC14066BDTEL TSSOP–14 2000/Tape & Reel
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14066BDTR2 TSSOP–14 2500/Tape & Reel


March, 2000 – Rev. 3 MC14066B/D
MC14066B
PIN ASSIGNMENT
IN 1 1 14 VDD
IN 2 4 11 IN 4
CONTROL 2 5 10 OUT 4
CONTROL 3 6 9 OUT 3
VSS 7 8 IN 3
BLOCK DIAGRAM LOGIC DIAGRAM AND TRUTH TABLE

13 (1/4 OF DEVICE SHOWN)
CONTROL 1 2
1 OUT 1
IN/OUT OUT/IN
IN 1
5
CONTROL 2 3 CONTROL
4 OUT 2
IN 2 Control Switch Logic Diagram Restrictions
6 0 = VSS OFF VSS ≤ Vin ≤ VDD
CONTROL 3
9 VSS ≤ Vout ≤ VDD
OUT 3 1 = VDD ON
8
IN 3
12
CONTROL 4 10
11 OUT 4
IN 4 VDD = PIN 14
VSS = PIN 7
CIRCUIT SCHEMATIC
(1/4 OF CIRCUIT SHOWN)
VDD VDD VDD
VSS
VDD
VDD VDD VDD
CMOS
INPUT 300 Ω
VSS VSS
http://onsemi.com
170
MC14066B
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
– 55_C 25_C 125_C
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Power Supply Voltage
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
VDDÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎ
— 3.0 18 3.0 — 18 3.0 18 V
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Range
µA
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Quiescent Current Per IDD 5.0 Control Inputs: — 0.25 — 0.005 0.25 — 7.5
Package 10 Vin = VSS or VDD, — 0.5 — 0.010 0.5 — 15
v
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
15 Switch I/O: VSS VI/O — 1.0 — 0.015 1.0 — 30
v
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
VDD, and
v ∆Vswitch 500 mV (5.)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎ
ID(AV)
5.0 TA = 25_C only The
µA
ÎÎ ÎÎ
(Dynamic Plus Quiescent, 10 channel component,
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Per Package 15 (Vin – Vout)/Ron, is
not included.)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CONTROL INPUTS (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
Low–Level Input Voltage
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎ
VIL
ÎÎÎÎÎ
5.0
10
15
Ron = per spec,
Ioff = per spec
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
V
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
VIH 5.0 Ron = per spec, 3.5 — 3.5 2.75 — 3.5 — V
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎ
10
15
Ioff = per spec 7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µA
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
SWITCHES IN AND OUT (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Recommended Peak–to– VI/O — Channel On or Off 0 VDD 0 — VDD 0 VDD Vp–p
Peak Voltage Into or Out
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
of the Switch
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Output Offset Voltage
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VOO
ÎÎ — Vin = 0 V, No Load — — — 10 — — — µV
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ON Resistance v
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Ron 5.0 ∆Vswitch 500 mV (5.), — 800 — 250 1050 — 1200 Ω
ÎÎ ÎÎ ÎÎ
10 Vin = VIL or VIH — 400 — 120 500 — 520
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
15 (Control), and Vin = — 220 — 80 280 — 300
0 to VDD (Switch)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
∆ON Resistance Between
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
∆Ron 5.0 — 70 — 25 70 — 135 Ω
ÎÎ ÎÎ ÎÎ
Any Two Channels 10 — 50 — 10 50 — 95
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
in the Same Package 15 — 45 — 10 45 — 65
±100 ± 0.05 ±100 ± 1000
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Off–Channel Leakage Ioff 15 Vin = VIL or VIH — — — nA
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Channel or Any One
Channel
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Capacitance, Switch I/O
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
CI/O — Switch Off — — — 10 15 — — pF
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
(Switch Off) ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎ
CI/O
ÎÎÎÎÎ
—
—
— — — 0.47 — — — pF
5. For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
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171
MC14066B
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C unless otherwise noted.)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Times VSS = 0 Vdc tPLH, tPHL ns
Input to Output (RL = 10 kΩ)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.17 ns/pF) CL + 15.5 ns 5.0 — 20 40
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.08 ns/pF) CL + 6.0 ns 10 — 10 20
tPLH, tPHL = (0.06 ns/pF) CL + 4.0 ns 15 — 7.0 15
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Control to Output (RL = 1 kΩ) (Figure 2)
ÎÎÎÎ
ÎÎÎ
Output “1” to High Impedance
tPHZ
5.0 — 40 80
ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 35 70
15 — 30 60
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Output “0” to High Impedance
ÎÎÎÎ
ÎÎÎ
tPLZ 5.0
10
15
—
—
—
40
35
30
80
70
60
ns
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
High Impedance to Output “1” tPZH 5.0
10
—
—
60
20
120
40
ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 15 30
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
High Impedance to Output “0” tPZL 5.0 — 60 120 ns
10 — 20 40
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Second Harmonic Distortion ÎÎÎ
ÎÎÎÎ
ÎÎÎ VSS = – 5 Vdc —
15
5.0
—
—
15
0.1
30
— %
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
RL = 10 kΩ, f = 1.0 kHz)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Bandwidth (Switch ON) (Figure 3)
ÎÎÎÎ
ÎÎÎ
VSS = – 5 Vdc
(RL = 1 kΩ, 20 Log (Vout/Vin) = – 3 dB, CL = 50 pF,
— 5.0 — 65 — MHz
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Vin = 5 Vp–p)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Feedthrough Attenuation (Switch OFF) VSS = – 5 Vdc — 5.0 — – 50 — dB
(Vin = 5 Vp–p, RL = 1 kΩ, fin = 1.0 MHz) (Figure 3)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Channel Separation (Figure 4)
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Vin = 5 Vp–p, RL = 1 kΩ, fin = 8.0 MHz)
VSS = – 5 Vdc — 5.0 — – 50 — dB
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Switch A ON, Switch B OFF)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Crosstalk, Control Input to Signal Output (Figure 5) mVp–p
VSS = – 5 Vdc — 5.0 — 300 —
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(R1 = 1 kΩ, RL = 10 kΩ, Control tTLH = tTHL = 20 ns)
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MC14066B
TEST CIRCUITS
Vout
VC
RL CL
ON SWITCH
Vin Vx
CONTROL 20 ns
SECTION VDD
90%
OF IC VC 50%
10%
tPZH VSS
tPHZ
LOAD 90%
V Vout Vin = VDD
10%
tPZL tPLZ Vx = VSS
90%
Vout Vin = VSS
SOURCE 10% Vx = VDD
Figure 1. ∆V Across Switch Figure 2. Turn–On Delay Time Test Circuit

and Waveforms
VDD – VSS
VC = VDD FOR BANDWIDTH TEST 2
VC = VSS FOR FEEDTHROUGH TEST
VDD – VSS Vin

2
RL CL
VDD
Vin Vout
RL CL
VC
RL CL
VSS
VDD VSS
Figure 3. Bandwidth and Figure 4. Channel Separation

Feedthrough Attenuation

VDD
Vin
A
Vout VSS
1k CONTROL
RL CL = 50 pF SECTION
10 k OF IC
VSS
VC = – 5.0 V TO + 5.0 V SWING VDD
Figure 5. Crosstalk, Figure 6. Off Channel Leakage

Control to Output
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MC14066B
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 kΩ
VDD RANGE X–Y
PLOTTER
VSS
350 350
300 300

250 250
200 200
150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
– 55°C – 55°C
50 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Figure 8. VDD = 7.5 V, VSS = – 7.5 V Figure 9. VDD = 5.0 V, VSS = – 5.0 V
700 350
TA = 25°C
600 300
RON , “ON” RESISTANCE (OHMS)
500 250 VDD = 2.5 V
400 200
300 150
TA = 125°C 5.0 V
200 100
25°C 7.5 V
100 – 55°C 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Figure 10. VDD = 2.5 V, VSS = – 2.5 V Figure 11. Comparison at 25°C, VDD = – VSS
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MC14066B
Figure A illustrates use of the Analog Switch. The 0– VDD and/or below VSS are anticipated on the analog
to–5 volt digital control signal is used to directly control a channels, external diodes (Dx) are recommended as shown
5 volt peak–to–peak analog signal. in Figure B. These diodes should be small signal types able
The digital control logic levels are determined by VDD to absorb the maximum anticipated current surges during
and VSS. The VDD voltage is the logic high voltage, the VSS clipping.
high at the control inputs; VSS = GND = 0 V = logic low. VDD and VSS is 18.0 volts. Most parameters are specified up
The maximum analog signal level is determined by VDD to 15 volts which is the recommended maximum difference
and VSS. The analog voltage must not swing higher than between VDD and V SS.
VDD or lower than VSS.
The example shows a 5 volt peak–to–peak signal which
allows no margin at either peak. If voltage transients above
+5 V
VDD VSS
+ 5.0 V
5 Vp–p SWITCH
ANALOG SIGNAL IN SWITCH 5 Vp–p
+ 2.5 V
+5 V OUT ANALOG SIGNAL
GND
EXTERNAL 0–TO–5 V DIGITAL MC14066B
CMOS
CONTROL SIGNALS
DIGITAL
CIRCUITRY
VDD VDD
DX DX
SWITCH SWITCH
IN OUT
DX DX
VSS VSS
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MC14067B
Analog Multiplexers /
Demultiplexers
The MC14067 multiplexer/demultiplexer is a digitally controlled

analog switch featuring low ON resistance and very low leakage
current. This device can be used in either digital or analog
applications. http://onsemi.com
The MC14067 is a 16–channel multiplexer/demultiplexer with an
inhibit and four binary control inputs A, B, C, and D. These control MARKING
inputs select 1–of–16 channels by turning ON the appropriate analog DIAGRAMS
switch (see MC14067 truth table.) 24
• Low OFF Leakage Current

PDIP–24
P SUFFIX MC14067BCP
• Matched Channel Resistance CASE 709 AWLYYWW
• Low Quiescent Power Consumption 1

• Low Crosstalk Between Channels
24
• Wide Operating Voltage Range: 3 to 18 V SOIC–24
• Low Noise DW SUFFIX
14067B
AWLYYWW
• Pin for Pin Replacement for CD4067B CASE 751E
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
WL or L = Wafer Lot
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) YY or Y = Year
WW or W = Work Week
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
VDD DC Supply Voltage Range – 0.5 to + 18.0 V
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V ORDERING INFORMATION
(DC or Transient)
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
± 10
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Iin Input Current (DC or Transient), mA
per Control Pin MC14067BCP PDIP–24 15/Rail
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Isw Switch Through Current ± 25 mA MC14067BDW SOIC–24 30/Rail
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
PD Power Dissipation, 500 mW MC14067BDWR2 SOIC–24 1000/Tape & Reel
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
TA Ambient Temperature Range – 55 to + 125 _C
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Tstg Storage Temperature Range – 65 to + 150 _C
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
TL Lead Temperature 260 _C
may occur.
to the range VSS v(Vin or Vout) v
VDD.

March, 2000 – Rev. 3 MC14067B/D
MC14067B
MC14067 TRUTH TABLE

Control Inputs
Selected
A B C D Inh Channel
X X X X 1 None
0 0 0 0 0 X0
1 0 0 0 0 X1
0 1 0 0 0 X2
1 1 0 0 0 X3
0 0 1 0 0 X4
1 0 1 0 0 X5
0 1 1 0 0 X6
1 1 1 0 0 X7
0 0 0 1 0 X8
1 0 0 1 0 X9
0 1 0 1 0 X10
1 1 0 1 0 X11
0 0 1 1 0 X12
1 0 1 1 0 X13
0 1 1 1 0 X14
1 1 1 1 0 X15
MC14067B
PIN ASSIGNMENT
X 1 24 VDD
X7 2 23 X8
X6 3 22 X9
X5 4 21 X10
X4 5 20 X11
X3 6 19 X12
X2 7 18 X13
X1 8 17 X14
X0 9 16 X15
A 10 15 INHIBIT
B 11 14 C
VSS 12 13 D
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MC14067B
MC14067B
16–Channel Analog
Multiplexer/Demultiplexer
15 INHIBIT
10 A
CONTROLS 11 B
14 C
13 D
9 X0
8 X1
7 X2
6 X3
5 X4
COMMON
4 X5 X 1
OUT/IN
3 X6
SWITCHES 2 X7
IN/OUT 23 X8
22 X9
21 X10 VDD = PIN 24
20 X11 VSS = PIN 12
19 X12
18 X13
17 X14
16 X15
MC14067 FUNCTIONAL DIAGRAM
INHIBIT
CONTROL A
B 1–OF–16 DECODER
INPUTS C
D
X0
X1
X2
X3
X4
X5
X6
X X7 X
IN/OUT X8
X9 OUT/IN
X10
X11
X12
X13
X14
X15
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MC14067B
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎ
– 55°C 25_C 125_C
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
SUPPLY REQUIREMENTS (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Power Supply Voltage VDD — 3.0 18 3.0 — 18 3.0 18 V
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Range
µA
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Quiescent Current Per IDD 5.0 Control Inputs: Vin = — 5.0 — 0.005 5.0 — 150
Package 10 VSS or VDD, — 10 — 0.010 10 — 300
v v
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
15 Switch I/O: VSS VI/O — 20 — 0.015 20 — 600
VDD, and
ÎÎÎÎÎÎÎÎ
ÎÎÎ
v
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ ∆Vswitch 500 mV (4.)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎ
ID(AV)
5.0 TA = 25_C only (The
µA
ÎÎ
Quiescent, 15 (Vin – Vout)/Ron, is
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Per Package not included.)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
CONTROL INPUTS — INHIBIT, A, B, C, D (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Low–Level Input Voltage VIL 5.0 Ron = per spec, — 1.5 — 2.25 1.5 — 1.5 V
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
10 Ioff = per spec — 3.0 — 4.50 3.0 — 3.0
15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
VIH
ÎÎÎÎÎ
ÎÎ
5.0
10
Ron = per spec,
Ioff = per spec
3.5
7.0
—
—
3.5
7.0
2.75
5.50
—
—
3.5
7.0
—
—
V
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
15 11 — 11 8.25 — 11 —
± 0.1 ± 0.00001 ± 0.1 µA
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Input Leakage Current Iin 15 Vin = 0 or VDD — — — 1.0
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Out of the Switch
ÎÎÎ
ÎÎÎ
Peak Voltage Into or
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Dynamic Voltage
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Across the Switch (4.)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
(Figure 1)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Output Offset Voltage VOO — Vin = 0 V, No Load — — — 10 — — — µV
v
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ON Resistance Ron 5.0 ∆Vswitch 500 mV (4.), — 800 — 250 1050 — 1300 Ω
10 Vin = VIL or VIH — 400 — 120 500 — 550
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
15 (Control), and Vin — 220 — 80 280 — 320
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
0 to VDD (Switch)
∆ON Resistance Between ∆Ron Ω
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
5.0 — 70 — 25 70 — 135
Any Two Channels 10 — 50 — 10 50 — 95
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Off–Channel Leakage Ioff 15 Vin = VIL or VIH — ± 100 — ± 0.05 ±100 — ± 1000 nA
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Channel or Any One
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Channel
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Capacitance, Switch I/O CI/O — Inhibit = VDD — — — 10 — — — pF
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Capacitance, Common O/I CO/I — Inhibit = VDD pF
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎ
(MC14067B)
ÎÎÎ
—
ÎÎÎ
—
ÎÎÎ
—
ÎÎÎ
100
ÎÎÎ
—
ÎÎÎ
—
ÎÎÎ
—
(MC14097B) — — — 60 — — —
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
CI/O
ÎÎÎ
— Pins Not Adjacent — — — 0.47 — — — pF
ÎÎ
(Channel Off) — Pins Adjacent
4. For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e.
the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
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179
MC14067B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD – VSS
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Typ (5.) Max Unit
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Times tPLH, tPHL ns
Channel Input–to–Channel Output (RL = 200 kΩ)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
MC14067B (Figure 3) 5.0 35 90
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 15 40
15 12 30
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Control Input–to–Channel Output
ÎÎÎÎ
ÎÎÎ
Channel Turn–On Time (RL = 10 kΩ)
tPZH, tPZL ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
MC14067B (Figure 4) 5.0 240 600
10 115 290
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 75 190
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Channel Turn–Off Time (RL = 300 kΩ) tPHZ, tPLZ ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
MC14067B
(Figure 4) 5.0 250 625
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 120 300
15 75 190
ÎÎÎÎÎ
MC14067B ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Any Pair of Address Inputs to Output
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0 280 700
10 115 290
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Second Harmonic Distortion ÎÎÎ
ÎÎÎÎ
ÎÎÎ —
15
10
85
0.3
215
— %
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(RL = 10 kΩ, f = 1 kHz, Vin = 5 Vp–p)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ON Channel Bandwidth BW MHz
[RL = 1 kΩ, Vin = 1/2 (VDD – VSS) p–p(sine–wave)]
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
20 Log10 (Vout/Vin) = – 3 dB
ÎÎÎÎ
ÎÎÎ
Off Channel Feedthrough Attenuation
MC14067B (Figure 5)
—
10
10
15
– 40
—
— dB
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
[RL = 1 kΩ, Vin = 1/2 (VDD–VSS) p–p(sine–wave)]
fin = 20 MHz – MC14067B (Figure 5)
ÎÎÎÎÎ
Channel Separation
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
[RL = 1 kΩ, Vin = 1/2 (VDD–VSS) p–p (sine–wave)]
— 10 – 40 — dB
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
fin = 20 MHz (Figure 6)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Crosstalk, Control Inputs–to–Common O/I — 10 30 — mV
(R1 = 1 kΩ, RL = 10 kΩ,
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Control tr = tf = 20 ns, Inhibit = VSS) (Figure 7)
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180
MC14067B

ON SWITCH VDD
A VSS
CONTROL
SECTION CONTROL
OF IC SECTION OTHER
OF IC CHANNEL(S) VSS
LOAD
V VDD
SOURCE
VSS
VDD
Figure 1. ∆V Across Switch Figure 2. Off Channel Leakage
VC
PULSE A
B
GENERATOR C
VDD Vout
D
A CL = 50 pF
B INH RL
C
D Vout Vin VX
INH RL CL = 50 pF VDD VSS VSS VDD
Vin 20 ns 20 ns
90%
VC 50%
20 ns 20 ns 10%
VDD
90%
Vin 50% 90% Vin = VDD
10% Vout
VSS 50% VX = VSS
tPLH tPHL
tPZH, tPZL tPHZ, tPLZ
Vout 50%
Vout 50% Vin = VSS
10% VX = VDD
Figure 3. Propagation Delay Test Circuit Figure 4. Turn–On and Delay Turn–Off
and Waveforms Vin to Vout Test Circuit and Waveforms
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181
MC14067B
VDD
A, B, and C inputs used to turn ON or OFF RL
the switch under test. A
B ON
C
A D
B
C INH OFF
D Vout Vout
INH RL CL = 50 pF
RL CL = 50 pF
Vin Vin

Feedthrough Attenuation (Adjacent Channels Used for Setup)
A
VC B
C
D Vout
INH RL CL = 50 pF
R1
Figure 7. Crosstalk, Control to Common O/I
VA A
VB B
C
D
INH VDD
VDD CL
Vout
KEITHLEY 160
DIGITAL
MULTIMETER
VA 50%
10 k
VDD
1 kΩ
RANGE X–Y VB 50%
PLOTTER
VSS tPHL tPLH
Vout 50%
Figure 8. Channel Resistance (RON) Test Circuit Figure 9. Propagation Delay, Any Pair of
Address Inputs to Output
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182
MC14067B
350 350
300 300

250 250
200 200
150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
– 55°C – 55°C
50 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Figure 10. VDD = 7.5 V, VSS = – 7.5 V Figure 11. VDD = 5.0 V, VSS = – 5.0 V
700 350
TA = 25°C
600 RON , “ON” RESISTANCE (OHMS) 300
500 250 VDD = 2.5 V
400 200
300 150
TA = 125°C 5.0 V
200 100
25°C 7.5 V
100 – 55°C 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Figure 12. VDD = 2.5 V, VSS = – 2.5 V Figure 13. Comparison at 25°C, VDD = – VSS
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183
MC14067B
Figure A illustrates use of the Analog signal which allows no margin at either peak. If voltage
Multiplexer/Demultiplexer. The 0–to–5 volt Digital Control transients above VDD and/or below VSS are anticipated on
signal is used to directly control a 5 Vp–p analog signal. the analog channels, external diodes (Dx) are recommended
The digital control logic levels are determined by VDD as shown in Figure B. These diodes should be small signal
and VSS. The VDD voltage is the logic high voltage; the VSS types able to absorb the maximum anticipated current surges
voltage is logic low. For the example. VDD = + 5 V = logic during clipping.
high at the control inputs; VSS = GND = 0 V = logic low. The absolute maximum potential difference between VDD
The maximum analog signal level is determined by VDD and VSS is 18.0 volts. Most parameters are specified up to
and VSS. The analog voltage must swing neither higher than 15 V which is the recommended maximum difference
VDD nor lower than VSS. The example shows a 5 Vp–p between VDD and VSS.
+5 V
VDD VSS
+ 5.0 V
5 Vp–p SWITCH
ANALOG SIGNAL I/O COMMON 5 Vp–p
+ 2.5 V
+5 V O/I ANALOG SIGNAL
GND
MC14067B
EXTERNAL 0–TO–5 V DIGITAL
CMOS
CONTROL SIGNALS
DIGITAL
CIRCUITRY
VDD VDD
DX DX
SWITCH COMMON
I/O O/I
DX DX
VSS VSS
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184
MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
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• Capable of Driving Two Low–Power TTL Loads or One Low–Power MARKING
Schottky TTL Load Over the Rated Temperature Range DIAGRAMS
• Triple Diode Protection on All Inputs 14
• Pin–for–Pin Replacement for CD4069UB

PDIP–14
P SUFFIX MC14069UBCP
• Meets JEDEC UB Specifications CASE 646 AWLYYWW
1
14
SOIC–14
14069U
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) D SUFFIX AWLYWW
CASE 751A
1
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V TSSOP–14 14
(DC or Transient) DT SUFFIX 069U
Iin, Iout Input or Output Current ± 10 mA CASE 948G ALYW
1
SOEIAJ–14
MC14069U
TA Ambient Temperature Range – 55 to +125 °C F SUFFIX
CASE 965 AWLYWW
1
(8–Second Soldering) A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
may occur.
3. Temperature Derating: WW or W = Work Week
This device contains protection circuitry to guard against damage due to high ORDERING INFORMATION
applications of any voltage higher than maximum rated voltages to this Device Package Shipping
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14069UBD SOIC–14 2750/Box
MC14069UBDR2 SOIC–14 2500/Tape & Reel
MC14069UBDT TSSOP–14 96/Rail
MC14069UBDTEL TSSOP–14 2000/Tape & Reel
MC14069UBDTR2 TSSOP–14 2500/Tape & Reel
MC14069UBF SOEIAJ–14 See Note 1.


MC14069UB
PIN ASSIGNMENT
IN 1 1 14 VDD
OUT 1 2 13 IN 6
IN 2 3 12 OUT 6
OUT 2 4 11 IN 5
IN 3 5 10 OUT 5
OUT 3 6 9 IN 4
VSS 7 8 OUT 4
LOGIC DIAGRAM CIRCUIT SCHEMATIC

1 2 VDD
VDD = PIN 14
3 4 VSS = PIN 7
5 6 INPUT* OUTPUT
9 8
11 10 VSS
*Double diode protection on all
13 12 inputs not shown.
20 ns 20 ns
VDD
VDD
14 90%
PULSE OUTPUT INPUT 50%
10% VSS
GENERATOR INPUT tPHL tPLH
7 VSS CL 90% VOH
OUTPUT 50%
10% VOL
tTHL tTLH
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186
MC14069UB
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ Symbo VDD
– 55_C 25_C 125_C
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic l Vdc Min Max Min Typ (4.) Max Min Max Unit
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎ
Vin = 0
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 Vdc) 5.0 — 1.0 — 2.25 1.0 — 1.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 Vdc) 10 — 2.0 — 4.50 2.0 — 2.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 Vdc) 15 — 2.5 — 6.75 2.5 — 2.5
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 Vdc) 5.0 4.0 — 4.0 2.75 — 4.0 —
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 Vdc) 10 8.0 — 8.0 5.50 — 8.0 —
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 Vdc) 15 12.5 — 12.5 8.25 — 12.5 —
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc
ÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30
Total Supply Current (5.) (6.) IT = (0.3 µA/kHz) f + IDD/6 µAdc
ÎÎÎ
ÎÎÎ
IT 5.0
(Dynamic plus Quiescent, 10 IT = (0.6 µA/kHz) f + IDD/6
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Per Gate) (CL = 50 pF) 15 IT = (0.9 µA/kHz) f + IDD/6
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Rise and Fall Times (5.) tTLH, ns
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(CL = 50 pF) tTHL 5.0 — — — 100 200 — —
tTLH, tTHL = (1.35 ns/pF) CL + 33 ns 10 — — — 50 100 — —
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
tTLH, tTHL = (0.60 ns/pF) CL + 20 ns 15 — — — 40 80 — —
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
(CL = 50 pF) ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
Propagation Delay Times (5.)
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ

ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
tPLH,
tPHL
ns
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.90 ns/pF) CL + 20 ns 5.0 — — — 65 125 — —
tPLH, tPHL = (0.36 ns/pF) CL + 22 ns 10 — — — 40 75 — —
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 17 ns 15 — — — 30 55 —
—

IT(CL) = IT(50 pF) + (CL – 50) Vfk
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187
MC14070B, MC14077B
CMOS SSI
Quad Exclusive “OR” and “NOR” Gates
The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic http://onsemi.com
structure. These complementary MOS logic gates find primary use
where low power dissipation and/or high noise immunity is desired. MARKING
• All Outputs Buffered 14
PDIP–14
• Capable of Driving Two Low–Power TTL Loads or One Low–Power P SUFFIX MC140XXBCP
AWLYYWW
• Double Diode Protection on All Inputs 1
• MC14070B — Replacement for CD4030B and CD4070B Types 14
• MC14077B — Replacement for CD4077B Type SOIC–14
140XXB
D SUFFIX AWLYWW
CASE 751A
1

F SUFFIX MC140XXB
VDD DC Supply Voltage Range – 0.5 to +18.0 V CASE 965 AWLYWW
1
(DC or Transient)
Iin, Iout Input or Output Current ± 10 mA XX = Specific Device Code
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
may occur. MC140XXBCP PDIP–14 2000/Box
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC140XXBD SOIC–14 2750/Box
This device contains protection circuitry to guard against damage due to high MC140XXBDR2 SOIC–14 2500/Tape & Reel
MC140XXBF SOEIAJ–14 See Note 1.
MC140XXBFEL SOEIAJ–14 See Note 1.

March, 2000 – Rev. 3 MC14070B/D
MC14070B, MC14077B
PIN ASSIGNMENT
IN 1A 1 14 VDD
IN 2A 2 13 IN 2D
OUTA 3 12 IN 1D
OUTB 4 11 OUTD
IN 1B 5 10 OUTC
IN 2B 6 9 IN 2C
VSS 7 8 IN 1C
MC14070B MC14077B
QUAD Exclusive OR QUAD Exclusive NOR
Gate Gate
1 1
3 3
2 2
5 5
4 4
6 6
8 8
10 10
9 9
12 12
11 11
13 13
VDD = PIN 14
VSS = PIN 7
(BOTH DEVICES)
20 ns 20 ns
VDD VDD
90%
50%
Vin 10%
IDD VSS
1/f
Vin * 50% DUTY CYCLE
CL
*Inverted output on MC14077B only.
VDD 20 ns 20 ns
VDD
PULSE 90%
* INPUT 50%
GENERATOR 10%
# VSS
CL tPHL tPLH
VSS 90% VOH
OUTPUT 50%
10% VOL
tTHL tTLH
*Inverted output on MC14077B only.
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.
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189
MC14070B, MC14077B
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎ
ÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
ÎÎ
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
ÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
Quiescent Current
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(Per Package)
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc
ÎÎÎÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30
ÎÎ ÎÎÎ
IT 5.0
ÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
buffers switching)
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Output Rise and Fall Times (5.)
ÎÎÎ
ÎÎÎ
tTLH, ns
ÎÎ
(CL = 50 pF) tTHL
ÎÎÎÎ
5.0
ÎÎÎÎ
—
ÎÎÎ
—
ÎÎÎ
—
ÎÎÎÎ
100
ÎÎÎ
200
ÎÎÎ
—
ÎÎÎ
—
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
—
—
—
—
—
—
50
40
100
80
—
—
—
—
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Propagation Delay Times (5.) tPLH, ns
(CL = 50 pF) tPHL
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
—
—
—
—
—
—
—
—
—
175
75
55
350
150
110
—
—
—
—
—
—
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
http://onsemi.com
190
MC14076B
4-Bit D-Type Register

with Three-State Outputs
The MC14076B 4–Bit Register consists of four D–type flip–flops
operating synchronously from a common clock. OR gated
output–disable inputs force the outputs into a high–impedance state
for use in bus organized systems. OR gated data–disable inputs cause http://onsemi.com
the Q outputs to be fed back to the D inputs of the flip–flops. Thus they
are inhibited from changing state while the clocking process remains MARKING
undisturbed. An asynchronous master root is provided to clear all four DIAGRAMS
flip–flops simultaneously independent of the clock or disable inputs. 16
• Three–State Outputs with Gated Control Lines PDIP–16
MC14076BCP
P SUFFIX
• Fully Independent Clock Allows Unrestricted Operation for the Two CASE 648 AWLYYWW
Modes: Parallel Load and Do Nothing 1
• Asynchronous Master Reset
• Four Bus Buffer Registers
16
SOIC–16
• Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX
14076B
AWLYWW
• Capable of Driving Two Low–Power TTL Loads or One Low–Power CASE 751B
WL or L = Wafer Lot
YY or Y = Year
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) WW or W = Work Week

VDD DC Supply Voltage Range – 0.5 to +18.0 V ORDERING INFORMATION
(DC or Transient)
Iin, Iout Input or Output Current ± 10 mA MC14076BCP PDIP–16 2000/Box
may occur.

March, 2000 – Rev. 3 MC14076B/D
MC14076B
PIN ASSIGNMENT
{B
OUTPUT A 1 16 VDD
DISABLE 2 15 R
Q0 3 14 D0
Q1 4 13 D1
Q2 5 12 D2
Q3 6 11 D3
C 7 10 B
} DATA
DISABLE
VSS 8 9 A
BLOCK DIAGRAM
15 RESET Q0 3
14 D0
13 D1
12 D2 Q1 4
11 D3
10 B DATA
9 A DISABLE Q2 5
7 CLOCK
2 B OUTPUT
1 A DISABLE Q3 6
VDD = PIN 16
VSS = PIN 8
FUNCTION TABLE
Inputs
Data Disable
Data Output
Reset Clock A B D Q
1 X X X X 0
0 0 X X X Qn
0 1 X X Qn
0 X 1 X Qn
0 0 0 0 0
0 0 0 1 1
When either output disable A or B (or both) is (are) high the
output is disabled to the high–impedance state; however
sequential operation of the flip–flops is not affected.
X = Don’t Care.
http://onsemi.com
192
MC14076B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc
ÎÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
ÎÎÎÎ
ÎÎÎ
IT 5.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
buffers switching)
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Three–State Leakage Current
ÎÎÎ
ÎÎÎ ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0
µAdc

IT(CL) = IT(50 pF) + (CL – 50) Vfk
http://onsemi.com
193
MC14076B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to Q
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset to Q
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
to High Impedance ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
3–State Propagation Delay, Output “1” or “0”
ÎÎÎ
tPHZ, tPLZ 5.0
10
15
—
—
—
150
60
45
300
120
90
ns
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
to “1” or “0” Level ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
3–State Propagation Delay, High Impedance tPZH, tPZL 5.0
10
—
—
200
80
400
160
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 60 120
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 110 55 —
ÎÎÎÎÎ
ÎÎÎÎÎ
Reset Pulse Width ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ tWH
15
5.0
80
370
40
185
—
— ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 150 75 —
15 110 55 —
ÎÎÎÎÎ
Data Setup Time
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tsu 5.0
10
30
10
15
5
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 4 2 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Data Hold Time th 5.0 130 65 — ns
10 60 30 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Data Disable Setup Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ tsu
15
5.0
50
220
25
110
—
— ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 80 40 —
15 50 25 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Clock Pulse Rise and Fall Time
ÎÎÎÎ
ÎÎÎ
tTLH, tTHL 5.0
10
—
—
—
—
15
5
µs
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — — 4
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 9.0 4.5
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 12 6.0
http://onsemi.com
194
MC14076B
20 ns 20 ns
OUTPUT VDD
90%
DISABLE 50% 50% 10%
INPUT RISE AND FALL 20 ns A OR B VSS
INPUT 90% VDD tPLZ tPZL
D 50% ANY Q VOH
INFORMATION 90%
10% ≈ 2.5 V @ VDD = 5 V,
VSS OUTPUT
th th 10% 10 V, AND 15 V
tsu tsu tPHZ tPZH ≈ 2 V @ VDD = 5 V
20 ns
VDD ANY Q 90% ≈ 6 V @ VDD = 10 V
90%
50% OUTPUT 10% ≈ 10 V @ VDD = 15 V
10% VSS VOL
tWH tWL
OUTPUTS OUTPUTS OUTPUTS
fcl
tPHL CONNECTED DISCONNECTED CONNECTED
tPLH
VOH
90% ANY Q
Q OUTPUT 50%
10% OUTPUT
VOL
tTLH tTHL OTHER RL = 1 kΩ VDD FOR tPLZ AND tPZL
INPUTS MC14076B VSS FOR tPHZ AND tPZH
RESET = 0
OUTPUT CL
DATA DISABLE A AND B = 0
DISABLE
OUTPUT DISABLE A AND B = 0
A OR B
Figure 1. Timing Diagram Figure 2. Three–State Propagation Delay

Waveshape and Circuit
EQUIVALENT
FUNCTIONAL BLOCK DIAGRAM
OUTPUT DISABLE A 1
OUTPUT DISABLE B 2
D Q
D0 14
C
R Q 3 Q0
DATA DISABLE A 9
DATA DISABLE B 10
D Q
D1 13
C
R Q 4 Q1
CLOCK 7
D Q
D2 12
C
R Q 5 Q2
D Q
D3 11
C
R Q 6 Q3
RESET 15
http://onsemi.com
195
MC14093B
Quad 2-Input NAND"

Schmitt Trigger
The MC14093B Schmitt trigger is constructed with MOS
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B http://onsemi.com
may be used in place of the MC14011B quad 2–input NAND gate for
enhanced noise immunity or to “square up” slowly changing MARKING
waveforms. DIAGRAMS

14
PDIP–14
• Capable of Driving Two Low–Power TTL Loads or One Low–Power P SUFFIX MC14093BCP
CASE 646 AWLYYWW
• Triple Diode Protection on All Inputs 1
• Pin–for–Pin Compatible with CD4093 14
• Can be Used to Replace MC14011B

SOIC–14
D SUFFIX
14093B
AWLYWW
• Independent Schmitt–Trigger at each Input CASE 751A
1
14
TSSOP–14 14
CASE 948G ALYW
14
F SUFFIX MC14093B
Iin, Iout Input or Output Current ± 10 mA CASE 965 AWLYWW
1
per Package (Note 3.) A = Assembly Location
WL or L = Wafer Lot
TA Ambient Temperature Range – 55 to +125 °C YY or Y = Year
Tstg Storage Temperature Range – 65 to +150 °C WW or W = Work Week

(8–Second Soldering) ORDERING INFORMATION
may occur.
3. Temperature Derating: MC14093BCP PDIP–14 2000/Box
static voltages or electric fields. However, precautions must be taken to avoid MC14093BDR2 SOIC–14 2500/Tape & Reel
high–impedance circuit. For proper operation, Vin and Vout should be constrained MC14093BDT TSSOP–14 96/Rail


March, 2000 – Rev. 3 MC14093B/D
MC14093B
PIN ASSIGNMENT
IN 1A 1 14 VDD
IN 2A 2 13 IN 2D
OUTA 3 12 IN 1D
OUTB 4 11 OUTD
IN 1B 5 10 OUTC
IN 2B 6 9 IN 2C
VSS 7 8 IN 1C
LOGIC DIAGRAM
1
3
2
5
6 4
8
9 10
12
11
13
VDD = PIN 14
VSS = PIN 7
EQUIVALENT CIRCUIT SCHEMATIC

http://onsemi.com
197
MC14093B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc
ÎÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30
ÎÎÎÎ
ÎÎÎ
IT 5.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
buffers switching)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Hysteresis Voltage
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
VH† 5.0
10
15
0.3
1.2
1.6
2.0
3.4
5.0
0.3
1.2
1.6
1.1
1.7
2.1
2.0
3.4
5.0
0.3
1.2
1.6
2.0
3.4
5.0
Vdc
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Threshold Voltage
Positive–GoingÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ VT+ 5.0 2.2 3.6 2.2 2.9 3.6 2.2 3.6
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10 4.6 7.1 4.6 5.9 7.1 4.6 7.1
15 6.8 10.8 6.8 8.8 10.8 6.8 10.8
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Negative–Going
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
VT– 5.0
10
0.9
2.5
2.8
5.2
0.9
2.5
1.9
3.9
2.8
5.2
0.9
2.5
2.8
5.2
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 4.0 7.4 4.0 5.8 7.4 4.0 7.4
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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198
MC14093B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Rise Time tTLH 5.0 — 100 200 ns
10 — 50 100
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 40 80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Fall Time tTHL 5.0 — 100 200 ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 50 100
15 — 40 80
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL 5.0
10
15
—
—
—
125
50
40
250
100
80
ns
7. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
20 ns 20 ns
14 VDD
INPUT 90%
50%
PULSE OUTPUT 10% VSS
GENERATOR tPHL tPLH
INPUT VOH
7 VSS CL 90%
OUTPUT 50%
10% VOL
tTHL tTLH
VH VDD VH VDD
Vin Vin
VSS VSS
VDD VDD
Vout Vout
VSS VSS
(a) Schmitt Triggers will square up (b) A Schmitt trigger offers maximum
(a) inputs with slow rise and fall times. (b) noise immunity in gate applications.
Figure 2. Typical Schmitt Trigger Applications
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199
MC14093B
14 14
IOH IOL
VGS
Vout Vout
7 7
All unused inputs All unused inputs
connected to ground. VGS connected to ground.
0 10
c a b c 15 Vdc
b
VGS = – 5.0 Vdc a
IOH, DRAIN CURRENT (mAdc)
IOL , DRAIN CURRENT (mAdc)

– 2.0 a 8.0 VGS = 10 Vdc
b
a TA = – 55°C
b TA = + 25°C
– 4.0 6.0 c
b TA = + 125°C
a TA = – 55°C
c b TA = + 25°C
– 6.0 4.0 c TA = + 125°C
– 10 Vdc b c b – 15 Vdc a
– 8.0 2.0 b 5.0 Vdc
c
a a
– 10 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0 2.0 4.0 6.0 8.0 10

VDD
0
0 VT– VT+ VDD
VH
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200
MC14094B
8-Stage Shift/Store Register

with Three-State Outputs
The MC14094B combines an 8–stage shift register with a data latch
for each stage and a three–state output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The QS output data is for use in http://onsemi.com
high–speed cascaded systems. The Q′S output data is shifted on the
following negative clock transition for use in low–speed cascaded MARKING
systems. DIAGRAMS
16
Data from each stage of the shift register is latched on the negative
PDIP–16
transition of the strobe input. Data propagates through the latch while P SUFFIX MC14094BCP
strobe is high. CASE 648 AWLYYWW
Outputs of the eight data latches are controlled by three–state 1
buffers which are placed in the high–impedance state by a logic Low
on Output Enable. 16
• Three–State Outputs SOIC–16
14094B
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
D SUFFIX AWLYWW
CASE 751B
• Input Diode Protection 16
• Data Latch
TSSOP–16 14
• Dual Outputs for Data Out on Both Positive and DT SUFFIX 094B
Negative Clock Transitions CASE 948F ALYW
• Useful for Serial–to–Parallel Data Conversion 1
• Pin–for–Pin Compatible with CD4094B 16
SOEIAJ–16
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) F SUFFIX MC14094B
CASE 966 AWLYWW

(DC or Transient)
WL or L = Wafer Lot

may occur.
3. Temperature Derating: MC14094BDT TSSOP–16 96/Rail
applications of any voltage higher than maximum rated voltages to this 1. For ordering information on the EIAJ version of the
high–impedance circuit. For proper operation, Vin and Vout should be constrained SOIC packages, please contact your local ON
to the range VSS v (Vin or Vout) vVDD. Semiconductor representative.

March, 2000 – Rev. 3 MC14094B/D
MC14094B
PIN ASSIGNMENT
STROBE 1 16 VDD
DATA 2 15 OUTPUT
ENABLE
CLOCK 3 14 Q5
Q1 4 13 Q6
Q2 5 12 Q7
Q3 6 11 Q8
Q4 7 10 Q′S
VSS 8 9 QS
Parallel Outputs Serial Outputs

Output
Clock Enable Strobe Data Q1 QN QS * Q′S
0 X X Z Z Q7 No Chg.
0 X X Z Z No Chg. Q7
1 0 X No Chg. No Chg. Q7 No Chg.
1 1 0 0 QN–1 Q7 No Chg.
1 1 1 1 QN–1 Q7 No Chg.
1 1 1 No Chg. No Chg. No Chg. Q7
Z = High Impedance X = Don’t Care
* At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS.
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202
MC14094B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
IT 5.0
(Dynamic plus Quiescent, 10 IT = (14 µA/kHz) f + IDD
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Per Package) 15 IT = (140 µA/kHz) f + IDD
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
buffers switching)
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
3–State Output Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0
µA

IT(CL) = IT(50 pF) + (CL – 50) Vfk
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203
MC14094B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Typ (8.)
ÎÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Min Max Unit
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
tTHL 5.0
10
15
—
—
—
100
50
40
200
100
80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Clock to Serial out QS ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH,
tPHL
5.0 — 350 600
ns
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.26 ns/pF) C L + 82 ns
10
15
—
—
125
95
250
190
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to Serial out Q’S
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
10
15
—
—
110
75
220
150
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to Parallel out
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Strobe to Parallel out
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.36 ns/pF) C L + 127 ns 10 — 145 290
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Enable to Output
tPHZ, tPZL = (0.90 ns/pF) CL + 95 ns tPHZ, 5.0 — 140 280
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHZ, tPZL = (0.36 ns/PF) CL + 57 ns tPZL 10 — 75 150
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHZ, tPZL = (0.26 ns/pF) CL + 42 ns 15 — 55 110
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLZ, tPZH = (0.90 ns/pF) CL + 180 ns tPLZ, 5.0 — 225 450
tPLZ, tPZH = (0.36 ns/pF) CL + 77 ns tPZH 10 — 95 190
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLZ, tPZH = (0.26 ns/pF) CL + 57 ns 15 — 70 140
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Setup Time tsu 5.0 125 60 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Data in to Clock 10 55 30 —
15 35 20 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Hold Time th 5.0 0 – 40 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock to Data 10 20 – 10 —
15 20 0 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
Clock Pulse Width, High
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tWH 5.0
10
15
200
100
83
100
50
40
—
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tr(cl)
tf(cl)
5
10
—
—
—
—
15
5.0
µs
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — — 4.0
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
10
15
—
—
5.0
6.0
2.5
3.0
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Strobe Pulse Width tWL 5.0 200 100 — ns
10 80 40 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 70 35 —
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204
MC14094B
3–STATE TEST CIRCUIT

FOR tPHZ AND tPZH FOR tPLZ AND tPZL
VSS VDD
O.E.
1k
DATA
OUTPUT
ST
50 pF
CLOCK
BLOCK DIAGRAM
REGISTER STAGE 1 LATCH 1 3–STATE BUFFER 1

CLOCK CLOCK STROBE VDD
2 *
SERIAL CLOCK CLOCK STROBE STROBE 4 Q1
DATA IN
CLOCK CLOCK STROBE
15 *
2 5 Q2
OUTPUT REGISTER STAGE 2 LATCH 2 3–STATE BUFFER 2
ENABLE 3
REGISTER STAGE 3 LATCH 3 3–STATE BUFFER 3 6 Q3
4 7 Q4
5 14 Q5
6 13 Q6
7 12 Q7
8 REGISTER STAGE 8 LATCH 8 3–STATE BUFFER 8 11 Q8
CLOCK
CLOCK CLOCK STROBE STROBE
10 Q′S
3 * CLOCK
CLOCK CLOCK
CLOCK
CLOCK
1 STROBE *Input Protection Diodes

* CLOCK
STROBE 9 QS
STROBE
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205
MC14094B
DYNAMIC TIMING DIAGRAM
tWH
tr tf
90%
3 CLOCK 50% 50%
10%
tsu th
2 DATA IN
tWL
1 STROBE
15
OUTPUT 50% 50%
ENABLE
tPLH tPHL tPLH tPHZ tPZH tPLZ tPZL
N Q1 ³ Q7 90% 90%
10%
90%
10%
90%
10% 10%
tTLH tTHL tPLH tPHL
9 QS 50% 50%
tPLH tPHL
10 Q′S 50% 50%
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206
MC14099B
8-Bit Addressable Latches

The MC14099B is an 8–bit addressable latch. Data is entered in
serial form when the appropriate latch is addressed (via address pins
A0, A1, A2) and write disable is in the low state. For the MC14099B
the input is a unidirectional write only port.
The data is presented in parallel at the output of the eight latches
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independently of the state of Write Disable, Write/Read or Chip
Enable. MARKING
A Master Reset capability is available on both parts. DIAGRAMS
• Serial Data Input 16
• Parallel Output PDIP–16
MC14099BCP
P SUFFIX
• Master Reset CASE 648 AWLYYWW
• Capable of Driving Two Low–power TTL Loads or One Low–Power 16
Schottky TTL Load over the Rated Temperature Range
• MC14099B pin for pin compatible with CD4099B SOIC–16 14099B
DW SUFFIX
CASE 751G
AWLYYWW

F SUFFIX MC14099B
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V CASE 966 AWLYWW
(DC or Transient)
1
WW or W = Work Week
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14099BDW SOIC–16 2350/Box
This device contains protection circuitry to guard against damage due to high MC14099BDWR2 SOIC–16 1000/Tape & Reel
v v
to the range VSS (Vin or Vout) VDD.

March, 2000 – Rev. 3 MC14099B/D
MC14099B
PIN ASSIGNMENT
Q7 1 16 VDD
RESET 2 15 Q6
MC14099B
4 9
DATA 3 14 Q5 WRITE DISABLE Q0
DATA 3 10 Q1
WRITE 11
5 Q2
DISABLE 4 13 Q4 A0 8 8 12
Q3
6 13 Q4
A1 DECODER LATCHES 14
A0 5 12 Q3 A2 7
15
Q5
1 Q6
2 Q7
A1 6 11 Q2 RESET
VDD = 16
A2 7 10 Q1 VSS = 8
VSS 8 9 Q0
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Characteristic
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ Symbol
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Vin = VDD or 0
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“0” Level
ÎÎÎ
ÎÎÎ
VOL 5.0
10
—
—
0.05
0.05
—
—
0
0
0.05
0.05
—
—
0.05
0.05
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Î
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 15 22.5 — — pF
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
MC14599B — Data (pin 3)
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc
ÎÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
ÎÎÎÎ
ÎÎÎ
IT 5.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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208
MC14099B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time tPHL, ns
Data to Output Q tPLH 5.0 — 200 400
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 75 150
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 50 100
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Write Disable to Output Q 5.0 — 200 400 ns
10 — 80 160
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 60 120
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Reset to Output Q 5.0 — 175 350 ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 80 160
15 — 65 130
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
CE to Output Q (MC14599B only)
ÎÎÎ
5.0
10
15
—
—
—
225
100
75
450
200
150
ns
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time, MC14599B only
Chip Enable, Write/Read to Data
tPHL,
tPLH 5.0 — 200 400
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 80 160
15 — 65 130
ÎÎÎÎÎ
Address to Data
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0
10
—
—
200
90
400
180
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 75 150
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Pulse Widths tw(H) ns
Reset tw(L) 5.0 150 75 —
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
10
15
75
50
40
25
—
—
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Write Disable 5.0 320 160 — ns
10 160 80 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 120 60 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Set Up Time tsu ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Data to Write Disable 5.0 100 50 —
10 50 25 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 35 20 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Hold Time th ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Write Disable to Data 5.0 150 75 —
10 75 40 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 50 25 —
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Set Up Time tsu 5.0 100 45 — ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Address to Write Disable 10 80 30 —
15 40 10 —
Removal Time
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Write Disable to Address ÎÎÎ
ÎÎÎÎ
ÎÎÎ
trem 5.0
10
15
0
0
0
– 80
– 40
– 40
—
—
—
ns
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209
MC14099B
MC14099B
FUNCTION DIAGRAM
RESET 2
9 Q0
DATA 3
WRITE
4
DISABLE
EACH LATCH
TO
OTHER
LATCHES ZERO
SELECT
10 Q1
A0 5
11 Q2
12 Q3
ADDRESS OTHER LATCHES 13 Q4
A1 6
DECODER
14 Q5
15 Q6
A2 7
(M.S.B.) 1 Q7
TRUTH TABLE
Write Addressed Unaddressed
Disable Reset Latch Latches
0 0 Data Qn* CAUTION: To avoid unintentional data changes in the latches, Write
0 1 Data Reset { Disable must be active (high) during transitions on the
address inputs A0, A1, and A2.
1 0 Qn* Qn*
1 1 Reset Reset
*Qn is previous state of latch.
†Reset to zero state.
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210
MC14099B
SWITCHING WAVEFORMS
VDD
DATA OR
50%
WRITE DISABLE
VSS
tPLH tPHL
VDD
90% 50%
ADDRESS
50%
OUTPUT Q VSS
10%
tsu tw(L) trem
tTLH tTHL VDD
WRITE
50%
DISABLE
VSS
tw(H) tsu th
VDD VDD
RESET 50% DATA 50%
VSS VSS
tPHL
OUTPUT Q
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211
MC14106B
Hex Schmitt Trigger
The MC14106B hex Schmitt Trigger is constructed with MOS
dissipation and/or high noise immunity is desired. The MC14106B
may be used in place of the MC14069UB hex inverter for enhanced
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noise immunity or to “square up” slowly changing waveforms.
• Increased Hysteresis Voltage Over the MC14584B MARKING
PDIP–14
Schottky TTL Load Over the Rated Temperature Range MC14106BCP
P SUFFIX
• Pin–for–Pin Replacement for CD40106B and MM74C14 CASE 646 AWLYYWW
• Can Be Used to Replace the MC14584B or MC14069UB 1
14
SOIC–14
14106B
D SUFFIX AWLYWW
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) CASE 751A
1
14
TSSOP–14 14
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V DT SUFFIX 106B
(DC or Transient) CASE 948G ALYW
TA Ambient Temperature Range – 55 to +125 °C WW or W = Work Week

applications of any voltage higher than maximum rated voltages to this MC14106BDT TSSOP–14 96/Rail
to the range VSS v (Vin or Vout) vVDD. MC14106BDTR2 TSSOP–14 2500/Tape & Reel

March, 2000 – Rev. 3 MC14106B/D
MC14106B
LOGIC DIAGRAM
1 2
3 4
5 6
9 8
11 10
13 12
VDD = PIN 14
VSS = PIN 7
EQUIVALENT CIRCUIT SCHEMATIC

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213
MC14106B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ
Vin = 0 ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Hysteresis Voltage VH (6.) 5.0 0.3 2.0 0.3 1.1 2.0 0.3 2.0 Vdc
10 1.2 3.4 1.2 1.7 3.4 1.2 3.4
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 1.6 5.0 1.6 2.1 5.0 1.6 5.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Threshold Voltage
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Positive–Going VT+ 5.0 2.2 3.6 2.2 2.9 3.6 2.2 3.6 Vdc
10 4.6 7.1 4.6 5.9 7.1 4.6 7.1
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 6.8 10.8 6.8 8.8 10.8 6.8 10.8
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Negative–Going VT– 5.0 0.9 2.8 0.9 1.9 2.8 0.9 2.8 Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10 2.5 5.2 2.5 3.9 5.2 2.5 5.2
15 4.0 7.4 4.0 5.8 7.4 4.0 7.4
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Source
IOH
5.0
5.0
– 3.0
– 0.64
—
—
– 2.4
– 0.51
– 4.2
– 0.88
—
—
– 1.7
– 0.36
—
—
mAdc
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOH = 9.5 Vdc)
ÎÎÎ
ÎÎÎÎ
(VOH = 13.5 Vdc) ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
– 1.6
– 4.2
—
—
– 1.3
– 3.4
– 2.25
– 8.8
—
—
– 0.9
– 2.4
—
—
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 1.5 Vdc)
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ Iin
15
15
4.2
—
—
± 0.1
3.4
—
8.8
± 0.00001
—
± 0.1
2.4
—
—
± 1.0 µAdc
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎ
Input Capacitance
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 0.25 — 0.0005 0.25 — 7.5 µAdc
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ 15 — 1.0 — 0.0015 1.0 — 30
ÎÎÎÎ
ÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
ÎÎÎ
IT 5.0
10
15
µAdc
ÎÎÎÎ
ÎÎÎ
buffers switching)
ÎÎÎ
ÎÎÎ
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
6. VH = VT+ – VT– (But maximum variation of VH is specified as less that VT+ max – VT– min).
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214
MC14106B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Typ (7.)
ÎÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Min Max Unit
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
10
15
—
—
50
40
100
80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 50 100
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 40 80
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time tPLH, tPHL 5.0 — 125 250 ns
10 — 50 100
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ 15 —
40 80
VDD 20 ns 20 ns
14
INPUT VDD
PULSE OUTPUT 90%
50%
GENERATOR INPUT 10% VSS
7 VSS CL tPHL tPLH
90% VOH
OUTPUT 50%
10%
VOL
tf tr
VDD
0
0 VT– VT+ VDD
VH
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215
MC14106B
APPLICATIONS
Vin Vout
VH VDD VH VDD
Vin Vin
VSS VSS
VDD VDD
Vout Vout
VSS VSS
(a) Schmitt Triggers will square up (b) A Schmitt trigger offers maximum
inputs with slow rise and fall times. noise immunity in gate applications.
Figure 3.
VDD VDD
R
tw C
tw
Rs Rs
Vout Vout
C R
VDD
tw = RC IN
VT+
Useful as Pushbutton/Keyboard Debounce Circuit.
Figure 4. Monostable Multivibrator
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216
MC14106B
1
f
R A
Vin Vout
R t1
C
t2
VDD
Vin VT+
VSS
C
[ RC ln VTT)
V
* t1 VDD
– VT+
A
ƪǒ Ǔǒ Ǔƫ
[ RC ln VVDDDD – VTT)
– V – VSS
* t2
VT )
[ RC ln VDD – VT – VDD
1
Vout VT+
f VDD – VT ) VT –
VSS
*t1 + t2 & tPHL + tPLH Useful in discriminating against short pulse durations.
Figure 5. Astable Multivibrator Figure 6. Integrator
C
Vin
Vin
R + EDGE
– EDGE C C C
– EDGE + EDGE
VDD Vin
tw R R R
VDD
tw = RC ln
VT+
Useful as an edge detector circuit.
Figure 7. Differentiator Figure 8. Positive Edge Time Delay Circuit
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217
MC14174B
Hex Type D Flip-Flop

The MC14174B hex type D flip–flop is constructed with MOS
monolithic structure. Data on the D inputs which meets the setup time
requirements is transferred to the Q outputs on the positive edge of the
clock pulse. All six flip–flops share common clock and reset inputs.
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The reset is active low, and independent of the clock.
• Static Operation MARKING
• All Inputs and Outputs Buffered DIAGRAMS

PDIP–16
P SUFFIX MC14174BCP
• Capable of Driving Two Low–Power TTL Loads or One Low–Power CASE 648 AWLYYWW
Schottky TTL Load over the Rated Temperature Range 1
• Functional Equivalent to TTL 74174
16
SOIC–16
14174B
D SUFFIX AWLYWW
CASE 751B
16
SOEIAJ–16
F SUFFIX MC14174B
CASE 966 AWLYWW
(DC or Transient)
WW or W = Work Week

March, 2000 – Rev. 3 MC14174B/D
MC14174B
PIN ASSIGNMENT
R 1 16 VDD
Q0 2 15 Q5
D0 3 14 D5
D1 4 13 D4
Q1 5 12 Q4
D2 6 11 D3
Q2 7 10 Q3
VSS 8 9 C
BLOCK DIAGRAM
9 CLOCK Q0 2
1 RESET
Q1 5
3 D0
4 Q2 7
D1
6 D2 Q3 10
11 D3
Q4 12
13 D4
14 D5 Q5 15
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
(Positive Logic)
Inputs Output
Clock Data Reset Q
0 1 0
1 1 1
No
X 1 Q
Change
X X 0 0
X = Don’t Care
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219
MC14174B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc
ÎÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
ÎÎÎÎ
ÎÎÎ
IT 5.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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220
MC14174B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ VDD All Types
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time — Clock to Q tPLH, tPHL ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Propagation Delay Time — Reset to Q
ÎÎÎÎ
ÎÎÎ
tPHL
5.0 — 250 500
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL = (0.36 ns/pF) CL + 79 ns 10 — 100 200
tPHL = (0.26 ns/pF) CL + 62 ns 15 — 75 150
ÎÎÎÎÎ
Clock Pulse Width
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tWH 5.0
10
15
150
90
70
75
45
35
—
—
—
ns
ÎÎÎÎÎ
Reset Pulse Width
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tWL 5.0
10
200
100
100
50
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 80 40 —
Clock Pulse Frequency fcl 5.0 — 7.0 2.0 mHz
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
10
15
—
—
12
15.5
5.0
6.5
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 — — 15 ms
10 — — 5.0
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — — 4.0
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Data Setup Time tsu 5.0 40 20 — ns
10 20 10 —
ÎÎÎÎÎ
ÎÎÎÎÎ
Data Hold Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
th
15
5.0
15
80
0
40
—
— ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 40 20 —
15 30 15 —
ÎÎÎÎÎ
Reset Removal Time
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
trem 5.0
10
15
250
100
80
125
50
40
—
—
—
ns
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221
MC14174B
TIMING DIAGRAM
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222
MC14175B
Quad Type D Flip-Flop

The MC14175B quad type D flip–flop is constructed with MOS
monolithic structure. Each of the four flip–flops is positive–edge
triggered by a common clock input (C). An active–low reset input (R)
asynchronously resets all flip–flops. Each flip–flop has independent
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Data (D) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flip–flops for
MARKING
counter and toggle applications.
DIAGRAMS
• Complementary Outputs 16
• Static Operation PDIP–16
MC14175BCP
• All Inputs and Outputs Buffered P SUFFIX
CASE 648 AWLYYWW
16
• Output Compatible with Two Low–Power TTL Loads or One
SOIC–16
Low–Power Schottky TTL Load 14175B
D SUFFIX AWLYWW
• Functional Equivalent to TTL 74175 CASE 751B
1
16

F SUFFIX MC14175B

(DC or Transient)
WL or L = Wafer Lot

(8–Second Soldering) MC14175BD SOIC–16 48/Rail
may occur.
static voltages or electric fields. However, precautions must be taken to avoid 1. For ordering information on the EIAJ version of
applications of any voltage higher than maximum rated voltages to this the SOIC packages, please contact your local
high–impedance circuit. For proper operation, Vin and Vout should be constrained ON Semiconductor representative.

March, 2000 – Rev. 3 MC14175B/D
MC14175B
PIN ASSIGNMENT
R 1 16 VDD
Q0 2 15 Q3
Q0 3 14 Q3
D0 4 13 D3
D1 5 12 D2
Q1 6 11 Q2
Q1 7 10 Q2
VSS 8 9 C
BLOCK DIAGRAM
9 CLOCK Q0 2
Q0 3
1 RESET
Q1 7
4 D0 Q1 6
5 D1 Q2 10
Q2 11
12 D2
Q3 15
13 D3 Q3 14
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Inputs Outputs
Clock Data Reset Q Q
0 1 0 1
1 1 1 0
No
X 1 Q Q
Change
X X 0 0 1
X = Don’t Care
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224
MC14175B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Vin = 0 or VDD
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0
10
0.64
1.6
—
—
0.51
1.3
0.88
2.25
—
—
0.36
0.9
—
—
mAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Quiescent Current
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package)
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10
—
—
5.0
10
—
—
0.005
0.010
5.0
10
—
—
150
300
µAdc
ÎÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600
ÎÎÎÎ
ÎÎÎ
IT 5.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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225
MC14175B
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ VDD All Types
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time — Clock to Q, Q tPLH, tPHL ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Propagation Delay Time — Reset to Q, Q
ÎÎÎÎ
ÎÎÎ
tPHL, tPLH
5.0 — 325 500
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPHL = (0.36 ns/pF) CL + 112 ns 10 — 130 200
tPHL = (0.26 ns/pF) CL + 87 ns 15 — 100 150
ÎÎÎÎÎ
Clock Pulse Width
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tWH 5.0
10
15
250
100
75
110
45
35
—
—
—
ns
ÎÎÎÎÎ
Reset Pulse Width
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
tWL 5.0
10
200
80
100
40
—
—
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 60 30 —
Clock Pulse Frequency fcl 5.0 — 4.5 2.0 mHz
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
10
15
—
—
11
14
5.0
6.5
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 — — 15 ms
10 — — 5.0
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — — 4.0
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Data Setup Time tsu 5.0 120 60 — ns
10 50 25 —
ÎÎÎÎÎ
ÎÎÎÎÎ
Data Hold Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
th
15
5.0
40
80
20
40
—
— ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 40 20 —
15 30 15 —
ÎÎÎÎÎ
Reset Removal Time
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
trem 5.0
10
15
250
100
80
125
50
40
—
—
—
ns
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226
MC14175B
TIMING DIAGRAM
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227
MC14490
Hex Contact Bounce
Eliminator
The MC14490 is constructed with complementary MOS
enhancement mode devices, and is used for the elimination of
extraneous level changes that result when interfacing with mechanical
contacts. The digital contact bounce eliminator circuit takes an input http://onsemi.com
signal from a bouncing contact and generates a clean digital signal
four clock periods after the input has stabilized. The bounce eliminator MARKING
circuit will remove bounce on both the “make” and the “break” of a DIAGRAMS
contact closure. The clock for operation of the MC14490 is derived 16
from an internal R–C oscillator which requires only an external PDIP–16
P SUFFIX MC14490P
capacitor to adjust for the desired operating frequency (bounce delay). AWLYYWW
CASE 648
The clock may also be driven from an external clock source or the
1
oscillator of another MC14490 (see Figure 5).
NOTE: Immediately after power–up, the outputs of the MC14490 16
are in indeterminate states. 14490
SOIC–16
• Diode Protection on All Inputs DW SUFFIX
• Six Debouncers Per Package
CASE 751G
AWLYYWW
• Internal Pullups on All Data Inputs 1
• Can Be Used as a Digital Integrator, System Synchronizer, or Delay 16
Line SOEIAJ–16
• Internal Oscillator (R–C), or External Clock Source F SUFFIX MC14490
AWLYWW
• TTL Compatible Data Inputs/Outputs CASE 966
• Single Line Input, Debounces Both “Make” and “Break” Contacts 1
• Does Not Require “Form C” (Single Pole Double Throw) Input A = Assembly Location
WL or L = Wafer Lot
Signal YY or Y = Year
• Cascadable for Longer Time Delays WW or W = Work Week
• Schmitt Trigger on Clock Input (Pin 7)
• Supply Voltage Range = 3.0 V to 18 V ORDERING INFORMATION
• Chip Complexity: 546 FETs or 136.5 Equivalent Gates Device Package Shipping
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) MC14490DW SOIC–16 47/Rail
Symbol Parameter Value Unit MC14490DWR2 SOIC–16 1000/Tape & Reel

VDD DC Supply Voltage Range – 0.5 to +18.0 V MC14490F SOEIAJ–16 See Note 1.
MC14490FEL SOEIAJ–16 See Note 1.
(DC or Transient)
Iin Input Current ± 10 mA MC14490P PDIP–16 25/Rail
(DC or Transient) per Pin 1. For ordering information on the EIAJ version of
PD Power Dissipation, 500 mW the SOIC packages, please contact your local
TA Ambient Temperature Range – 55 to +125 °C This device contains protection circuitry to guard
against damage due to high static voltages or electric
Tstg Storage Temperature Range – 65 to +150 °C fields. However, precautions must be taken to avoid ap-
plications of any voltage higher than maximum rated
voltages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained to the
2. Maximum Ratings are those values beyond which damage to the device range VSS v v
(Vin or Vout) VDD.
may occur. Unused inputs must always be tied to an appropriate
3. Temperature Derating: logic voltage level (e.g., either VSS or VDD). Unused out-
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C puts must be left open.

March, 2000 – Rev. 3 MC14490/D
MC14490
PIN ASSIGNMENT
Ain 1 16 VDD
Bout 2 15 Aout
Cin 3 14 Bin
Dout 4 13 Cout
Ein 5 12 Din
Fout 6 11 Eout
OSCin 7 10 Fin
VSS 8 9 OSCout
BLOCK DIAGRAM
+VDD
DATA 15 Aout
1/2–BIT
Ain 1 4–BIT STATIC SHIFT REGISTER
DELAY
SHIFT LOAD
OSCILLATOR VDD = PIN 16

OSCin 7 φ1 φ1 φ2
AND φ1 φ2 VSS = PIN 8
TWO–PHASE
OSCout 9 CLOCK GENERATOR φ2
φ1 φ2
Bin 14 IDENTICAL TO ABOVE STAGE 2 Bout
φ1 φ2
Cin 3 IDENTICAL TO ABOVE STAGE 13 Cout
φ1 φ2
Din 12 IDENTICAL TO ABOVE STAGE 4 Dout
φ1 φ2
Ein 5 IDENTICAL TO ABOVE STAGE 11 Eout
φ1 φ2
Fin 10 IDENTICAL TO ABOVE STAGE 6 Fout
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MC14490
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD – 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
Input Voltage
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
ÎÎÎ
ÎÎÎ ÎÎÎ
“0” Level
ÎÎÎ
ÎÎÎ
VIL
5.0
10
—
—
1.5
3.0
—
—
2.25
4.50
1.5
3.0
—
—
1.5
3.0
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1 Level” VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOH = 2.5 V)
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Oscillator Output ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Source
IOH
5.0 – 0.6 — – 0.5 – 1.5 — – 0.4 —

mAdc
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOH = 4.6 V)
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 V)
(VOH = 13.5 V) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.12
– 0.23
– 1.4
—
—
—
– 0.1
– 0.2
– 1.2
– 0.3
– 0.8
– 3.0
—
—
—
– 0.08
– 0.16
– 1.0
—
—
—
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
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Debounce Outputs
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOH = 2.5 V) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
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5.0 – 0.9 — – 0.75 – 2.2 — – 0.6 —
ÎÎÎÎ
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ÎÎÎ
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ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 V) 5.0 – 0.19 — – 0.16 – 0.46 — – 0.12 —
(VOH = 9.5 V) 10 – 0.6 — – 0.5 – 1.2 — – 0.4 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 V) 15 1.8 — – 1.5 – 4.5 — – 1.2 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Oscillator Output Sink IOL mAdc
(VOL = 0.4 V) 5.0 0.36 — 0.3 0.9 — 0.24 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 V) 10 0.9 — 0.75 2.3 — 0.6 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 V) 15 4.2 — 3.5 10 — 2.8 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Debounce Outputs
(VOL = 0.4 V) 5.0 2.6 — 2.2 4.0 — 1.8 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 V) 10 4.0 — 3.3 9.0 — 2.7 —
(VOL = 1.5 V) 15 12 — 10 35 — 8.1 —
ÎÎÎÎ
Input Current
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
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ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
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Debounce Inputs (Vin = VDD)
IIH 15 — 2.0 — 0.2 2.0 — 11 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Oscillator — Pin 7 Iin 15 — ± 620 — ± 255 ± 400 — ± 250 µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = VSS or VDD)
Pullup Resistor Source Current IIL 5.0 175 375 140 190 255 70 225 µAdc
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = VSS)
ÎÎÎÎ
Debounce Inputs
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
340
505
740
1100
280
415
380
570
500
750
145
215
440
660
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
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ÎÎÎ
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current ISS 5.0 — 150 — 40 100 — 90
(Vin = VSS or VDD, Iout = 0 µA) 10 — 280 — 90 225 — 180
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 840 — 225 650 — 550
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MC14490
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
All Outputs
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
10
15
—
—
90
65
180
130
Output Fall Time Oscillator Output 5.0 — 100 200 ns
tTHL 10 — 50 100
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 40 80
Debounce Outputs tTHL 5.0 — 60 120
10 — 30 60
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Oscillator Input to Debounce Outputs
tPHL
15
5.0
—
—
20
285
40
570 ns
10 — 120 240
15 — 95 190
tPLH 5.0 — 370 740
10 — 160 320
15 — 120 240
Clock Frequency (50% Duly Cycle) fcl 5.0 — 2.8 1.4 MHz
(External Clock) 10 — 6 3.0
15 — 9 4.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time (See Figure 1)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ tsu 5.0 100 50 — ns
10 80 40 —
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 60 30 —
Maximum External Clock Input tr, tf 5.0 ns
ÎÎÎÎÎÎÎÎ
Rise and Fall Time
Oscillator Input
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
10
15
No Limit
Oscillator Frequency fosc, typ Hz
OSCout 5.0
Cext ≥ 100 pF*
10
Note: These equations are intended to be a design guide.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Laboratory experimentation may be required. Formulas 15
are typically ± 15% of actual frequencies.
*POWER–DOWN CONSIDERATIONS
Large values of Cext may cause problems when powering down the MC14490 because of the amount of energy stored in the
capacitor. When a system containing this device is powered down, the capacitor may discharge through the input protection
diodes at Pin 7 or the parasitic diodes at Pin 9. Current through these internal diodes must be limited to 10 mA, therefore the
turn–off time of the power supply must not be faster than t = (VDD – VSS) Cext / (10 mA). For example, If VDD – VSS = 15
V and Cext = 1 µF, the power supply must turn off no faster than t = (15 V) (1 µF) / 10 mA = 1.5 ms. This is usually not a problem
because power supplies are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of the power supply to zero volts occurs, the MC14490 may sustain damage. To avoid this
possibility, use external clamping diodes, D1 and D2, connected as shown in Figure 2.
VDD
OSCin 50%
0V
tPLH
50% 90% D1 Cext D2
Aout
10% VDD VDD
tr
tPHL 7 9
90% 50% OSCin OSCout
Aout
10%
tf
VDD
OSCin 50% MC14490
0V
tsu
Ain 50% VDD
0V
Figure 1. Switching Waveforms Figure 2. Discharge Protection During Power Down
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231
MC14490
THEORY OF OPERATION
The MC14490 Hex Contact Bounce Eliminator is After some time period of N clock periods, the contact is
basically a digital integrator. The circuit can integrate both opened and at N +1 a low is loaded into the first bit. Just after
up and down. This enables the circuit to eliminate bounce on N+1, when the input bounces low, all bits are set to a high.
both the leading and trailing edges of the signal, shown in the At N +2 nothing happens because the input and output are
timing diagram of Figure 3. low and all bits of the shift register are high. At time N +3
Each of the six Bounce Eliminators is composed of a and thereafter the input signal is a high, clean signal. At the
4–1/2–bit register (the integrator) and logic to compare the positive edge of N +6 the output goes high as a result of four
input with the contents of the shift register, as shown in lows being shifted into the shift register.
Figure 4. The shift register requires a series of timing pulses Assuming the input signal is long enough to be clocked
in order to shift the input signal into each shift register through the Bounce Eliminator, the output signal will be no
location. These timing pulses (the clock signal) are longer or shorter than the clean input signal plus or minus
represented in the upper waveform of Figure 3. Each of the one clock period.
six Bounce Eliminator circuits has an internal resistor as The amount of time distortion between the input and
shown in Figure 4. A pullup resistor was incorporated rather output signals is a function of the difference in bounce
than a pulldown resistor in order to implement switched characteristics on the edges of the input signal and the clock
ground input signals, such as those coming from relay frequency. Since most relay contacts have more bounce
contacts and push buttons. By switching ground, rather than when making as compared to breaking, the overall delay,
a power supply lead, system faults (such as shorts to ground counting bounce period, will be greater on the leading edge
on the signal input leads) will not cause excessive currents of the input signal than on the trailing edge. Thus, the output
in the wiring and contacts. Signal lead shorts to ground are signal will be shorter than the input signal — if the leading
much more probable than shorts to a power supply lead. edge bounce is included in the overall timing calculation.
When the relay contact is closed, (see Figure 4) the low The only requirement on the clock frequency in order to
level is inverted, and the shift register is loaded with a high obtain a bounce free output signal is that four clock periods
on each positive edge of the clock signal. To understand the do not occur while the input signal is in a false state.
operation, we assume all bits of the shift register are loaded Referring to Figure 3, a false state is seen to occur three times
with lows and the output is at a high level. at the beginning of the input signal. The input signal goes
At clock edge 1 (Figure 3) the input has gone low and a low three times before it finally settles down to a valid low
high has been loaded into the first bit or storage location of state. The first three low pulses are referred to as false states.
the shift register. Just after the positive edge of clock 1, the If the user has an available clock signal of the proper
input signal has bounced back to a high. This causes the shift frequency, it may be used by connecting it to the oscillator
register to be reset to lows in all four bits — thus starting the input (pin 7). However, if an external clock is not available
timing sequence over again. the user can place a small capacitor across the oscillator
During clock edges 3 to 6 the input signal has stayed low. input and output pins in order to start up an internal clock
Thus, a high has been shifted into all four shift register bits source (as shown in Figure 4). The clock signal at the
and, as shown, the output goes low during the positive edge oscillator output pin may then be used to clock other
of clock pulse 6. MC14490 Bounce Eliminator packages. With the use of the
It should be noted that there is a 3–1/2 to 4–1/2 clock MC14490, a large number of signals can be cleaned up, with
period delay between the clean input signal and output the requirement of only one small capacitor external to the
signal. In this example there is a delay of 3.8 clock periods Hex Bounce Eliminator packages.
from the beginning of the clean input signal.
1 2 3 4 5 6 N+1 N+3 N+5 N+7

OSCin OR OSCout
INPUT
OUTPUT
CONTACT CONTACT CLOSED CONTACT OPEN

OPEN (VALID TRUE SIGNAL)
CONTACT CONTACT
BOUNCING BOUNCING
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232
MC14490
+VDD
PULLUP RESISTOR
(INTERNAL) DATA
Ain 1/2 BIT 15
1 4–BIT STATIC SHIFT REGISTER Aout
DELAY
“FORM A” SHIFT LOAD
CONTACT
OSCin 7 OSCILLATOR φ1 φ2
φ1 φ1 φ2
AND
Cext 9 TWO–PHASE
CLOCK GENERATOR φ2
OSCout
Figure 4. Typical “Form A” Contact Debounce Circuit

(Only One Debouncer Shown)
OPERATING CHARACTERISTICS
The single most important characteristic of the MC14490 paralleled standard gates or by the MC14049 or MC14050
is that it works with a single signal lead as an input, making buffers.
it directly compatible with mechanical contacts (Form A The clock input circuit (pin 7) has Schmitt trigger shaping
and B). such that proper clocking will occur even with very slow
The circuit has a built–in pullup resistor on each input. clock edges, eliminating any need for clock preshaping. In
The worst case value of the pullup resistor (determined from addition, other MC14490 oscillator inputs can be driven
the Electrical Characteristics table) is used to calculate the from a single oscillator output buffered by an MC14050 (see
contact wetting current. If more contact current is required, Figure 5). Up to six MC14490s may be driven by a single
an external resistor may be connected between VDD and the buffer.
input. The MC14490 is TTL compatible on both the inputs and
Because of the built–in pullup resistors, the inputs cannot the outputs. When VDD is at 4.5 V, the buffered outputs can
be driven with a single standard CMOS gate when VDD is sink 1.6 mA at 0.4 V. The inputs can be driven with TTL as
below 5 V. At this voltage, the input should be driven with a result of the internal input pullup resistors.
NO CONNECTION
OSCin 7 9 OSCout
Cext 1/6 MC14050
FROM TO SYSTEM
MC14490
OSCin 7 9 OSCout CONTACTS LOGIC
TO SYSTEM
FROM CONTACTS MC14490 NO CONNECTION
LOGIC
OSCin 7 9 OSCout
TO SYSTEM
FROM CONTACTS MC14490
LOGIC
Figure 5. Typical Single Oscillator Debounce System
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MC14490
ASYMMETRICAL TIMING MULTIPLE TIMING SIGNALS

In applications where different leading and trailing edge As shown in Figure 8, the Bounce Eliminator circuits can
delays are required (such as a fast attack/slow release timer.) be connected in series. In this configuration each output is
Clocks of different frequencies can be gated into the delayed by four clock periods relative to its respective input.
MC14490 as shown in Figure 6. In order to produce a slow This configuration may be used to generate multiple timing
attack/fast release circuit leads A and B should be signals such as a delay line, for programming other timing
interchanged. The clock out lead can then be used to feed operations.
clock signals to the other MC14490 packages where the One application of the above is shown in Figure 9, where
asymmetrical input/output timing is required. it is required to have a single pulse output for a single
operation (make) of the push button or relay contact. This
IN OUT only requires the series connection of two Bounce
Eliminator circuits, one inverter, and one NOR gate in order
MC14490 OSCout
to generate the signal AB as shown in Figures 9 and 10. The
OSCin signal AB is four clock periods in length. If the inverter is
switched to the A output, the pulse AB will be generated
upon release or break of the contact. With the use of a few
MC14011B additional parts many different pulses and waveshapes may
be generated.
1 15
B.E. 1 Aout
A B Ain
EXTERNAL fC
÷N fC/N
CLOCK 14 2
B.E. 2 Bout
Bin
Figure 6. Fast Attack/Slow Release Circuit
3 13
B.E. 3 Cout
LATCHED OUTPUT Cin
The contents of the Bounce Eliminator can be latched by
using several extra gates as shown in Figure 7. If the latch
12 4
lead is high the clock will be stopped when the output goes B.E. 4 Dout
low. This will hold the output low even though the input has Din
returned to the high state. Any time the clock is stopped the
outputs will be representative of the input signal four clock 5 11
periods earlier. B.E. 5 Eout
Ein
IN OUT
10 6
B.E. 6 Fout
MC14490 Fin
OSCin
OSCout
MC14011B
7 9
CLOCK OSCin CLOCK OSCout
LATCH = 1
UNLATCH = 0 Figure 8. Multiple Timing Circuit Connections
Figure 7. Latched Output Circuit
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234
MC14490
IN OUT
BE 1
A A
AB
IN OUT B
BE 2
B
A ≡ ACTIVE LOW
B ≡ ACTIVE LOW
Figure 9. Single Pulse Output Circuit
OSCin OR
OSCout
INPUT
AB
AB
Figure 10. Multiple Output Signal Timing Diagram
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235
MC14503B
Hex Non-Inverting 3-State

Buffer
The MC14503B is a hex non–inverting buffer with 3–state outputs,
and a high current source and sink capability. The 3–state outputs
make it useful in common bussing applications. Two disable controls
are provided. A high level on the Disable A input causes the outputs of http://onsemi.com
buffers 1 through 4 to go into a high impedance state and a high level
on the Disable B input causes the outputs of buffers 5 and 6 to go into a MARKING
high impedance state. DIAGRAMS
• 3–State Outputs PDIP–16
16
• TTL Compatible — Will Drive One TTL Load Over Full P SUFFIX MC14503BCP
CASE 648 AWLYYWW
Temperature Range
• Two Disable Controls for Added Versatility 16

• Pin for Pin Replacement for MM80C97 and 340097 SOIC–16
14503B
D SUFFIX AWLYWW
CASE 751B
1

F SUFFIX MC14503B
CASE 966
(DC or Transient) 1
Iin Input Current ± 10 mA A = Assembly Location

YY or Y = Year
Iout Output Current ± 25 mA WW or W = Work Week
(8–Second Soldering) MC14503BD SOIC–16 48/Rail
may occur.
3. Temperature Derating: MC14503BF SOEIAJ–16 See Note 1.
static voltages or electric fields. However, precautions must be taken to avoid 1. For ordering information on the EIAJ version of

March, 2000 – Rev. 3 MC14503B/D
MC14503B
PIN ASSIGNMENT
DIS A 1 16 VDD
IN 1 2 15 DIS B
OUT 1 3 14 IN 6
IN 2 4 13 OUT 6
OUT 2 5 12 IN 5
IN 3 6 11 OUT 5
OUT 3 7 10 IN 4
VSS 8 9 OUT 4
TRUTH TABLE LOGIC DIAGRAM

Appropriate 15
Disable DISABLE B
Inn Input Outn 12 11
IN 5 OUT 5
0 0 0
14 13
1 0 1 IN 6 OUT 6
X 1 High 2 3
Impedance IN 1 OUT 1
4 5
X = Don’t Care IN 2 OUT 2
6 7
IN 3 OUT 3
10 9
IN 4 OUT 4
1
DISABLE A
VDD = PIN 16
VSS = PIN 8
CIRCUIT DIAGRAM
ONE OF TWO/FOUR BUFFERS
VDD
* INn OUTn
* DISABLE
* INPUT
VSS
TO OTHER BUFFERS
*Diode protection on all inputs (not shown)
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237
MC14503B
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Vin = VDD ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
“1” Level
ÎÎÎ
ÎÎÎ
VOH 5.0
10
4.95
9.95
—
—
4.95
9.95
5.0
10
—
—
4.95
9.95
—
—
Vdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 3.6 or 1.4 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 7.2 or 2.8 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 11.5 or 3.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.4 or 3.6 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 2.8 or 7.2 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 3.5 or 11.5 Vdc) 15 11 — 11 8.25 — 11 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 4.5 – 4.3 — – 3.6 – 5.0 — – 2.5 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) 5.0 – 5.8 — – 4.8 – 6.1 — – 3.0 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 1.2 — – 1.02 – 1.4 — – 0.7 —
(VOH = 9.5 Vdc) 10 – 3.1 — – 2.6 – 3.7 — – 1.8 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 8.2 — – 6.8 – 14.1 — – 4.8 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) 5.0 2.6 — 2.1 2.3 — 1.3 —
(VOL = 0.5 Vdc) 10 6.5 — 5.5 6.2 — 3.8 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 19.2 — 16.1 25 — 11.2 —
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = 0)
µAdc
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IQ 5.0 — 1.0 — 0.002 1.0 — 30
(Per Package) 10 — 2.0 — 0.004 2.0 — 60
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 4.0 — 0.006 4.0 — 120
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Per Package) 15 IT = (10 µA/kHz) f + IDD
ÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs)
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(All outputs switching,
50% Duty Cycle)
ÎÎÎÎ
ÎÎÎÎ
Current ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
Three–State Output Leakage
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0
µAdc
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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238
MC14503B
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
All Types
VDD
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Characteristic Symbol VCC Typ (8.) Max Unit
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tTLH = (0.5 ns/pF) CL + 20 ns 5.0 45 90
tTLH = (0.3 ns/pF) CL + 8.0 ns 10 23 45
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tTLH = (0.2 ns/pF) CL + 8.0 ns 15 18 35
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tTHL = (0.5 ns/pF) CL + 20 ns 5.0 45 90
tTHL = (0.3 ns/pF) CL + 8.0 ns 10 23 45
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tTHL = (0.2 ns/pF) CL + 8.0 ns 15 18 35
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Turn–Off Delay Time, all Outputs tPLH ns
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tPLH = (0.3 ns/pF) CL + 60 ns 5.0 75 150
tPLH = (0.15 ns/pF) CL + 27 ns 10 35 70
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tPLH = (0.1 ns/pF) CL + 20 ns 15 25 50
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Turn–On Delay Time, all Outputs tPHL ns
tPHL = (0.3 ns/pF) CL + 60 ns 5.0 75 150
ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
10
15
35
25
70
50
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
3–State Propagation Delay Time tPHZ 5.0 75 150 ns
Output “1” to High Impedance 10 40 80
ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Output “0” to High Impedance tPLZ
15
5.0
35
80
70
160 ns
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
10 40 80
15 35 70
ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
High Impedance to “1” Level
ÎÎÎÎ
ÎÎÎÎ
tPZH 5.0
10
65
25
130
50
ns
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
15 20 40
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
High Impedance to “0” Level tPZL 5.0 100 200 ns
10 35 70
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
15 25 50
DISABLE 20 ns 20 ns
INPUT VDD
VDD 90%
INPUT 50%
16 10%
VSS
INPUT tPLH tPHL
PULSE
OUTPUT VOH
GENERATOR 90%
OUTPUT 50%
VSS CL 10%
VOL
tTLH tTHL
tPLH tPHL

(tTLH, tTHL, tPHL, and tPLH)
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239
MC14503B
DISABLE INPUT DISABLE INPUT

PULSE PULSE tPLZ, tPZL CIRCUIT
GENERATOR GENERATOR
VDD VDD
tPHZ, tPZH CIRCUIT 16

16 1k
INPUT OUTPUT INPUT OUTPUT
1k CL
VSS CL
8 8 VSS
20 ns 20 ns
VDD
90%
50%
10%
DISABLE INPUT VSS
tPLZ tPZL
VOH
90%
10%
OUTPUT FOR tPZH, tPZL CIRCUIT ≈ VOL + 0.05 V
tPHZ tPZH
OUTPUT FOR tPHZ, tPLZ CIRCUIT 90% ≈ VOH – 0.15 V
10%
VOL
Figure 2. 3–State AC Test Circuit and Waveforms

(tPLZ, tPHZ, tPZH, tPZL)
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240
MC14504B
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS
The MC14504B is a hex non–inverting level shifter using CMOS
technology. The level shifter will shift a TTL signal to CMOS logic
levels for any CMOS supply voltage between 5 and 15 volts. A control
input also allows interface from CMOS to CMOS at one logic level to http://onsemi.com
another logic level: Either up or down level translating is
accomplished by selection of power supply levels VDD and VCC. The MARKING
VCC level sets the input signal levels while VDD selects the output DIAGRAMS
voltage levels. 16
• UP Translates from a Low to a High Voltage or DOWN Translates PDIP–16

P SUFFIX MC14504BCP
from a High to a Low Voltage CASE 648 AWLYYWW
• Input Threshold Can Be Shifted for TTL Compatibility 1
• No Sequencing Required on Power Supplies or Inputs for Power Up
16
or Power Down SOIC–16
• 3 to 18 Vdc Operation for VDD and VCC D SUFFIX
14504B
AWLYWW
• Diode Protected Inputs to VSS CASE 751B
• Capable of Driving Two Low–Power TTL Loads or One Low–Power

1
TSSOP–16 14
DT SUFFIX 504B
CASE 948F ALYW
1
VCC DC Supply Voltage Range – 0.5 to +18.0 V 16

F SUFFIX MC14504B
Vin Input Voltage Range – 0.5 to +18.0 V CASE 966 AWLYWW
(DC or Transient)
1
Vout Output Voltage Range – 0.5 to VDD + 0.5 V
(DC or Transient) A = Assembly Location
WL or L = Wafer Lot
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14504BDT TSSOP–16 96/Rail
This device contains protection circuitry to guard against damage due to high MC14504BF SOEIAJ–16 See Note 1.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., ON Semiconductor representative.

March, 2000 – Rev. 3 MC14504B/D
MC14504B
PIN ASSIGNMENT
VCC 1 16 VDD
Aout 2 15 Fout
Ain 3 14 Fin
Bout 4 13 MODE
Bin 5 12 Eout
Cout 6 11 Ein
Cin 7 10 Dout
VSS 8 9 Din
LOGIC DIAGRAM
VCC VDD
LEVEL
INPUT OUTPUT
SHIFTER
TTL/CMOS
MODE
MODE SELECT
Input Logic Output Logic

Mode Select Levels Levels
1 (VCC) TTL CMOS
0 (VSS) CMOS CMOS
1/6 of package shown.
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242
MC14504B
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Î ÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ VCC VDD
– 55_C 25_C 125_C
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Vdc Min Max Min Typ (4.) Max Min Max Unit
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Voltage “0” Level VOL — 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = 0 V
ÎÎÎÎ
ÎÎÎÎÎ ÎÎ
— 10
ÎÎÎ
—
ÎÎÎ
0.05
ÎÎÎ
—
ÎÎÎÎ
0
ÎÎÎ
0.05 —
ÎÎÎ
0.05
ÎÎÎÎ
Vin = VCC
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level
VOH
—
—
15
5.0 4.95
— 0.05
—
—
4.95
0
5.0
0.05
—
—
4.95
0.05
— Vdc
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
— 10 9.95 — 9.95 10 — 9.95 —
— 15 14.95 — 14.95 15 — 14.95 —
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Input Voltage
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
“0” Level
ÎÎÎ
ÎÎÎ
VIL Vdc
ÎÎ ÎÎ
(VOL = 1.0 Vdc) TTL–CMOS 5.0 10 — 0.8 — 1.3 0.8 — 0.8
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(VOL = 1.5 Vdc) TTL–CMOS 5.0 15 — 0.8 — 1.3 0.8 — 0.8
(VOL = 1.0 Vdc) CMOS–CMOS 5.0 10 — 1.5 — 2.25 1.5 — 1.4
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) CMOS–CMOS 5.0 15 — 1.5 — 2.25 1.5 — 1.5
(VOL = 1.5 Vdc) CMOS–CMOS 10 15 — 3.0 — 4.5 3.0 — 2.9
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ ÎÎ
Input Voltage “1” Level VIH Vdc
(VOH = 9.0 Vdc) TTL–CMOS 5.0 10 2.0 — 2.0 1.5 — 2.0 —
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(VOH = 13.5 Vdc) TTL–CMOS 5.0 15 2.0 — 2.0 1.5 — 2.0 —
(VOH = 9.0 Vdc) CMOS–CMOS 5.0 10 3.6 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(VOH = 13.5 Vdc) CMOS–CMOS 5.0 15 3.6 — 3.5 2.75 — 3.5 —
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) CMOS–CMOS 10 15 7.1 — 7.0 5.5 — 7.0 —
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(VOH = 2.5 Vdc) Source — 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(VOH = 4.6 Vdc) — 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) — 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎ ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ Sink IOL
—
—
15
5.0
– 4.2
0.64
—
—
– 3.4
0.51
– 8.8
0.88
—
—
– 2.4
0.36
—
— mAdc
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) — 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) — 15 4.2 — 3.4 8.8 — 2.4 —
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Iin — 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance (Vin = 0) Cin — — — — — 5.0 7.5 — — pF
µAdc
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
Quiescent Current IDD or — 5.0 — 0.05 — 0.0005 0.05 — 1.5
(Per Package) ICC — 10 — 0.10 — 0.0010 0.10 — 3.0
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
CMOS–CMOS Mode — 15 — 0.20 — 0.0015 0.20 — 6.0
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 5.0 — 0.5 — 0.0005 0.5 — 3.8 µAdc
(Per Package) 5.0 10 — 1.0 — 0.0010 1.0 — 7.5
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
TTL–CMOS Mode 5.0 15 — 2.0 — 0.0015 2.0 — 15
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current ICC 5.0 5.0 — 5.0 — 2.5 5.0 — 6.0 mAdc
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 5.0 10 — 5.0 — 2.5 5.0 — 6.0
TTL–CMOS Mode 5.0 15 — 5.0 — 2.5 5.0 — 6.0
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243
MC14504B
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
VCC VDD Limits
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic Symbol Shifting Mode Vdc Vdc Min Typ (5.) Max Unit
Propagation Delay, High to Low tPHL ns
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
TTL – CMOS 5.0 10 — 140 280
VDD > VCC 5.0 15 — 140 280
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
CMOS – CMOS 5.0 10 — 120 240
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD > VCC 5.0 15 — 120 240
10 15 — 70 140
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
CMOS – CMOS
VCC > VDD
10
15
15
5.0
5.0
10
—
—
—
185
185
175
370
370
350
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Propagation Delay, Low to High
ÎÎÎ
ÎÎÎ
tPLH TTL – CMOS
VDD > VCC
5.0
5.0
10
15
—
—
170
160
340
320
ns
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
CMOS – CMOS 5.0 10 — 170 340
VDD > VCC 5.0 15 — 170 340
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
CMOS – CMOS
10
10
15
5.0
—
—
100
275
200
550
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VCC > VDD 15 5.0 — 275 550
15 10 — 145 290
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Rise and Fall Time tTLH, tTHL ALL — 5.0 — 100 200 ns
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
— 10 — 50 100
— 15 — 40 80
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244
MC14504B
7 7
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)

6 6
VCC = 10 V
5 5
4 4
3 VCC = 5 V 3
2 2 VCC = 5 V
1 1
0 0
0 5 10 15 20 0 5 10 15 20
VDD, SUPPLY VOLTAGE (Vdc) VDD, SUPPLY VOLTAGE (Vdc)
Figure 1. Input Switchpoint CMOS to CMOS Mode Figure 2. Input Switchpoint TTL to CMOS Mode
20 20
ÉÉÉÉÉÉÉÉÉ ÉÉ
15 15
VDD, SUPPLY VOLTAGE (Vdc)
VDD, SUPPLY VOLTAGE (Vdc)

10 10
ÉÉÉÉÉÉÉÉÉ
5 5
0 0
0 5 10 15 20 0 5 10 15 20
VCC, SUPPLY VOLTAGE (Vdc) VCC, SUPPLY VOLTAGE (Vdc)
Figure 3. Operating Boundary CMOS to CMOS Mode Figure 4. Operating Boundary TTL to CMOS Mode
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MC14511B
BCD-To-Seven Segment
Latch/Decoder/Driver
The MC14511B BCD–to–seven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure.
The circuit provides the functions of a 4–bit storage latch, an 8421 http://onsemi.com
BCD–to–seven segment decoder, and an output drive capability. Lamp
test (LT), blanking (BI), and latch enable (LE) inputs are used to test the MARKING
display, to turn–off or pulse modulate the brightness of the display, and DIAGRAMS
16
to store a BCD code, respectively. It can be used with seven–segment PDIP–16
light–emitting diodes (LED), incandescent, fluorescent, gas discharge, P SUFFIX MC14511BCP
AWLYYWW
or liquid crystal readouts either directly or indirectly. CASE 648
Applications include instrument (e.g., counter, DVM, etc.) display 1
driver, computer/calculator display driver, cockpit display driver, and 16
various clock, watch, and timer uses. SOIC–16
14511B
• Low Logic Circuit Power Dissipation D SUFFIX
CASE 751B
AWLYWW
• High–Current Sourcing Outputs (Up to 25 mA) 1
• Latch Storage of Code 16
• Blanking Input
• Lamp Test Provision SOIC–16 14511B
•
DW SUFFIX
Readout Blanking on all Illegal Input Combinations CASE 751G
• Lamp Intensity Modulation Capability AWLYYWW
• Time Share (Multiplexing) Facility 1

• Supply Voltage Range = 3.0 V to 18 V 16
• Capable of Driving Two Low–power TTL Loads, One Low–power SOEIAJ–16
Schottky TTL Load or Two HTL Loads Over the Rated Temperature F SUFFIX MC14511B
CASE 966 AWLYWW
Range
• Chip Complexity: 216 FETs or 54 Equivalent Gates 1
• Triple Diode Protection on all Inputs A = Assembly Location
WL or L = Wafer Lot
MAXIMUM RATINGS (Voltages Referenced to VSS) (2.) YY or Y = Year
Symbol Parameter Value Unit WW or W = Work Week

Vin Input Voltage Range, All Inputs – 0.5 to VDD + 0.5 V ORDERING INFORMATION
I DC Current Drain per Input Pin 10 mA Device Package Shipping
per Package (3.)
TA Operating Temperature Range – 55 to +125 °C MC14511BD SOIC–16 48/Rail
Tstg Storage Temperature Range – 65 to +150 °C MC14511BDW SOIC–16 47/Rail
IOHmax Maximum Output Drive Current 25 mA MC14511BDWR2 SOIC–16 1000/Tape & Reel
(Source) per Output
POHmax Maximum Continuous Output 50 mA
Power (Source) per Output (4.) MC14511BFEL SOEIAJ–16 See Note 1.
2. Maximum Ratings are those values beyond which damage to the device 1. For ordering information on the EIAJ version of
may occur. the SOIC packages, please contact your local
3. Temperature Derating: ON Semiconductor representative.
4. POHmax = IOH (VDD – VOH)

March, 2000 – Rev. 3 MC14511B/D
MC14511B
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. A
destructive high current mode may occur if Vin and Vout are not constrained to the range VSS (Vin or Vout) VDD. v v
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to VSS and are at a
logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
PIN ASSIGNMENT
B 1 16 VDD
C 2 15 f
LT 3 14 g a
f g b
BI 4 13 a
e c
LE 5 12 b
d
D 6 11 c
A 7 10 d
VSS 8 9 e
DISPLAY
0 1 2 3 4 5 6 7 8 9
TRUTH TABLE
Inputs Outputs
LE BI LT D C B A a b c d e f g Display
X X 0 X X X X 1 1 1 1 1 1 1 8
X 0 1 X X X X 0 0 0 0 0 0 0 Blank
0 1 1 0 0 0 0 1 1 1 1 1 1 0 0
0 1 1 0 0 0 1 0 1 1 0 0 0 0 1
0 1 1 0 0 1 1 1 1 1 1 0 0 1 2
0 1 1 0 0 1 1 1 1 1 1 0 0 1 3
0 1 1 0 1 0 0 0 1 1 0 0 1 1 4
0 1 1 0 1 0 1 1 0 1 1 0 1 1 5
0 1 1 0 1 1 0 0 0 1 1 1 1 1 6
0 1 1 0 1 1 1 1 1 1 0 0 0 0 7
0 1 1 1 0 0 0 1 1 1 1 1 1 1 8
0 1 1 1 0 0 1 1 1 1 0 0 1 1 9
0 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 0 1 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 1 0 0 0 0 0 0 0 Blank
1 1 1 X X X X * *
X = Don’t Care
* Depends upon the BCD code previously applied when LE = 0
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MC14511B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (5.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.1 — 4.1 4.57 — 4.1 — Vdc
Vin = 0 or VDD 10 9.1 — 9.1 9.58 — 9.1 —
15 14.1 — 14.1 14.59 — 14.1 —
Input Voltage # “0” Level VIL Vdc
(VO = 3.8 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 8.8 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.8 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 3.8 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 8.8 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.8 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Voltage VOH Vdc
(IOH = 0 mA) Source 5.0 4.1 — 4.1 4.57 — 4.1 —
(IOH = 5.0 mA) — — — 4.24 — — —
(IOH = 10 mA) 3.9 — 3.9 4.12 — 3.5 —
(IOH = 15 mA) — — — 3.94 — — —
(IOH = 20 mA) 3.4 — 3.4 3.70 — 3.0 —
(IOH = 25 mA) — — — 3.54 — — —
(IOH = 0 mA) 10 9.1 — 9.1 9.58 — 9.1 — Vdc
(IOH = 5.0 mA) — — — 9.26 — — —
(IOH = 10 mA) 9.0 — 9.0 9.17 — 8.6 —
(IOH = 15 mA) — — — 9.04 — — —
(IOH = 20 mA) 8.6 — 8.6 8.90 — 8.2 —
(IOH = 25 mA) — — — 8.70 — — —
(IOH = 0 mA) 15 14.1 — 14.1 14.59 — 14.1 — Vdc
(IOH = 5.0 mA) — — — 14.27 — — —
(IOH = 10 mA) 14 — 14 14.18 — 13.6 —
(IOH = 15 mA) — — — 14.07 — — —
(IOH = 20 mA) 13.6 — 13.6 13.95 — 13.2 —
(IOH = 25 mA) — — — 13.70 — — —
Output Drive Current IOL mAdc
(VOL = 0.4 V) Sink 5.0 0.64 — 0.51 0.88 — 0.36 —
(VOL = 0.5 V) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 V) 15 4.2 — 3.4 8.8 — 2.4 —
(Per Package) Vin = 0 or VDD, 10 — 10 — 0.010 10 — 300
Iout = 0 µA 15 — 20 — 0.015 20 — 600
buffers switching)
Noise Margin for both “1” and “0” level =
1.0 Vdc min @ VDD = 5.0 Vdc
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
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MC14511B
VDD
Vdc Min Typ Max Unit
tTLH = (0.40 ns/pF) CL + 20 ns 5.0 — 40 80
tTLH = (0.25 ns/pF) CL + 17.5 ns 10 — 30 60
tTLH = (0.20 ns/pF) CL + 15 ns 15 — 25 50
tTHL = (1.5 ns/pF) CL + 50 ns 5.0 — 125 250
tTHL = (0.75 ns/pF) CL + 37.5 ns 10 — 75 150
tTHL = (0.55 ns/pF) CL + 37.5 ns 15 — 65 130
Data Propagation Delay Time tPLH ns
tPLH = (0.40 ns/pF) CL + 620 ns 5.0 — 640 1280
tPLH = (0.25 ns/pF) CL + 237.5 ns 10 — 250 500
tPLH = (0.20 ns/pF) CL + 165 ns 15 — 175 350
tPHL = (1.3 ns/pF) CL + 655 ns tPHL 5.0 — 720 1440
tPHL = (0.60 ns/pF) CL + 260 ns 10 — 290 580
tPHL = (0.35 ns/pF) CL + 182.5 ns 15 — 200 400
Blank Propagation Delay Time tPLH ns

tPLH = (0.30 ns/pF) CL + 585 ns 5.0 — 600 750
tPLH = (0.25 ns/pF) CL + 187.5 ns I0 — 200 300
tPLH = (0.15 ns/pF) CL + 142.5 ns 15 — 150 220
tPHL = (0.85 ns/pF) CL + 442.5 ns tPHL 5.0 — 485 970

tPHL = (0.45 ns/pF) CL + 177.5 ns 10 — 200 400
tPHL = (0.35 ns/pF) CL + 142.5 ns 15 — 160 320
Lamp Test Propagation Delay Time tPLH ns

tPLH = (0.45 ns/pF) CL + 290.5 ns 5.0 — 313 625
tPLH = (0.25 ns/pF) CL + 112.5 ns 10 — 125 250
tPLH = (0.20 ns/pF) CL + 80 ns 15 — 90 180
tPHL = (1.3 ns/pF) CL + 248 ns tPHL 5.0 — 313 625

tPHL = (0.45 ns/pF) CL + 102.5 ns 10 — 125 250
tPHL = (0.35 ns/pF) CL + 72.5 ns 15 — 90 180
Setup Time tsu 5.0 100 — — ns

10 40 — —
15 30 — —
Hold Time th 5.0 60 — — ns
10 40 — —
15 30 — —
Latch Enable Pulse Width tWL 5.0 520 260 — ns
10 220 110 —
15 130 65 —
8. The formulas given are for the typical characteristics only.
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249
MC14511B
Input LE low, and Inputs D, BI and LT high.

f in respect to a system clock.
All outputs connected to respective CL loads.
20 ns 20 ns
VDD
90%
A, B, AND C 50%
1 10% VSS
2f
50% DUTY CYCLE
VOH
50%
ANY OUTPUT
VOL
Figure 1. Dynamic Power Dissipation Signal Waveforms
20 ns 20 ns
90% VDD
INPUT C 50%
10%
VSS
tPLH tPHL
VOH
90%
OUTPUT g 50%
10% VOL
tTLH tTHL
(a) Inputs D and LE low, and Inputs A, B, BI and LT high.
20 ns
VDD
90%
50%
LE 10%
VSS
th
tsu
VDD
INPUT C 50%
VSS
VOH
OUTPUT g
VOL
(b) Input D low, Inputs A, B, BI and LT high.
20 ns
20 ns
VDD
90%
LE 50%
10% VSS
tWL
(c) Data DCBA strobed into latches.
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250
MC14511B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LED) READOUT

VDD VDD
COMMON
ANODE LED
COMMON ≈ 1.7 V
CATHODE LED
≈ 1.7 V
VSS
VSS
INCANDESCENT READOUT FLUORESCENT READOUT

VDD VDD VDD
** DIRECT
(LOW BRIGHTNESS)
FILAMENT
SUPPLY
VSS
VSS VSS OR APPROPRIATE
VOLTAGE BELOW VSS.
(CAUTION: Maximum working voltage = 18.0 V)
GAS DISCHARGE READOUT LIQUID CRYSTAL (LCD) READOUT

EXCITATION
APPROPRIATE (SQUARE WAVE,
VDD VOLTAGE VDD VSS TO VDD)
1/4 OF MC14070B
VSS VSS
** A filament pre–warm resistor is recommended to reduce filament Direct dc drive of LCD’s not recommended for life of
thermal shock and increase the effective cold resistance of the LCD readouts.
filament.
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251
MC14511B
LOGIC DIAGRAM
BI 4
13 a
A 7
12 b
11 c
B 1
10 d
9 e
15 f
C 2
14 g
LT 3
D 6
VDD = PIN 16
LE 5 VSS = PIN 8
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252
MC14512B
8-Channel Data Selector

The MC14512B is an 8–channel data selector constructed with
single monolithic structure. This data selector finds primary
application in signal multiplexing functions. It may also be used for
data routing, digital signal switching, signal gating, and number
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sequence generation.
• Single Supply Operation MARKING
DIAGRAMS
• 3–State Output (Logic “1”, Logic “0”, High Impedance)
16
AWLYYWW
1
16
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) SOIC–16
14512B
D SUFFIX AWLYWW
CASE 751B
(DC or Transient) per Pin F SUFFIX MC14512B
CASE 966 AWLYWW
per Package (Note 3.) 1
WL or L = Wafer Lot
TL Lead Temperature 260 °C YY or Y = Year
(8–Second Soldering) WW or W = Work Week
may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C ORDERING INFORMATION
This device contains protection circuitry to guard against damage due to high Device Package Shipping
applications of any voltage higher than maximum rated voltages to this MC14512BCP PDIP–16 2000/Box
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14512BDR2 SOIC–16 2500/Tape & Reel
MC14512BFL1 SOEIAJ–16 See Note 1.


March, 2000 – Rev. 3 MC14512B/D
MC14512B
TRUTH TABLE
C B A Inhibit Disable Z
0 0 0 0 0 X0
0 0 1 0 0 X1
0 1 0 0 0 X2
0 1 1 0 0 X3
1 0 0 0 0 X4
1 0 1 0 0 X5
1 1 0 0 0 X6
1 1 1 0 0 X7
X X X 1 0 0
X X X X 1 High
Impedance
X = Don’t Care
PIN ASSIGNMENT
X0 1 16 VDD
X1 2 15 DIS
X2 3 14 Z
X3 4 13 C
X4 5 12 B
X5 6 11 A
X6 7 10 INH
VSS 8 9 X7
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254
MC14512B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
buffers switching)
Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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MC14512B
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C, See Figure 1)

All Types
Characteristic Symbol VDD Typ (8.) Max Unit
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 40 80
Propagation Delay Time (Figure 2) tPLH ns
Inhibit, Control, or Data to Z 5.0 330 650
10 125 250
15 85 170
Propagation Delay Time (Figure 2) tPHL ns
Inhibit, Control, or Data to Z 5.0 330 650
10 125 250
15 85 170
3–State Output Delay Times (Figure 3) tPHZ, tPLZ, 5.0 60 150 ns
“1” or “0” to High Z, and tPZH, tPZL 10 35 100
High Z to “1” or “0” 15 30 75
ID VDD
DISABLE
INHIBIT Z
A CL
B
C
X0
X1
PULSE X2
Vin 50% GENERATOR
50% X3
DUTY X4
CYCLE X5
X6
X7
VSS
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256
MC14512B
VDD
20 ns 20 ns
90% VDD
DISABLE DATA 50%
INHIBIT Z 10% VSS
A tPLH tPHL
CL 90% VOH
B 50%
C Z 10%
VOL
X0 tTLH tTHL
PULSE X1
GENERATOR TEST CONDITIONS:
X2 INHIBIT = VSS
X3 A, B, C = VSS
X4
X5 20 ns 20 ns
X6 INHIBIT, VDD
90%
X7 A, B, OR C 50%
10% VSS
tPHL tPLH
VSS Parameter Test Conditions 90% VOH
50%
Inhibit to Z A, B, C = VSS, XO = VDD Z 10% VOL
A, B, C to Z Inh = VSS, XO = VDD tTHL tTLH
Figure 2. AC Test Circuit and Waveforms
VDD
PULSE 20 ns
VDD 20 ns
GENERATOR VDD
DISABLE 90%
VDD 50%
INHIBIT Z DISABLE 10%
CL VSS
A INPUT
B 1k S1 tPZL
S3 tPLZ
C VOH
90%
X0 S2 OUTPUT 10% VOL ≈ 2.5 V @ VDD = 5 V,
S4 X1 10 V, AND 15 V
tPHZ tPZH
X2 ≈ 2 V @ VDD = 5 V
X3 VSS OUTPUT
90%
VOH ≈ 6 V @ VDD = 10 V
VSS X4 10% ≈ 10 V @ VDD = 15 V
VOL
X5
X6 Switch Positions for 3–State Test
X7 Test S1 S2 S3 S4
tPHZ Open Closed Closed Open
VSS
tPLZ Closed Open Open Closed
tPZL Closed Open Open Closed
tPZH Open Closed Closed Open
Figure 3. 3–State AC Test Circuit and Waveform
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MC14512B
LOGIC DIAGRAM
13
C
12
B 15
11 DISABLE
A
1 10 DATA
X0 SELECTED
BUS
INHIBIT DEVICE
2 VDD IOD
X1
MC14512B
3 IL
X2
14 LOAD
Z ITL
4
X3 MC14512B
5
X4
ITL
6 MC14512B
X5
7 VSS
X6
9
X7 1 1
OUT
IN IN OUT
2 2
TRANSMISSION
GATE
3–STATE MODE OF OPERATION
Output terminals of several MC14512B 8–Bit Data (including fanout to other device inputs), and can be
Selectors can be connected to a single date bus as shown. calculated by:
One MC14512B is selected by the 3–state control, and the IOD – IL
remaining devices are disabled into a high–impedance “off” N= +1
ITL
state. The number of 8–bit data selectors, N, that may be
connected to a bus line is determined from the output drive N must be calculated for both high and low logic state of the
current, IOD, 3–state or disable output leakage current, ITL, bus line.
and the load current, IL, required to drive the bus line
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258
MC14513B
BCD-To-Seven Segment
Latch/Decoder/Driver
CMOS MSI
(Low–Power Complementary MOS)
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constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure.
The circuit provides the functions of a 4–bit storage latch, an 8421
BCD–to–seven segment decoder, and has output drive capability. Lamp
test (LT), blanking (BI), and latch enable (LE) inputs are used to test the
display, to turn–off or pulse modulate the brightness of the display, and
to store a BCD code, respectively. The Ripple Blanking Input (RBI) and
Ripple Blanking Output (RBO) can be used to suppress either leading
or trailing zeroes. It can be used with seven–segment light emitting MARKING
diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal DIAGRAMS
readouts either directly or indirectly. 18
PDIP–18
Applications include instrument (e.g., counter, DVM, etc.) display MC14513BCP
P SUFFIX
driver, computer/calculator display driver, cockpit display driver, and AWLYYWW
CASE 707
various clock, watch, and timer uses. 1
• Low Logic Circuit Power Dissipation
• High–current Sourcing Outputs (Up to 25 mA) A = Assembly Location
WL or L = Wafer Lot
• Latch Storage of Binary Input YY or Y = Year
• Blanking Input WW or W = Work Week
• Lamp Test Provision
• Readout Blanking on all Illegal Input Combinations
• Lamp Intensity Modulation Capability
• Time Share (Multiplexing) Capability Device Package Shipping
• Adds Ripple Blanking In, Ripple Blanking Out to MC14511B MC14513BCP PDIP–18 20/Rail
• Supply Voltage Range = 3.0 V to 18 V
This device contains protection circuitry to protect
• Capable of Driving Two Low–Power TTL Loads, One Low–power the inputs against damage due to high static voltages
Schottky TTL Load to Two HTL Loads Over the Rated Temperature or electric fields. However, it is advised that normal
Range. precautions be taken to avoid application of any volt-
age higher than maximum rated voltages to this high–
MAXIMUM RATINGS (Voltages Referenced to VSS) (1.) impedance circuit. A destructive high current mode
may occur if Vin and Vout are not constrained to the
v v
range VSS (Vin or Vout) VDD.
VDD DC Supply Voltage Range – 0.5 to +18.0 V Due to the sourcing capability of this circuit, dam-
Vin Input Voltage Range, All Inputs – 0.5 to VDD + 0.5 V age can occur to the device if VDD is applied, and the
outputs are shorted to VSS and are at a logical 1 (See
I DC Current Drain per Input Pin 10 mA Maximum Ratings).
PD Power Dissipation, 500 mW Unused inputs must always be tied to an appropri-
per Package (2.) ate logic voltage level (e.g., either VSS or VDD).

1. Maximum Ratings are those values beyond which
IOHmax Maximum Continuous Output 25 mA damage to the device may occur.
Drive Current (Source) per Output 2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C
POHmax Maximum Continuous Output 50 mW From 65_C To 125_C
Power (Source) per Output (3.) 3. POHmax = IOH (VDD – VOH)

March, 2000 – Rev. 3 MC14513B/D
MC14513B
PIN ASSIGNMENT
B 1 18 VDD
C 2 17 f
LT 3 16 g
a
BI 4 15 a f g b
LE 5 14 b e c
D 6 13 c d
A 7 12 d
RBI 8 11 e
VSS 9 10 RBO
DISPLAY
0 1 2 3 4 5 6 7 8 9
TRUTH TABLE
Inputs Outputs
RBI LE BI LT D C B A RBO a b c d e f g Display
X X X 0 X X X X + 1 1 1 1 1 1 1 8
X X 0 1 X X X X + 0 0 0 0 0 0 0 Blank
1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 Blank
0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0
X 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 1
X 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 2
X 0 1 1 0 0 1 1 0 1 1 1 1 0 0 1 3
X 0 1 1 0 1 0 0 0 0 1 1 0 0 1 1 4
X 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 5
X 0 1 1 0 1 1 0 0 1 0 1 1 1 1 1 6
X 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 7
X 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 8
X 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 9
X 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank
X 1 1 1 X X X X † * *
X = Don’t Care
†RBO = RBI (D C B A), indicated by other rows of table
*Depends upon the BCD code previously applied when LE = 0
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2
MC14513B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Output Voltage — Segment Outputs VOL Vdc
“0” Level 5.0 — 0.05 — 0 0.05 — 0.05
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.1 — 4.1 5.0 — 4.1 — Vdc
Vin = 0 or VDD 10 9.1 — 9.1 10 — 9.1 —
15 14.1 — 14.1 15 — 14.1 —
Output Voltage — RBO Output VOL Vdc
“0” Level 5.0 — 0.05 — 0 0.05 — 0.05
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage (4.) “0” Level VIL Vdc
(VO = 3.8 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 8.8 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.8 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 1.0 or 8.8 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.8 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Voltage — Segments VOH Vdc

(IOH = 0 mA) Source 5.0 4.1 — 4.1 4.57 — 4.1 —
(IOH = 5.0 mA) — — — 4.24 — — —
(IOH = 10 mA) 3.9 — 3.9 4.12 — 3.5 —
(IOH = 15 mA) — — — 3.94 — — —
(IOH = 20 mA) 3.4 — 3.4 3.70 — 3.0 —
(IOH = 25 mA) — — — 3.54 — — —
(IOH = 0 mA) 10 9.1 — 9.1 9.58 — 9.1 — Vdc
(IOH = 5.0 mA) — — — 9.26 — — —
(IOH = 10 mA) 9.0 — 9.0 9.17 — 8.6 —
(IOH = 15 mA) — — — 9.04 — — —
(IOH = 20 mA) 8.6 — 8.6 8.90 — 8.2 —
(IOH = 25 mA) — — — 8.75 — — —
(IOH = 0 mA) 15 14.1 — 14.1 14.59 — 14.1 — Vdc
(IOH = 5.0 mA) — — — 14.27 — — —
(IOH = 10 mA) 14 — 14 14.18 — 13.6 —
(IOH = 15 mA) — — — 14.07 — — —
(IOH = 20 mA) 13.6 — 13.6 13.95 — 13.2 —
(IOH = 25 mA) — — — 13.80 — — —
(continued)
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MC14513B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to VSS)
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Output Drive Current — RBO Output IOH mAdc
(VOH = 2.5 V) Source 5.0 – 0.40 — – 0.32 – 0.64 — – 0.22 —
(VOH = 9.5 V) 10 – 0.21 — – 0.17 – 0.34 — – 0.12 —
(VOH = 13.5 V) 15 – 0.81 — – 0.66 – 1.30 — – 0.46 —
(VOL = 0.4 V) Sink IOL 5.0 0.18 — 0.15 0.29 — 0.10 — mAdc
(VOL = 0.5 V) 10 0.47 — 0.38 0.75 — 0.26 —
(VOL = 1.5 V) 15 1.80 — 1.50 2.90 — 1.0 —
Output Drive Current — Segments IOL mAdc

(VOL = 0.4 V) Sink 5.0 0.64 — 0.51 0.88 — 0.36 —
(VOL = 0.5 V) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 V) 15 4.2 — 3.4 8.8 — 2.4 —
Iout = 0 µA 15 — 20 — 0.015 20 — 600
buffers switching)
Noise Margin for both “1” and “0” level =
1.0 Vdc min @ VDD = 5.0 Vdc
where: IT is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
Input LE and RBI low, and Inputs D, BI and LT high.

f in respect to a system clock.
20 ns 20 ns
VDD
90%
A, B, AND C 50%
1 10% VSS
2f
50% DUTY CYCLE
VOH
ANY OUTPUT 50%
VOL
Figure 1. Dynamic Power Dissipation Signal Waveforms
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262
MC14513B
VDD
Vdc Min
All Types
Typ Max Unit
Output Rise Time — Segment Outputs tTLH ns
5.0 — 40 80
10 — 30 60
15 — 25 50
Output Rise Time — RBO Output tTLH ns
5.0 — 480 960
10 — 240 480
15 — 190 380
Output Fall Time — Segment Outputs (7.) tTHL ns
tTHL = (1.5 ns/pF) CL + 50 ns 5.0 — 125 250
tTHL = (0.75 ns/pF) CL + 37.5 ns 10 — 75 150
tTHL = (0.55 ns/pF) CL + 37.5 ns 15 — 65 130
Output Fall Time — RBO Outputs tTHL ns
tTHL = (3.25 ns/pF) CL + 107.5 ns 5.0 — 270 540
tTHL = (1.35 ns/pF) CL + 67.5 ns 10 — 135 270
tTHL = (0.95 ns/pF) CL + 62.5 ns 15 — 110 220
Propagation Delay Time — A, B, C, D Inputs (7.) tPLH ns
tPLH = (0.40 ns/pF) CL + 620 ns 5.0 — 640 1280
tPLH = (0.25 ns/pF) CL + 237.5 ns 10 — 250 500
tPLH = (0.20 ns/pF) CL + 165 ns 15 — 175 350
tPHL = (0.60 ns/pF) CL + 260 ns 10 — 290 580
tPHL = (0.35 ns/pF) CL + 182.5 ns 15 — 200 400
Propagation Delay Time — RBI and BI Inputs (7.) tPLH ns

tPLH = (1.05 ns/pF) CL + 547.5 ns 5.0 — 600 750
tPLH = (0.45 ns/pF) CL + 177.5 ns 10 — 200 300
tPLH = (0.30 ns/pF) CL + 135 ns 15 — 150 220
tPHL = (0.85 ns/pF) CL + 442.5 ns tPHL 5.0 — 485 970 ns

tPHL = (0.45 ns/pF) CL + 177.5 ns 10 — 200 400
tPHL = (0.35 ns/pF) CL + 142.5 ns 15 — 160 320
Propagation Delay Time — LT Input (7.) tPLH ns

tPLH = (0.45 ns/pF) CL + 290.5 ns 5.0 — 313 625
tPLH = (0.25 ns/pF) CL + 112.5 ns 10 — 125 250
tPLH = (0.20 ns/pF) CL + 80 ns 15 — 90 180

tPHL = (0.45 ns/pF) CL + 102.5 ns 10 — 125 250
tPHL = (0.35 ns/pF) CL + 72.5 ns 15 — 90 180
Setup Time tsu 5.0 100 — — ns

10 40 — —
15 30 — —
Hold Time th 5.0 60 — — ns
10 40 — —
15 30 — —
Latch Enable Pulse Width tWL(LE) 5.0 520 260 — ns
10 220 110 —
15 130 65 —
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263
MC14513B
20 ns 20 ns
90% VDD
INPUT C 50%
10% VSS
tPLH tPHL
VOH
OUTPUT g
VOL
tTLH tTHL
a. Data Propagation Delay: Inputs RBI, D and LE low, and Inputs A, B, BI and LT high.
20 ns 20 ns
90% VDD
INPUT C 50%
10% VSS
tPLH tPHL
VOH
90%
OUTPUT RBO 50%
10% VOL
tTLH tTHL
b. Inputs A, B, D and LE low, and Inputs RBI, BI and LT high.
20 ns
VDD
90%
LE 50%
10% VSS
th
tsu
VDD
INPUT C 50%
VSS
VOH
OUTPUT g
VOL
c. Setup and Hold Times: Input RBI and D low, Inputs A, B, BI and LT high.
20 ns
20 ns
VDD
90%
50%
10%
LE VSS
tWL(LE)
d. Pulse Width: Data DCBA strobed into latches.
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MC14513B
LIGHT EMITTING DIODE (LED) READOUT

VDD VDD
COMMON
COMMON ANODE LED
CATHODE LED ≈ 1.7 V
≈ 1.7 V
VSS
VSS
INCANDESCENT READOUT FLUORESCENT READOUT

VDD VDD VDD
**
DIRECT
(LOW BRIGHTNESS)
FILAMENT
(SUPPLY)
VSS VSS VSS OR APPROPRIATE
VOLTAGE BELOW VSS.
GAS DISCHARGE READOUT LIQUID CRYSTAL (LC) READOUT

EXCITATION
APPROPRIATE (SQUARE WAVE,
VDD VOLTAGE VDD VSS TO VDD)
1/4 OF MC14070B
VSS VSS
** A filament pre–warm resistor is recommended to reduce
filament thermal shock and increase the effective cold Direct dc drive of LC’s not recommended for life of LC readouts.
resistance of the filament.
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265
MC14513B
LOGIC DIAGRAM
BI 4
15 a
A 7
14 b
13 c
B 1 12 d
11 e
17 f
C 2
16 g
LT 30
RBI 8 10 RBO
D 6
LE 5
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266
MC14513B
TYPICAL APPLICATIONS FOR RIPPLE BLANKING
LEADING EDGE ZERO SUPPRESSION
DISPLAYS
a–– – –– g a–– – –– g a–– – –– g a–– – –– g a–– – –– g a–– – – –g

CONNECT TO
RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO
VDD (1) D C B A 1 D C B A 1 D C B A 0 D C B A 0 D C B A 0 D C B A 0
MC14513B MC14513B MC14513B MC14513B MC14513B MC14513B

INPUT 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1
CODE (0) (0) (5) (0) (1) (3)
TRAILING EDGE ZERO SUPPRESSION
DISPLAYS
a–– – –– g a –– – –– g a –– – ––g a–– – –– g a –– – ––g a –– – ––g CONNECT TO

0
RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI
D C B A 0 D C B A 0 D C B A 0 D C B A 1 D C B A 1 D C B A VDD (1)
MC14513B MC14513B MC14513B MC14513B MC14513B MC14513B

0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0
(5) (0) (1) (3) (0) (0) INPUT CODE
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MC14514B, MC14515B
4-Bit Transparent
Latch/4-to-16 Line Decoder
The MC14514B and MC14515B are two output options of a 4 to 16
line decoder with latched inputs. The MC14514B (output active high
option) presents a logical “1” at the selected output, whereas the
MC14515B (output active low option) presents a logical “0” at the http://onsemi.com
selected output. The latches are R–S type flip–flops which hold the
last input data presented prior to the strobe transition from “1” to “0”.
These high and low options of a 4–bit latch/4 to 16 line decoder are
constructed with N–channel and P–channel enhancement mode
devices in a single monolithic structure. The latches are R–S type MARKING
flip–flops and data is admitted upon a signal incident at the strobe 24 DIAGRAMS
input, decoded, and presented at the output.
These complementary circuits find primary use in decoding PDIP–24
MC145XXBCP
applications where low power dissipation and/or high noise immunity P SUFFIX
AWLYYWW
CASE 709
is desired.
• Capable of Driving Two Low–power TTL Loads or One Low–power
Symbol Parameter Value Unit SOIC–24 145XXB

VDD DC Supply Voltage Range – 0.5 to +18.0 V DW SUFFIX AWLYYWW
CASE 751E
(DC or Transient) 1

(DC or Transient) per Pin XX = Specific Device Code
WW or W = Work Week
may occur. MC14514BCP PDIP–24 15/Rail
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14514BDW SOIC–24 30/Rail
applications of any voltage higher than maximum rated voltages to this MC14515BCP PDIP–24 15/Rail
MC14515BDW SOIC–24 30/Rail
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14515BDWR2 SOIC–24 1000/Tape & Reel

March, 2000 – Rev. 3 MC14514B/D
MC14514B, MC14515B
PIN ASSIGNMENT
ST 1 24 VDD
D1 2 23 INH
D2 3 22 D4
S7 4 21 D3
S6 5 20 S10
S5 6 19 S11
S4 7 18 S8
S3 8 17 S9
S1 9 16 S14
S2 10 15 S15
S0 11 14 S12
VSS 12 13 S13
DECODE TRUTH TABLE (Strobe = 1)*

Data Inputs Selected Output
MC14514 = Logic “1”
Inhibit D C B A MC14515 = Logic “0”
0 0 0 0 0 S0
0 0 0 0 1 S1
0 0 0 1 0 S2
0 0 0 1 1 S3
0 0 1 0 0 S4
0 0 1 0 1 S5
0 0 1 1 0 S6
0 0 1 1 1 S7
0 1 0 0 0 S8
0 1 0 0 1 S9
0 1 0 1 0 S10
0 1 0 1 1 S11
0 1 1 0 0 S12
0 1 1 0 1 S13
0 1 1 1 0 S14
0 1 1 1 1 S15
1 X X X X All Outputs = 0, MC14514
All Outputs = 1, MC14515
X = Don’t Care
*Strobe = 0, Data is latched
BLOCK DIAGRAM 11
S0 ABCD
9
S1 ABCD
VDD = PIN 24 S2 10 ABCD
VSS = PIN 12 S3 8 ABCD
S4 7 ABCD
2 A 6
DATA 1 S5 ABCD
5
S6 ABCD
3 B 4
DATA 2 S7 ABCD
TRANSPARENT 4 TO 16 18
21 LATCH C DECODER S8 ABCD
DATA 3 17
S9 ABCD
22 D 20
DATA 4 S10 ABCD
19
S11 ABCD
S12 14 ABCD
1
STROBE 13
S13 ABCD
S14 16 ABCD
15
S15 ABCD
23
INHIBIT
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MC14514B, MC14515B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current (4.) (5.) ITL 5.0 IT = (1.35 µA/kHz) f + IDD µAdc
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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270
MC14514B, MC14515B
Characteristic Symbol VDD Min

All Types
Typ (7.) Max Unit
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 180
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time; Data, Strobe to S tPLH, ns
Inhibit Propagation Delay Times tPLH, ns
Setup Time tsu ns
Data to Strobe 5.0 250 125 —
10 100 50 —
15 75 38 —
Hold Time th 5.0 – 20 – 100 — ns
Strobe to Data 10 0 – 40 —
15 10 – 30 —
Strobe Pulse Width tWH ns
5.0 350 175 —
10 100 50 —
15 75 38 —
VDD
VDS
S0
STROBE S1
S2 For MC14515B
S3 1. For P–channel: Inhibit = VDD
INHIBIT S4 2. For N–channel: Inhibit = VSS
For MC14514B S5 2. and D1–D4 constitute binary
1. For P–channel: Inhibit = VSS D1 S6 2. code for “output under test.”
1. and D1–D4 constitute S7
1. binary code for “output S8
D2 S9
1. under test.” ID
S10
2. For N–channel: Inhibit = VDD D3 S11
S12
S13 EXTERNAL
D4 S14 POWER SUPPLY
S15
VSS
Figure 1. Drain Characteristics Test Circuit
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271
MC14514B, MC14515B
VDD
0.01 µF
ID
500 CERAMIC
µF
24 VDD
20 ns 20 ns
PULSE VDD
D1 S0 90%
GENERATOR
D2 CL Vin
D3 10% VSS
D4
STROBE
INHIBIT S15
12 CL
VSS
Figure 2. Dynamic Power Dissipation Test Circuit and Waveform
VDD
STROBE OUTPUT S0
S0
S1 OUTPUT S1 tTLH tTHL
INHIBIT 20 ns
CL CL
VDD
90%
D1 INPUT 50%
PROGRAMMABLE 10%
PULSE VSS
GENERATOR tPLH tPHL
D2
VDD
OUTPUT
90%
50%
D3 10% VSS
S15 OUTPUT S15

D4 tTLH tTHL
VSS CL
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LOGIC DIAGRAM
AB CD
11 S0
AB CD
9 S1
AB CD
10 S2
AB CD
DATA 1 2 A 8 S3
S Q
AB CD
7 S4
R Q AB CD
6 S5
DATA 2 3 B
S Q AB CD
5 S6
AB CD
4 S7
R Q
273
AB CD
DATA 3 21 C 18 S8
S Q
AB CD
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17 S9
R Q AB CD
20 S10
MC14514B, MC14515B
DATA 4 22 D AB CD
S Q 19 S11
AB CD
14 S12
R Q
STROBE 1 AB CD
13 S13
AB CD
16 S14
INHIBIT 23
AB CD
15 S15
IN MC14515B ONLY
MC14514B, MC14515B
COMPLEX DATA ROUTING
Two MC14512 eight–channel data selectors are used here times faster then the shift frequency of the input registers,
with the MC14514B four–bit latch/decoder to effect a the most significant bit (MSB) from each register could be
complex data routing system. A total of 16 inputs from data selected for transfer to the data bus. Therefore, all of the
registers are selected and transferred via a 3–state data bus most significant bits from all of the registers can be
to a data distributor for rearrangement and entry into 16 transferred to the data bus before the next most significant
output registers. In this way sequential data can be re–routed bit is presented for transfer by the input registers.
or intermixed according to patterns determined by data Information from the 3–state bus is redistributed by the
select and distribution inputs. MC14514B four–bit latch/decoder. Using the four–bit
Data is placed into the routing scheme via the eight inputs address, D1 thru D4, the information on the inhibit line can
on both MC14512 data selectors. One register is assigned to be transferred to the addressed output line to the desired
each input. The signals on A0, A1, and A2 choose one of output registers, A thru P. This distribution of data bits to the
eight inputs for transfer out to the 3–state data bus. A fourth output registers can be made in many complex patterns. For
signal, labelled Dis, disables one of the MC14512 selectors, example, all of the most significant bits from the input
assuring transfer of data from only one register. registers can be routed into output register A, all of the next
In addition to a choice of input registers, 1 thru 16, the rate most significant bits into register B, etc. In this way
of transfer of the sequential information can also be varied. horizontal, vertical, or other methods of data slicing can be
That is, if the MC14512 were addressed at a rate that is eight implemented.
DATA ROUTING SYSTEM
INPUT DATA 3–STATE DATA OUTPUT

REGISTERS TRANSFER DATA BUS DISTRIBUTION REGISTERS
DIS
REGISTER 1 D0 Q
D1
D2
D1 D2 D3 D4
MC14512
D3
S0 REGISTER A
D4
STROBE S1
D5
S2
D6
S3
REGISTER 8 D7 S4
A0 A1 A2
S5
S6
MC14514B
DATA S7
SELECT S8
S9
S10
A0 A1 A2
D0 Q S11
REGISTER 9
D1 S12
D2 S13
MC14512
INHIBIT S14
D3
D4 S15 REGISTER P
D5
D6
REGISTER 16 D7
DIS
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274
MC14516B
Binary Up/Down Counter
The MC14516B synchronous up/down binary counter is

constructed with MOS P–channel and N–channel enhancement mode
devices in a monolithic structure.
This counter can be preset by applying the desired value, in binary,
to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset
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Enable (PE) high. The direction of counting is controlled by applying
a high (for up counting) or a low (for down counting) to the
MARKING
UP/DOWN input. The state of the counter changes on the positive
DIAGRAMS
transition of the clock input.
16
Cascading can be accomplished by connecting the Carry Out to the PDIP–16
Carry In of the next stage while clocking each counter in parallel. The P SUFFIX MC14516BCP
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high CASE 648 AWLYYWW
to the reset (R) pin. 1
This CMOS counter finds primary use in up/down and difference
16
counting. Other applications include: (1) Frequency synthesizer
SOIC–16
applications where low power dissipation and/or high noise immunity 14516B
D SUFFIX AWLYWW
is desired, (2) Analog–to–digital and digital–to–analog conversions, CASE 751B
and (3) Magnitude and sign generation. 1
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOEIAJ–16
• Internally Synchronous for High Speed F SUFFIX MC14516B
AWLYWW
• Logic Edge–Clocked Design — Count Occurs on Positive Going CASE 966
Edge of Clock 1
• Single Pin Reset A = Assembly Location
• Asynchronous Preset Enable Operation WL or L = Wafer Lot
YY or Y = Year
• Capable of Driving Two Low–Power TTL Loads or One Low–Power WW or W = Work Week
Schottky Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Device Package Shipping
(DC or Transient) MC14516BDR2 SOIC–16 2500/Tape & Reel
Iin, Iout Input or Output Current ± 10 mA MC14516BF SOEIAJ–16 See Note 1.

per Package (Note 3.) 1. For ordering information on the EIAJ version of
TA Ambient Temperature Range – 55 to +125 °C ON Semiconductor representative.
TL Lead Temperature 260 °C against damage due to high static voltages or electric
(8–Second Soldering) fields. However, precautions must be taken to avoid ap-
may occur. voltages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained to the
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C range VSS v v
(Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused out-
puts must be left open.

March, 2000 – Rev. 3 MC14516B/D
MC14516B
PIN ASSIGNMENT
PE 1 16 VDD
Q3 2 15 C
P3 3 14 Q2
P0 4 13 P2
CARRY IN 5 12 P1
Q0 6 11 Q1
CARRY OUT 7 10 U/D
VSS 8 9 R
BLOCK DIAGRAM
1 PE Q0 6
5 CARRY IN
9 RESET Q1 11
10 UP/DOWN
15 CLOCK Q2 14
4 P0
12 P1 Q3 2
13 P2
CARRY
3 P3 7
OUT
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Preset
Carry In Up/Down Enable Reset Clock Action
1 X 0 0 X No Count
0 1 0 0 Count Up
0 0 0 0 Count Down
X X 1 0 X Preset
X X X 1 X Reset
X = Don’t Care
NOTE: When counting up, the Carry Out signal is normally high and is low only
when Q0 through Q3 are high and Carry In is low. When counting down,
Carry Out is low only when Q0 through Q3 and Carry In are low.
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MC14516B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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277
MC14516B

All Types
Typ (8.) Max Unit
Clock to Q tPHL
Clock to Carry Out tPLH, ns
Carry In to Carry Out tPLH, ns
Preset or Reset to Q tPLH, ns
Preset or Reset to Carry Out tPLH, ns
10 200 100 —
15 160 80 —
10 170 100 —
15 140 75 —
10 — 6.0 3.0
15 — 8.0 4.0
8. Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.
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278
MC14516B
SWITCHING CHARACTERISTICS (9.) (CL = 50 pF, TA = 25_C) (continued)

All Types
Typ (10.) Max Unit
Preset or Reset Removal Time trem 5.0 650 325 — ns
The Preset or Reset signal must be low prior to a 10 230 115
positive–going transition of the clock. 15 180 90 —
Clock Rise and Fall Time tTLH, 5.0 — — 15 µs
tTHL 10 — — 5
15 — — 4
Carry In to Clock 10 120 60 —
15 100 50 —
Clock to Carry In 10 20 – 20 —
15 20 0 —
Up/Down to Clock 10 200 100 —
15 150 75 —
Hold Time th 5.0 – 70 – 160 — ns
Clock to Up/Down 10 – 10 – 60 —
15 0 – 40 —
Setup Time tsu 5.0 – 40 – 120 — ns
Pn to PE 10 – 30 – 70 —
15 – 25 – 50 —
Hold Time th 5.0 480 240 — ns
PE to Pn 10 420 210 —
15 420 210 —
Preset Enable Pulse Width tWH 5.0 200 100 — ns
10 100 50 —
15 80 40 —
10. Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.
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279
MC14516B
VDD
500 pF ID 0.01 µF
CERAMIC
PE Q0
CARRY IN
20 ns 20 ns
R Q1 VDD
UP/DOWN 90%
CL CLOCK 50%
PULSE CLOCK Q2 10% VSS
GENERATOR CL VARIABLE
P0 WIDTH
P1 Q3
CL
P2
CARRY
P3 CL
OUT
CL
LOGIC DIAGRAM
P0 Q0 P1 Q1 P2 Q2 P3 Q3
4 6 12 11 13 14 3 2
RESET 9
PRESET
1
ENABLE
CLOCK 15
P P P P
PE Q PE Q PE Q PE Q
C C C C
CARRY OUT 7
T Q T Q T Q T Q
CARRY IN 5
UP/DOWN 10
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280
MC14516B
TOGGLE FLIP–FLOP FLIP–FLOP FUNCTIONAL TRUTH TABLE

PARALLEL IN Preset
Enable Clock T Qn+1
P
PE Q 1 X X Parallel In
C 0 0 Qn
T Q 0 1 Qn
0 X Qn
X = Don’t Care
tsu trem
1
th fcl
CARRY IN OR VDD
UP/DOWN 50%
VSS
VDD
50%
CLOCK VSS
tw(H) tw(H)
VDD
PRESET ENABLE VSS
tTLH
CARRY OUT ONLY
Q0 OR CARRY OUT VOH
90% 90%
10% 10% VOL
tPHL
tTHL tPLH tPLH
trem
VDD
50%
RESET VSS
tw
Figure 2. Switching Time Waveforms
PIN DESCRIPTIONS
INPUTS CONTROLS
P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) — Data PE, Preset Enable, (Pin 1) — Asynchronously loads data
on these inputs is loaded into the counter when PE is taken on the Preset Inputs. This pin is active high and inhibits the
high. clock when high.
Carry In, (Pin 5) — This active–low input is used when R, Reset, (Pin 9) — Asynchronously resets the Q out–
Cascading stages. Carry In is usually connected to Carry Out puts to a low state. This pin is active high and inhibits the
of the previous stage. While high, Clock is inhibited. clock when high.
Clock, (Pin 15) — Binary data is incremented or Up/Down, (Pin 10) — Controls the direction of count,
decremented, depending on the direction of count, on the high for up count, low for down count.
positive transition of this input.
SUPPLY PINS
OUTPUTS VSS, Negative Supply Voltage, (Pin 8) — This pin is
Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2) — usually connected to ground.
Binary data is present on these outputs with Q0 VDD, Positive Supply Voltage, (Pin 16) — This pin is
corresponding to the least significant bit. connected to a positive supply voltage ranging from 3.0
Carry Out, (Pin 7) — Used when cascading stages, Carry volts to 18.0 volts.
Out is usually connected to Carry In of the next stage. This
synchronous output is active low and may also be used to
indicate terminal count.
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281
MC14516B
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
PRESET
ENABLE
0 = COUNT Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
PE PE
1 = PRESET TERMINAL COUNT
Cin Cout Cin Cout
L.S.D. M.S.D. INDICATOR
CLOCK CLOCK
1 = UP MC14516B MC14516B
U/D U/D
0 = DOWN R R
P0 P1 P2 P3 P0 P1 P2 P3
P0 P1 P2 P3 P4 P5 P6 P7
+VDD +VDD
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
CLOCK RESISTORS = 10 kW
RESET
+VDD
OPEN = COUNT
NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) is disabled while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count
up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.
(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.
Figure 3. Presettable Cascaded 8–Bit Up/Down Counter
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282
CLOCK
UP/DOWN
CARRY IN
(MSD)
PE
P7
P6
P5
P4
P3
P2
P1
P0
CARRY OUT
(MSD)
283
Q7
Q6
MC14516B
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Q5
Q4
Q3
Q2
Q1
Q0
CARRY OUT
(LSD)
RESET
COUNT 13 14 15 16 17 18 19 18 17 16 15 14 13 251 252 253 254 255 0 1 2 3 2 1 0 1 2

TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8–BIT UP/DOWN COUNTER
PRESET RESET
PRESET ENABLE ENABLE
UP COUNT DOWN COUNT UP COUNT DOWN UP COUNT
COUNT
MC14516B
fout
BUFFER
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
PE PE
Cin Cout Cin Cout
CLOCK L.S.D. CLOCK M.S.D.
MC14516B MC14516B
U/D U/D
R R
P0 P1 P2 P3 P0 P1 P2 P3
P0 P1 P2 P3 P4 P5 P6 P7
+VDD +VDD
THUMBWHEEL SWITCHES
CLOCK (fin) (OPEN FOR “0”) RESISTORS = 10 k W
RESET fin
+VDD fout =
n
OPEN = COUNT
NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example,
the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For this divide operation,
both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.
Figure 4. Programmable Cascaded Frequency Divider
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284
MC14517B
Dual 64-Bit Static Shift

Register
The MC14517B dual 64–bit static shift register consists of two
identical, independent, 64–bit registers. Each register has separate clock
and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data
at the data input is entered by clocking, regardless of the state of the write http://onsemi.com
enable input. An output is disabled (open circuited) when the write enable
input is high. During this time, data appearing at the data input as well as MARKING
the 16–bit, 32–bit, and 48–bit taps may be entered into the device by DIAGRAMS
application of a clock pulse. This feature permits the register to be loaded 16
with 64 bits in 16 clock periods, and also permits bus logic to be used. PDIP–16
P SUFFIX MC14517BCP
This device is useful in time delay circuits, temporary memory storage AWLYYWW
circuits, and other serial shift register applications. CASE 648
1
• Fully Static Operation 16
• Output Transitions Occur on the Rising Edge of the Clock Pulse

SOIC–16 14517B
• Exceedingly Slow Input Transition Rates May Be Applied to the DW SUFFIX
Clock Input CASE 751G
AWLYYWW
• 3–State Output at 64th–Bit Allows Use in Bus Logic Applications
• Shift Registers of any Length may be Fully Loaded with 16 Clock 1
Pulses
WL or L = Wafer Lot
• Capable of Driving Two Low–power TTL Loads or One Low–power YY or Y = Year
Schottky TTL Load Over the Rated Temperature Range WW or W = Work Week

Symbol Parameter Value Unit ORDERING INFORMATION
(DC or Transient) MC14517BCP PDIP–16 2000/Box
Iin, Iout Input or Output Current ±10 mA MC14517BDW SOIC–16 47/Rail

may occur.

March, 2000 – Rev. 3 MC14517B/D
MC14517B
PIN ASSIGNMENT
Q16A 1 16 VDD
Q48A 2 15 Q16B
WEA 3 14 Q48B
CA 4 13 WEB
Q64A 5 12 CB
Q32A 6 11 Q64B
DA 7 10 Q32B
VSS 8 9 DB
FUNCTIONAL TRUTH TABLE (X = Don’t Care)

Write
Clock Enable Data 16–Bit Tap 32–Bit Tap 48–Bit Tap 64–Bit Tap
0 0 X Content of 16–Bit Content of 32–Bit Content of 48–Bit Content of 64–Bit
Displayed Displayed Displayed Displayed
0 1 X High Impedance High Impedance High Impedance High Impedance
1 0 X Content of 16–Bit Content of 32–Bit Content of 48–Bit Content of 64–Bit
1 1 X High Impedance High Impedance High Impedance High Impedance
0 Data entered Content of 16–Bit Content of 32–Bit Content of 48–Bit Content of 64–Bit
into 1st Bit Displayed Displayed Displayed Displayed
1 Data entered Data at tap Data at tap Data at tap High Impedance
into 1st Bit entered into 17–Bit entered into 33–Bit entered into 49–Bit
0 X Content of 16–Bit Content of 32–Bit Content of 48–Bit Content of 64–Bit
1 X High Impedance High Impedance High Impedance High Impedance
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286
MC14517B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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287
MC14517B
Characteristic
Symbol
tTLH, tTHL
VDD Min Typ (7.) Max Unit
ns
10 125 75 —
15 100 60 —
10 — 6.7 4.0
15 — 8.3 5.3
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 —
10 See Note (8.)
15
Data to Clock Setup Time tsu 5.0 0 – 40 — ns
10 10 – 15 —
15 15 0 —
Data to Clock Hold Time th 5.0 150 75 — ns
10 75 25 —
15 35 10 —
Write Enable to Clock Setup Time tsu 5.0 400 170 — ns
10 200 65 —
15 110 50 —
Write Enable to Clock Release Time trel 5.0 380 160 — ns
10 180 55 —
15 100 40 —
8. When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall
time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.
VDD
CL
CL
Q16 Q32 Q48 Q64
D D
REPETITIVE WAVEFORM C C CL
VDD WE
fo
VSS CL
C
VDD D
C
D VSS
WE
(f = 1/2 fo)
Q16 Q32 Q48 Q64
VSS
50 µF CL CL CL CL
ID
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288
MC14517B
Vout = VOH Vout = VOL

VDD = VGS VDD = VGS
Q16 Q32 Q48 Q64 Q16 Q32 Q48 Q64

D D
C C
WE WE
D D
C C
IOH IOL
WE WE
Q16 Q32 Q48 Q64 Q16 Q32 Q48 Q64
EXTERNAL EXTERNAL
POWER POWER
SUPPLY VSS SUPPLY
VSS
(Output being tested should be in the high–logic state) (Output being tested should be in the low–logic state)
Figure 2. Typical Output Source Current Figure 3. Typical Output Sink Current
tWH
tWL VDD
PIN NO’S 1 2 16 17 18 19 90% 33
50%
CLOCK 4 (12) 10% VSS
trel tsu
WRITE 3 (13) VDD
th1 th0 VSS
20 ns
tsu1 tsu0 VDD
DATA IN 7 (9) 90%
th1 50% 50%
10% VSS
tsu1 tsu0 tPHL tPLH
VOH VDD
16–BIT OUTPUT 1 (15) th0 VDD 90%
th1 10%
17–BIT INPUT tTLH V VSS
tsu1 tsu0 20 ns tPHL tTHL OL
tPLH VOH VDD
32–BIT OUTPUT 6 (10) th0 VDD 90% 50%
th1 10%
33–BIT INPUT tPHL tTLH VOL VSS
tsu1 tsu0 20 ns tTHL
tPLH VDD
VOH
48–BIT OUTPUT 2 (14) th0 VDD
49–BIT INPUT VOL VSS
20 ns tPHL tTLH tTHL
tPLH VDD
64–BIT OUTPUT 5 (11)
VSS
tTLH
tTHL
Figure 4. AC Test Waveforms
EXPANDED BLOCK DIAGRAM (1/2 OF DEVICE SHOWN)
CLOCK
D Q D Q D Q D Q D Q D Q D Q D Q D
DATA C 1 C 2 C 16 C 17 C 32 C 33 C 48 C 49 C 64 Q
3–STATE WE 3–STATE WE 3–STATE WE 3–STATE
WRITE
WRITE ENABLE = 0, 16–BIT OUTPUT 32–BIT OUTPUT 48–BIT OUTPUT 64–BIT OUTPUT
ENABLE
WRITE ENABLE = 1, 17–BIT INPUT 33–BIT INPUT 49–BIT INPUT HIGH IMPEDANCE
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289
MC14518B
Dual Up Counters
The MC14518B dual BCD counter and the MC14520B dual binary
counter are constructed with MOS P–channel and N–channel
enhancement mode devices in a single monolithic structure. Each
consists of two identical, independent, internally synchronous 4–stage
counters. The counter stages are type D flip–flops, with
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interchangeable Clock and Enable lines for incrementing on either the
positive–going or negative–going transition as required when
cascading multiple stages. Each counter can be cleared by applying a MARKING
high level on the Reset line. In addition, the MC14518B will count out DIAGRAMS
of all undefined states within two clock periods. These complementary 16
MOS up counters find primary use in multi–stage synchronous or PDIP–16
P SUFFIX MC14518BCP
ripple counting applications requiring low power dissipation and/or CASE 648 AWLYYWW
high noise immunity.
1
16
• Internally Synchronous for High Internal and External Speeds SOIC–16 14518B
• Logic Edge–Clocked Design — Incremented on Positive Transition DW SUFFIX

CASE 751G
of Clock or Negative Transition on Enable AWLYYWW
1
16
SOEIAJ–16
F SUFFIX MC14518B
CASE 966 AWLYWW
1
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V WL or L = Wafer Lot
(DC or Transient) YY or Y = Year
WW or W = Work Week
Iin, Iout Input or Output Current ±10 mA
TL Lead Temperature 260 °C MC14518BDW SOIC–16 47/Rail

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14518BFEL SOEIAJ–16 See Note 1.
This device contains protection circuitry to guard against damage due to high 1. For ordering information on the EIAJ version of
static voltages or electric fields. However, precautions must be taken to avoid the SOIC packages, please contact your local
applications of any voltage higher than maximum rated voltages to this ON Semiconductor representative.

March, 2000 – Rev. 3 MC14518B/D
MC14518B
PIN ASSIGNMENT
CA 1 16 VDD
EA 2 15 RB
Q0A 3 14 Q3B
Q1A 4 13 Q2B
Q2A 5 12 Q1B
Q3A 6 11 Q0B
RA 7 10 EB
VSS 8 9 CB
BLOCK DIAGRAM
CLOCK
Q0 3
1
Q1 4
C
2 Q2 5
ENABLE Q3 6
R
7
CLOCK 11
Q0
9
Q1 12
C
10 Q2 13
ENABLE Q3 14
R
15
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Clock Enable Reset Action
1 0 Increment Counter
0 0 Increment Counter
X 0 No Change
X 0 No Change
0 0 No Change
1 0 No Change
X X 1 Q0 thru Q3 = 0
X = Don’t Care
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291
MC14518B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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292
MC14518B

All Types
Typ (8.) Max Unit
Clock to Q/Enable to Q tPHL
Reset to Q tPHL ns
tPHL = (1.7 ns/pF) CL + 265 ns 5.0 — 330 650
tPHL = (0.66 ns/pF) CL + 117 ns 10 — 130 230
tPHL = (0.66 ns/pF) CL + 95 ns 15 — 90 170
Clock Pulse Width tw(H) 5.0 200 100 — ns
tw(L) 10 100 50 —
15 70 35 —
10 — 6.0 3.0
15 — 8.0 4.0
Clock or Enable Rise and Fall Time tTHL, tTLH 5.0 — — 15 µs
10 — — 5
15 — — 4
Enable Pulse Width tWH(E) 5.0 440 220 — ns
10 200 100 —
15 140 70 —
Reset Pulse Width tWH(R) 5.0 280 125 — ns
10 120 55 —
15 90 40 —
Reset Removal Time trem 5.0 –5 – 45 — ns
10 15 – 15 —
15 20 –5 —
VDD
0.01 µF
500 µF ID CERAMIC
PULSE
C Q0
GENERATOR Q1
Q2 CL
E Q3 CL
R CL
CL
VSS
20 ns 20 ns
90%
50%
10%
VSS
VARIABLE
WIDTH
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293
MC14518B
VDD 20 ns 20 ns
90% VDD
CLOCK 50%
PULSE Q0 INPUT 10%
C VSS
GENERATOR tWH tWL
Q1
tPLH tPHL
Q2 CL
E CL 90%
R Q3 CL 50%
CL 10%
VSS Q
tr tf
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CLOCK
ENABLE
RESET
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
Q0
Q1
MC14518B
Q2
Q3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
Q0
Q1
MC14520B
Q2
Q3
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294
MC14518B
Q0 Q1 Q2 Q3
D Q D Q D Q D Q
C Q C Q C Q C Q
R R R R
RESET
ENABLE
CLOCK
Figure 4. Decade Counter (MC14518B) Logic Diagram

Q0 Q1 Q2 Q3
D Q D Q D Q D Q
C Q C Q C Q C Q
R R R R
RESET
ENABLE
CLOCK
Figure 5. Binary Counter (MC14520B) Logic Diagram

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295
MC14521B
24-Stage Frequency Divider

The MC14521B consists of a chain of 24 flip–flops with an input
circuit that allows three modes of operation. The input will function as
a crystal oscillator, an RC oscillator, or as an input buffer for an
external oscillator. Each flip–flop divides the frequency of the
previous flip–flop by two, consequently this part will count up to 224 =
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16,777,216. The count advances on the negative going edge of the
clock. The outputs of the last seven–stages are available for added
flexibility. MARKING
DIAGRAMS
• All Stages are Resettable 16
• Reset Disables the RC Oscillator for Low Standby Power Drain PDIP–16
MC14521BCP
• RC and Crystal Oscillator Outputs Are Capable of Driving External P SUFFIX
AWLYYWW
CASE 648
Loads
1
• Test Mode to Reduce Test Time
• VDD′ and VSS′ Pins Brought Out on Crystal Oscillator Inverter to 16
SOIC–16
Allow the Connection of External Resistors for Low–Power 14521B
D SUFFIX AWLYWW
Operation CASE 751B
16
Schottky TTL Load over the Rated Temperature Range.
SOEIAJ–16
F SUFFIX MC14521B
CASE 966 AWLYWW
1
Symbol Parameter Value Unit A = Assembly Location
WL or L = Wafer Lot
WW or W = Work Week
(DC or Transient)
Iin, Iout Input or Output Current ± 10 mA ORDERING INFORMATION
(8–Second Soldering) MC14521BF SOEIAJ–16 See Note 1.
may occur.
3. Temperature Derating: MC14521BFR2 SOEIAJ–16 See Note 1.
This device contains protection circuitry to guard against damage due to high the SOIC packages, please contact your local
static voltages or electric fields. However, precautions must be taken to avoid ON Semiconductor representative.

March, 2000 – Rev. 3 MC14521B/D
MC14521B
PIN ASSIGNMENT
Q24 1 16 VDD
RESET 2 15 Q23
VSS′ 3 14 Q22
OUT 2 4 13 Q21
VDD′ 5 12 Q20
IN 2 6 11 Q19
7 10 Q18
VSS 8 9 IN 1
BLOCK DIAGRAM
RESET
2
Output Count Capacity
Q18 218 = 262,144
Q19 219 = 524,288
STAGES STAGES
9 6 1 THRU 17 18 THRU 24 Q20 220 = 1,048,576
IN 1 IN 2 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q21 221 = 2,097,152
Q22 222 = 4,194,304
VDD = PIN 16 Q23 223 = 8,388,608
VSS = PIN 8
5 4 Q24 224 = 16,777,216
7 VDD′ 3 OUT2 10 11 12 13 14 15 1
OUT 1 VSS′
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297
MC14521B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) Pins 4 & 7 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 — mAdc
(VOH = 4.6 Vdc) Pins 1, 10, 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 11, 12, 13, 14 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) and 15 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

(Vin = 0)
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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298
MC14521B
VDD
Output Rise and Fall Time (Counter Outputs) tTLH, tTHL ns
Propagation Delay Time tPHL, tPLH µs
Clock to Q18
tPHL, tPLH = (1.7 ns/pF) CL + 4415 ns 5.0 — 4.5 9.0
tPHL, tPLH = (0.66 ns/pF) CL + 1667 ns 10 — 1.7 3.5
Clock to Q24
tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns 5.0 — 6.0 12
Reset to Qn
tPHL = (1.7 ns/pF) CL + 1215 ns 5.0 — 1300 2600
tPHL = (0.66 ns/pF) CL + 467 ns 10 — 500 1000
tPHL = (0.5 ns/pF) CL + 350 ns 15 — 375 750
Clock Pulse Width tWH(cl) 5.0 385 140 — ns
10 150 55 —
15 120 40 —
10 — 9.0 5.0
15 — 12 6.5
Clock Rise and Fall Time tTLH, tTHL 5.0 — — 15 µs
10 — — 5.0
15 — — 4.0
Reset Pulse Width tWH(R) 5.0 1400 700 — ns
10 600 300 —
15 450 225 —
Reset Removal Time trem 5.0 30 – 200 — ns
10 0 – 160 —
15 – 40 – 110 —
VDD
500 µF 0.01 µF
ID
CERAMIC
VDD VDD
Q18 20 ns 20 ns
PULSE CL VDD
IN 2 Q19 Vin 90%
GENERATOR CL 50%
Q20 10% 0V
CL
Q21 50% DUTY CYCLE
Q22 CL
Q23 CL
R
Q24 CL
CL
VSS VSS
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299
MC14521B
VDD
VDD VDD′
20 ns 20 ns 20 ns
IN 2
Q18
PULSE IN 2 CL 90%
GENERATOR Q19 50%
CL 10%
Q20
CL tWL tWH
Q21
Q22 CL
90%
Q23 CL 50%
R Qn
CL 10%
Q24
CL tPLH tPHL
VSS VSS′ tTLH tTHL
500 kHz 50 kHz

Characteristic Circuit Circuit Unit
Crystal Characteristics
Resonant Frequency 500 50 kHz
Equivalent Resistance, RS 1.0 6.2 kΩ
External Resistor/Capacitor Values
VDD
Ro 47 750 kΩ
Ro CT 82 82 pF
R* CS 20 20 pF
VDD VDD′
18 M Frequency Stability
IN 1 OUT 1 Frequency Change as a Function
OUT 2 of VDD (TA = 25_C)
Q18 VDD Change from 5.0 V to 10 V
Q19 + 6.0 + 2.0 ppm
VDD Change from 10 V to 15 V
IN 2 Q20 + 2.0 + 2.0 ppm
Q21 Frequency Change as a Function
Q22 of Temperature (VDD = 10 V)
– 4.0 – 2.0 ppm
Q23 TA Change from – 55_C to + 25_C
CS CT + 100 + 120 ppm
R Q24 MC14521 only
Complete Oscillator*
VSS VSS′
TA Change from + 25_C to + 125_C
R*
MC14521 only
– 2.0 – 2.0 ppm
Complete Oscillator*
– 160 – 560 ppm
*Optional for low power operation,
10 kΩ ≤ R ≤ 70 kΩ. *Complete oscillator includes crystal, capacitors, and resistors.
Figure 3. Crystal Oscillator Circuit Figure 4. Typical Data for Crystal Oscillator Circuit
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300
MC14521B
100
VDD = 10 V TEST CIRCUIT
50

8.0 FIGURE 7
TEST CIRCUIT
VDD = 15 V 20 f AS A FUNCTION
FIGURE 7
4.0 OF RTC
10 (C = 1000 pF)
5.0 (RS ≈ 2RTC)
0 f AS A FUNCTION
OF C
10 V 2.0 (RTC = 56 kΩ)
–4.0
1.0 (RS = 120 k)
–8.0 0.5
5.0 V
0.2
–12
RTC = 56 kΩ, RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C 0.1
C = 1000 pF
{ RS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
1.0 k 10 k 100 k 1.0 m
–16 RTC, RESISTANCE (OHMS)
–55 –25 0 25 50 75 100 125 0.0001 0.001 0.01 0.1
TA, AMBIENT TEMPERATURE (°C), DEVICE ONLY C, CAPACITANCE (µF)

RS RTC VDD VDD

C
VDD′
VDD VDD′
IN 1 Q18
IN 1 OUT 1 Q19
OUT 2 Q20
Q18 Q21
Q19 PULSE IN 2 Q22
IN 2 Q20 GENERATOR Q23
Q21 Q24
Q22 OUT 1
Q23 R OUT 2
R Q24
VSS VSS
VSS VSS′
Figure 7. RC Oscillator Circuit Figure 8. Functional Test Circuit
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MC14521B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ FUNCTIONAL TEST SEQUENCE
Reset
Inputs
In 2 Out 2 VSS′
Outputs
VDD′ Q18 thru
Comments
Counter is in three 8–stage
Q24 sections in parallel mode
Counter is reset. In 2 and
1 0 0 VDD Gnd 0 Out 2 are connected
together
A test function (see Figure 8) has been 0 1 1 First “0” to “1” transition
included for the reduction of test time required to on In 2, Out 2 node.
exercise all 24 counter stages. This test function 0 0 255 “0” to “1” transitions
divides the counter into three 8–stage sections, 1 1 are clocked into this In 2,
and 255 counts are loaded in each of the — — Out 2 node.
8–stage sections in parallel. All flip–flops are — —
now at a logic
g “1”. The counter is now returned — —
to the normal 24–stages in series configuration. The 255th “0” to “1”
1 1 1
One more pulse is entered into Input 2 (In 2) transition.
which will cause the counter to ripple from an all 0 0 1
“1” state to an all “0” state. 0 0 1
G d
Gnd
Counter converted back to
1 0 VDD 1
24–stages in series mode.
Out 2 converts back to an
1 0 1
output.
Counter ripples from an all
0 1 0 “1” state to an all “0” stage.
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MC14521B
LOGIC DIAGRAM
VDD RESET
5 2
9 STAGES
1 2 8
3 THRU 7
IN 1
6 4
IN 2 OUT 2
7 3
OUT 1 VSS
9 10 STAGES 16
11 THRU 15
17 18 19 20 21 22 23 24
10 11 12 13 14 15 1 VDD = PIN 16
Q18 Q19 Q20 Q21 Q22 Q23 Q24 VSS = PIN 8
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MC14526B
Presettable 4-Bit Down

Counters
The MC14526B binary counter is constructed with MOS P–channel
and N–channel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded “0” state output for divide–by–N applications. In http://onsemi.com
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade divide–by–N MARKING
operation with no additional gates required. The Inhibit input allows DIAGRAMS
disabling of the pulse counting function. Inhibit may also be used as a 16
negative edge clock. PDIP–16
P SUFFIX MC14526BCP
This complementary MOS counter can be used in frequency AWLYYWW
synthesizers, phase–locked loops, and other frequency division CASE 648
applications requiring low power dissipation and/or high noise 1
immunity. 16
14526B
• Logic Edge–Clocked Design — Incremented on Positive Transition SOIC–16
DW SUFFIX
of Clock or Negative Transition of Inhibit CASE 751G
• Asynchronous Preset Enable AWLYYWW

SOEIAJ–16
F SUFFIX MC14526B
CASE 966 AWLYWW
1
WL or L = Wafer Lot
(8–Second Soldering) MC14526BDWR2 SOIC–16 1000/Tape & Reel
may occur.

March, 2000 – Rev. 3 MC14526B/D
MC14526B
PIN ASSIGNMENT
Q3 1 16 VDD
P3 2 15 Q2
PE 3 14 P2
INHIBIT 4 13 CF
P0 5 12 “0”
CLOCK 6 11 P1
7 10 RESET
VSS 8 9 Q1
FUNCTION TABLE
Inputs Output
Preset Cascade Resulting
Clock Reset Inhibit Enable Feedback “0” Function
X H X L L L Asynchronous
y reset*
X H X H L H Asynchronous reset
X H X X H H A
Asynchronous
h reset
X L X H X L Asynchronous preset
L H L X L Decrement inhibited
L L L X L Decrement inhibited
L L L L L No change**
g (inactive
( edge)
g )
H L L L L No change** (inactive edge)
L L L L L D
Decrement**
**
H L L L L Decrement**
X = Don’t Care
NOTES:
** Output “0” is low when reset goes high only it PE and CF are low.
** Output “0” is high when reset is low, only if CF is high and count is 0000.
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MC14526B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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306
MC14526B
Characteristic
Symbol
tTLH,
ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns (Figures 4, 5) 10 — 50 100
Propagation Delay Time (Inhibit Used as Negative tPLH, ns
Edge Clock) tPHL
Clock or Inhibit to Q (Figures 4, 5, 6)
Clock or Inhibit to “0”
Propagation Delay Time tPLH, 5.0 — 260 520 ns

Pn to Q tPHL 10 — 120 240
(Figures 4, 7) 15 — 100 200
Propagation Delay Time tPHL 5.0 — 250 500 ns
Reset to Q 10 — 110 220
(Figure 8) 15 — 80 160
Propagation Delay Time tPHL, 5.0 — 220 440 ns
Preset Enable to “0” tPLH 10 — 100 200
(Figures 4, 9) 15 — 80 160
Clock or Inhibit Pulse Width tw 5.0 250 125 — ns
10 100 50 —
(Figures 5, 6) 15 80 40 —
Clock Pulse Frequency (with PE = low) fmax 5.0 — 2.0 1.5 MHz
10 — 5.0 3.0
(Figures 4, 5, 6) 15 — 6.6 4.0
Clock or Inhibit Rise and Fall Time tr, 5.0 — — 15 µs
tf 10 — — 5
(Figures 5, 6) 15 — — 4
Pn to Preset Enable 10 50 15 —
(Figure 10) 15 40 10 —
Preset Enable to Pn 10 30 –5 —
(Figure 10) 15 30 0 —
Preset Enable Pulse Width tw 5.0 250 125 — ns
10 100 50 —
(Figure 10) 15 80 40 —
10 250 125 —
(Figure 8) 15 200 100 —
10 20 – 30 —
(Figure 8) 15 30 – 20 —
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307
MC14526B
VOH VOL
VDD = –VGS VDD = VGS
CF Q0 CF Q0
PE PE
P0 Q1 P0 Q1
P1 P1
P2 Q2 P2 Q2
P3 IOH P3 IOL
RESET Q3 RESET Q3
INHIBIT INHIBIT
CLOCK “0” CLOCK “0”
EXTERNAL EXTERNAL
VSS VSS
POWER POWER
SUPPLY SUPPLY

VDD
CF Q0
PE
P0 Q1
P1
P2 Q2
P3 CL
RESET Q3 TEST POINT
CL
INHIBIT CL
CLOCK “0” Q or “0”
CL DEVICE
VSS CL UNDER
TEST CL*
PULSE
GENERATOR 20 ns 20 ns
90% VDD
CLOCK 50%
10% VSS
VARIABLE
WIDTH 50% DUTY CYCLE *Includes all probe and jig capacitance.
Figure 3. Power Dissipation Figure 4. Test Circuit
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308
MC14526B
SWITCHING WAVEFORMS
tr tf tf tr
VDD VDD
90% 90%
CLOCK 50% INHIBIT 50%
10% VSS 10%
VSS
tw tw
1/fmax 1/fmax
tPLH tPHL tPLH tPHL
ANY Q 90% 90%

ANY Q
OR “0” 50% OR “0” 50%
10% 10%
tTLH tTHL tTLH tTHL
Figure 5. Figure 6.
tw
VDD
RESET 50%
VSS
tr tf
tPHL
VDD
90%
ANY P 50%
10% ANY Q 50%
VSS
tPLH tPHL
trem
ANY Q VDD
50%
CLOCK
50%
VSS
Figure 7. Figure 8.
VALID
tr tf VDD
VDD ANY P 50%
PRESET 90%
ENABLE 50% VSS
10% GND
tsu th
tPHL tPLH VDD
PRESET
ENABLE 50%
“0” 50% VSS
tw
Figure 9. Figure 10.
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309
MC14526B
PIN DESCRIPTIONS
Preset Enable (Pin 3) — If Reset is low, a high level on other than all zeroes, the “0” output is valid after the rising
the Preset Enable input asynchronously loads the counter edge of Preset Enable (when Cascade Feedback is high). See
with the programmed values on P0, P1, P2, and P3. the Function Table.
Inhibit (Pin 4) — A high level on the Inhibit input pre– Cascade Feedback (Pin 13) — If the Cascade Feedback
vents the Clock from decrementing the counter. With Clock input is high, a high level is generated at the “0” output when
(pin 6) held high, Inhibit may be used as a negative edge the count is all zeroes. If Cascade Feedback is low, the “0”
clock input. output depends on the Preset Enable input level. See the
Clock (Pin 6) — The counter decrements by one for each Function Table.
rising edge of Clock. See the Function Table for level P0, P1, P2, P3 (Pins 5, 11, 14, 2) — These are the preset
requirements on the other inputs. data inputs. P0 is the LSB.
Reset (Pin 10) — A high level on Reset asynchronously Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) — These are the
forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is synchronous counter outputs. Q0 is the LSB.
high, causes the “0” output to go high. VSS (Pin 8) — The most negative power supply potential.
“0” (Pin 12) — The “0” (Zero) output issues a pulse one This pin is usually ground.
clock period wide when the counter reaches terminal count VDD (Pin 16) — The most positive power supply
(Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and potential. VDD may range from 3 to 18 V with respect to VSS.
Preset Enable is low. When presetting the counter to a value
STATE DIAGRAM
MC14526B
0 1 2 3 4
15 5
14 6
13 7
12 11 10 9 8
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310
MC14526B
MC14526B LOGIC DIAGRAM (Binary Down Counter)
P0 Q0 P1 Q1 P2 Q2 P3 Q3
5 7 11 9 14 15 2 1
D R D RQ D RQ D RQ
C C C C
T PE Q T PE Q T PE Q T PE Q
VDD VDD
13
CF
PE 3
INHIBIT 4
12
“0”
CLOCK 6
10
RESET
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311
MC14526B
Divide–By–N, Single Stage Cascaded, Presettable Divide–By–N

Figure 11 shows a single stage divide–by–N application. Figure 12 shows a three stage cascade application. Taking
To initialize counting a number, N is set on the parallel Reset high loads N. Only the first stage’s Reset pin (least
inputs (P0, P1, P2, and P3) and reset is taken high significant counter) must be taken high to cause the preset
asynchronously. A zero is forced into the master and slave for all stages, but all pins could be tied together, as shown.
of each bit and, at the same time, the “0” output goes high. When the first stage’s Reset pin goes high, the “0” output
Because Preset Enable is tied to the “0” output, preset is is latched in a high state. Reset must be released while Clock
enabled. Reset must be released while the Clock is high so is high and time allowed for Preset Enable to load N into all
the slaves of each bit may receive N before the Clock goes stages before Clock goes low.
low. When the Clock goes low and Reset is low, the “0” When Preset Enable is high and Clock is low, time must
output goes low (if P0 through P3 are unequal to zero). be allowed for the zero digits to propagate a Cascade
The counter downcounts with each rising edge of the Feedback to the first non–zero stage. Worst case is from the
Clock. When the counter reaches the zero state, an output most significant bit (M.S.B.) to the L.S.B., when the L.S.B.
pulse occurs on “0” which presets N. The propagation delays is equal to one (i.e. N = 1).
from the Clock’s rising and falling edges to the “0” output’s After N is loaded, each stage counts down to zero with
rising and falling edges are about equal, making the “0” each rising edge of Clock. When any stage reaches zero and
output pulse approximately equal to that of the Clock pulse. the leading stages (more significant bits) are zero, the “0”
The Inhibit pin may be used to stop pulse counting. When output goes high and feeds back to the preceding stage.
this pin is taken high, decrementing is inhibited. When all stages are zero, the Preset Enable automatically
loads N while the Clock is high and the cycle is renewed.
P0 Q0
P1 Q1
N
P2 Q2
P3 Q3 BUFFER
VDD fin
CF
“0” N
RESET
VSS INHIBIT
fin CLOCK
PE
Figure 11. ÷ N Counter
LSB MSB
N0 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
VDD
P0 P1 P2 P3 Q0 Q1 Q2 Q3 P0 P1 P2 P3 Q0 Q1 Q2 Q3 P0 P1 P2 P3 Q0 Q1 Q2 Q3
fin CLOCK CLOCK CLOCK
CF CF CF
INHIBIT INHIBIT INHIBIT
VSS RESET “0” PE VSS RESET “0” PE VSS RESET “0” PE
VDD
LOAD
N BUFFER
10 KΩ
VSS fin
N
Figure 12. 3 Stages Cascaded
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312
MC14528B
Dual Monostable
Multivibrator
The MC14528B is a dual, retriggerable, resettable monostable
multivibrator. It may be triggered from either edge of an input pulse,
and produces an output pulse over a wide range of widths, the duration
of which is determined by the external timing components, CX and http://onsemi.com
RX.
• Separate Reset Available MARKING
DIAGRAMS
16
• Triggerable from Leading or Trailing Edge Pulse PDIP–16
AWLYYWW
CASE 648
1
• Pin–for–Pin Replacement with the MC14538B 16
SOIC–16
14528B
D SUFFIX AWLYWW
CASE 751B
1
SOEIAJ–16
VDD DC Supply Voltage Range – 0.5 to +18.0 V MC14528B
F SUFFIX
CASE 966 AWLYWW
(DC or Transient)
1
WL or L = Wafer Lot
2. Maximum Ratings are those values beyond which damage to the device MC14528BCP PDIP–16 2000/Box
may occur.
3. Temperature Derating: MC14528BD SOIC–16 48/Rail
applications of any voltage higher than maximum rated voltages to this MC14528BFEL SOEIAJ–16 See Note 1.
to the range VSS v (Vin or Vout) vVDD. 1. For ordering information on the EIAJ version of

March, 2000 – Rev. 3 MC14528B/D
MC14528B
PIN ASSIGNMENT
VSS 1 16 VDD
CX1/RX1 2 15 VSS
RESET 1 3 14 CX2/RX2
A1 4 13 RESET 2
B1 5 12 A2
Q1 6 11 B2
Q1 7 10 Q2
VSS 8 9 Q2
BLOCK DIAGRAM
CX1 RX1
VDD
1 2
4 6
A1 Q1
5 7
B1 Q1
3
RESET 1
CX2 RX2
VDD
15 14
12 10
A2 Q2
11 9
B2 Q2
13
RESET 2
VDD = PIN 16
VSS = PIN 1, PIN 8, PIN 15
RX AND CX ARE EXTERNAL COMPONENTS
ONE–SHOT SELECTION GUIDE
100 ns 1 ms 10 ms 100 ms 1 ms 10 ms 100 ms 1s 10 s

MC14528B
MC14536B 23 HR
MC14538B
MC14541B 5 MIN.
MC4538A*
*LIMITED OPERATING VOLTAGE (2–6 V)
TOTAL OUTPUT PULSE WIDTH RANGE

RECOMMENDED PULSE WIDTH RANGE
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314
MC14528B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current mAdc

(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) IOH 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) IOL 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current at an IT — IT(CL, CX) = [(CL + 0.36CX)VDDf + 2x10–8 µAdc
external load Capacitance (CL) RXCX(VDD–2)2f] x 10–3
and at external timing where: IT in µA (per circuit), CL and CX in pF, RX in megohms,
capacitance (CX), use the VDD in Vdc, f in kHz is input frequency.
formula — (5.)
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315
MC14528B

CX RX VDD
Characteristic Symbol pF kΩ Vdc Min Typ (9.) Max Unit
Output Rise and Fall Time tTLH, — — ns
Turn–Off, Turn–On Delay Time — A or B to Q or Q tPLH, 15 5.0 ns
Turn–Off, Turn–On Delay Time — A or B to Q or Q tPLH, 1000 10 ns
tPLH, tPHL = (1.7 ns/pF) CL + 620 ns tPHL 5.0 — 705 —
tPLH, tPHL = (0.66 ns/pF) CL + 257 ns 10 — 290 —
tPLH, tPHL = (0.5 ns/pF) CL + 185 ns 15 — 210 —
Input Pulse Width — A or B tWH 15 5.0 5.0 150 70 — ns
10 75 30 —
15 55 30 —
tWL 1000 10 5.0 — 70 — ns
10 — 30 —
15 — 30 —
Output Pulse Width — Q or Q tW 15 5.0 5.0 — 550 — ns
(For CX < 0.01 µF use graph for 10 — 350 —
appropriate VDD level.) 15 — 300 —
Output Pulse Width — Q or Q tW 10,000 10 5.0 15 30 45 µs
(For CX > 0.01 µF use formula: 10 10 50 90
tW = 0.2 RX CX Ln [VDD – VSS]) (6.) 15 15 55 95
Pulse Width Match between Circuits in the same t1 – t2 10,000 10 5.0 — 6.0 25 %
package 10 — 8.0 35
15 — 8.0 35
Reset Propagation Delay — Reset to Q or Q tPLH, 15 5.0 5.0 — 325 600 ns
tPHL 10 — 90 225
15 — 60 170
1000 10 5.0 — 1000 — ns
10 — 300 —
15 — 250 —
Retrigger Time trr 15 5.0 5.0 0 — — ns
10 0 — —
15 0 — —
1000 10 5.0 0 — — ns
10 0 — —
15 0 — —
External Timing Resistance RX — — — 5.0 — 1000 kΩ
External Timing Capacitance CX — — — No Limits (7.) µF
6. RX is in Ohms, CX is in farads, VDD and VSS in volts, PWout in seconds.
7. If CX > 15 µF, Use Discharge Protection Diode DX, per Fig. 9.
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316
MC14528B
FUNCTION TABLE
Inputs Outputs
Reset A B Q Q
H H
H L
H L Not Triggered
H H Not Triggered
H L, H, H Not Triggered
H L L, H, Not Triggered
L X X L H
X X Not Triggered
VDD VDD
16 16
IOL
A Q OPEN A Q
VOL
B B
VOH
RESET Q RESET Q OPEN
IOH
8 VSS 8 VSS
Figure 1. Output Source Current Test Circuit Figure 2. Output Sink Current Test Circuit
VDD
0.1 mF
500 pF ID
CERAMIC
RX RX′
CX CX′
20 ns 20 ns
VDD
Vin 90%
A
B Q Vin 10% 0V
CL
RESET Q DUTY CYCLE = 50%
CL
A′ Q′
CL
B′ Q′
CL
RESET′
VSS
Figure 3. Power Dissipation Test Circuit and Waveforms
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317
MC14528B
VDD
INPUT CONNECTIONS
*CX = 15 pF
RX RX′ *CL = 15 pF Characteristics Reset A B
CX CX′
RX = 5.0 k W tPLH, tPHL, tTLH, tTHL VDD PG1 VDD
tW
tPLH, tPHL, tTLH, tTHL VDD VSS PG2
A tW
PULSE
GENERATOR tPLH(R), tPHL(R), tW PG3 PG1 PG2
B Q
CL
RESET Q
PULSE
CL
GENERATOR PG1 =
A′ Q′ *Includes capacitance of probes,
CL wiring, and fixture parasitic.
B′ Q′ PG2 =
PULSE NOTE: AC test waveforms for
CL
GENERATOR
RESET′ PG1, PG2, and PG3 on
next page. PG3 =
VSS
Figure 4. AC Test Circuit
90% VDD
50% 10% 50%
A VSS
tWH tTLH tTHL
tTHL tTLH
B VDD
50% 90%
10% VSS
tWL
tTHL tTLH
RESET VDD
90% 50%
10% VSS
tTHL tWL
tW
tPLH tTLH tPHL trr
90% VOH
50% 50% 50% 10% 50%
Q VOL
tTLH tTHL
tPHL tPHL tPHL
Q VOH
50% 50% 90% 50% 50%
10% VOL
Figure 5. AC Test Waveforms
1000
VDD = 15 V
10 V 15 V
5.0 V 10 V
100 5.0 V
t W, PULSE WIDTH ( m s)
RX = 100 k W 15 V
10 V
10
5.0 V
RX = 10 k W
1.0 RX = 5.0 k W
15 V
10 V
5.0 V
0.1
10 100 1000 10,000 100,000
CX, EXTERNAL CAPACITANCE (pF)
Figure 6. Pulse Width versus CX
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318
MC14528B
Cx Rx Cx Rx
VDD VDD
RISING EDGE RISING EDGE

Q A Q
TRIGGER A TRIGGER
B Q B Q
RESET RESET
VDD
VDD VDD
Cx Rx
Cx Rx
VDD
VDD
A Q
A Q
FALLING EDGE B Q
FALLING EDGE B Q TRIGGER RESET
TRIGGER RESET
VDD
VDD
Figure 7. Retriggerable Figure 8. Non–Retriggerable

Monostables Circuitry Monostables Circuitry
DX
Cx VDD
NC
Rx 1, 15 2, 14
VDD
Q NC
A
Q
B Q NC
Q RESET
RESET
VDD
VDD VDD
VDD
Figure 9. Use of a Diode to Limit Figure 10. Connection of Unused Sections

Power Down Current Surge
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319
MC14532B
8-Bit Priority Encoder

The MC14532B is constructed with complementary MOS (CMOS)
enhancement mode devices. The primary function of a priority
encoder is to provide a binary address for the active input with the
highest priority. Eight data inputs (D0 thru D7) and an enable input
(Ein) are provided. Five outputs are available, three are address outputs
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(Q0 thru Q2), one group select (GS) and one enable output (Eout).
Schottky TTL Load over the Rated Temperature Range PDIP–16
P SUFFIX MC14532BCP
CASE 648 AWLYYWW

Symbol Parameter Value Unit SOIC–16
14532B
D SUFFIX AWLYWW
VDD DC Supply Voltage Range – 0.5 to +18.0 V CASE 751B
(DC or Transient)
16
(DC or Transient) per Pin F SUFFIX MC14532B
CASE 966 AWLYWW
1
YY or Y = Year
TL Lead Temperature 260 °C WW or W = Work Week
applications of any voltage higher than maximum rated voltages to this MC14532BD SOIC–16 48/Rail
MC14532BFR1 SOEIAJ–16 See Note 1.


March, 2000 – Rev. 3 MC14532B/D
MC14532B
PIN ASSIGNMENT
D4 1 16 VDD
D5 2 15 Eout
D6 3 14 GS
D7 4 13 D3
Ein 5 12 D2
Q2 6 11 D1
Q1 7 10 D0
VSS 8 9 Q0
TRUTH TABLE
Input Output
Ein D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0 Eout
0 X X X X X X X X 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 1
1 1 X X X X X X X 1 1 1 1 0
1 0 1 X X X X X X 1 1 1 0 0
1 0 0 1 X X X X X 1 1 0 1 0
1 0 0 0 1 X X X X 1 1 0 0 0
1 0 0 0 0 1 X X X 1 0 1 1 0
1 0 0 0 0 0 1 X X 1 0 1 0 0
1 0 0 0 0 0 0 1 X 1 0 0 1 0
1 0 0 0 0 0 0 0 1 1 0 0 0 0
X = Don’t Care
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MC14532B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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322
MC14532B
Characteristic
Symbol
tTLH,
ns
Propagation Delay Time — Ein to Eout tPLH, ns
Propagation Delay Time — Ein to GS tPLH, ns
tPLH, tPHL = (0.66 ns/pF) CL 57 ns 10 — 90 180
Propagation Delay Time — Ein to Qn tPHL, ns
tPLH, tPHL = (1.7 ns/pF) CL + 195 ns tPLH 5.0 — 280 560
Propagation Delay Time — Dn to Qn tPLH, ns
Propagation Delay Time — Dn to GS tPLH, ns
Vout
Ein
D0
D1 Eout
D2 Q0
SWITCH
MATRIX D3 Q1
D4 Q2 VDD
ID
D5 GS
D6 500 µF ID 0.01 µF
D7
EXTERNAL
POWER
SUPPLY Ein Eout
D0 CL
VGS = VDD VGS = – VDD D1 Q0

VDS = Vout VDS = Vout – VDD D2 CL
Output
Sink Current Source Current D3 Q1
Under
D4 CL
Test D0 thru D7 Ein D0 thru D6 D7 Ein
D5 Q2
Eout X 0 0 0 1 CL
Q0 X 0 0 1 1 PULSE D6
Q1 X 0 0 1 1 GENERATOR D7 GS
Q2 X 0 0 1 1 (fo) CL
VSS
GS X 0 0 1 1
Figure 1. Typical Sink and Source

Current Characteristics Figure 2. Typical Power Dissipation Test Circuit
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323
MC14532B
VDD
Ein Eout
D0 CL
D1 Q0
PROGRAMMABLE D2 CL
PULSE D3 Q1
GENERATOR D4 CL
D5 Q2
D6 CL
D7 GS
VSS CL
NOTE: Input rise and fall times are 20 ns

PIN
NO.
50%
D0 10
50%
D1 11
50%
D2 12
50%
D3 13
50%
D4 1
50%
D5 2
50%
D6 3
50%
D7 4
50%
Ein 5
tPLH tPHL
90%
50%
Eout 15 10%
tTHL
tTLH tPLH tPHL
90%
50%
GS 14 10%
tTLH tPLH tPLH tPLH tTHL
tPLH tPHL tPHL tPHL tPHL
90%
50%
Q0 9 10%
tPLH tPLH tTLH tTHL
tPHL tPHL
90%
50%
Q1 7 10%
tTLH tTHL
tPLH tPHL
90%
50%
10%
Q2 6
tTLH tTHL
Figure 3. AC Test Circuit and Waveforms
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324
MC14532B
LOGIC DIAGRAM
(Positive Logic)
LOGIC EQUATIONS
Eout = Ein D0 D1 D2 D3 D4 D5 D6 D7
Q0 = Ein (D1 D2 D4 D6 + D3 D4 D6 + D5 D6 + D7)
Q1 = Ein (D2 D4 D5 + D3 D4 D5 + D6 + D7)
10 Q2 = Ein (D4 + D5 + D6 + D7)
D0
GS = Ein (D0 + D1 + D2 + D3 + D4 + 05 + D6 + D7)
11
D1 9
Q0
12
D2
13
D3
1
D4
7
Q1
2
D5
3
D6
4
D7
6
5 Q2
Ein
14
GS
15
Eout
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325
MC14532B
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
VDD Ein Eout Ein Eout Eout = “1”

WITH Din = “0”
GS Q2 Q1 Q0 Q2 Q1 Q0
3/4 MC14071B
Q3 Q2 Q1 Q0
Figure 4. Two MC14532B’s Cascaded for 4–Bit Output
VDD VSS
CLOCK
INPUT
C E R C E R
1/2 MC14520B 1/2 MC14520B
DIGITAL TO ANALOG CONVERSION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
The digital eight–bit word to be converted is applied to the
inputs of the MC14512 with the most significant bit at
X7 and the least significant bit at X0. A clock input of up to
2.5 MHz (at VDD = 10 V) is applied to the MC14520B.
A compromise between Ibias for the MC1710 and ∆R
between N and P–channel outputs gives a value of R of
[
33 k ohms. In order to filter out the switching frequencies,
RC should be about 1.0 ms (if R = 33 k ohms, C 0.03 µF). DIGITAL INPUT/OUTPUT
The analog 3.0 dB bandwidth would then be dc to 1.0 kHz. D0 D1 D2 D3 D4 D5 D6 D7 8–BIT WORD
Ein TO BE CONVERTED
ANALOG TO DIGITAL CONVERSION VDD
Q2 Q1 Q0
An analog signal is applied to the analog input of the
X7 X6 X5 X4 X3 X2 X1 X0
MC1710. A digital eight–bit word known to represent a dig- A
itized level less than the analog input is applied to the B MC14512
C Z
MC14512 as in the D to A conversion. The word is increm-
ented at rates sufficient to allow steady state to be reached
MC1710
between incrementations (i.e. 3.0 ms). The output of the R
MC1710 will change when the digital input represents the ANALOG
STOP OUTPUT
first digitized level above the analog input. This word is the WORD C
digital representation of the analog word. INCREMENTATION
ANALOG
INPUT
Figure 5. Digital to Analog and Analog to Digital Converter
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326
MC14536B
Programmable Timer
The MC14536B programmable timer is a 24–stage binary ripple
counter with 16 stages selectable by a binary code. Provisions for an
on–chip RC oscillator or an external clock are provided. An on–chip
monostable circuit incorporating a pulse–type output has been
included. By selecting the appropriate counter stage in conjunction
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with the appropriate input clock frequency, a variety of timing can be
achieved.
• 24 Flip–Flop Stages — Will Count From 20 to 224 MARKING
DIAGRAMS
• Last 16 Stages Selectable By Four–Bit Select Code 16
• 8–Bypass Input Allows Bypassing of First Eight Stages PDIP–16
MC14536BCP
• Set and Reset Inputs P SUFFIX
CASE 648 AWLYYWW
• Clock Inhibit and Oscillator Inhibit Inputs 1
• On–Chip RC Oscillator Provisions
16
• On–Chip Monostable Output Provisions
• Clock Conditioning Circuit Permits Operation With Very Long Rise SOIC–16 14536B
and Fall Times DW SUFFIX
• Test Mode Allows Fast Test Sequence CASE 751G
AWLYYWW
1

SOEIAJ–16
F SUFFIX MC14536B
CASE 966 AWLYWW

YY or Y = Year
WW or W = Work Week
(DC or Transient)
TA Operating Temperature Range – 55 to +125 °C MC14536BCP PDIP–16 2000/Box

Tstg Storage Temperature Range – 65 to +150 °C MC14536BDW SOIC–16 47/Rail
may occur. 1. For ordering information on the EIAJ version of
3. Temperature Derating: the SOIC packages, please contact your local
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C ON Semiconductor representative.

March, 2000 – Rev. 5 MC14536B/D
MC14536B
PIN ASSIGNMENT
SET 1 16 VDD
RESET 2 15 MONO IN
IN 1 3 14 OSC INH
OUT 1 4 13 DECODE
OUT 2 5 12 D
8–BYPASS 6 11 C
CLOCK INH 7 10 B
VSS 8 9 A
BLOCK DIAGRAM
CLOCK INH. RESET SET 8 BYPASS
7 2 1 6
OSC. INHIBIT 14
STAGES STAGES 9 THRU 24

IN1 Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
3 1 THRU 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
4 5
OUT1 OUT2 A 9
B 10
C 11 DECODER
VDD = PIN 16 D 12
VSS = PIN 8
MONOSTABLE DECODE
MONO–IN 15 13
MULTIVIBRATOR OUT
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328
MC14536B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) Pins 4 & 5 5.0 – 0.25 — – 0.25 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 — mAdc
(VOH = 4.6 Vdc) Pin 13 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.020 10 — 300
15 — 20 — 0.030 20 — 600
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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329
MC14536B
Characteristic
Output Rise and Fall Time (Pin 13)
Symbol
tTLH,
ns
Clock to Q1, 8–Bypass (Pin 6) High tPHL
Clock to Q1, 8–Bypass (Pin 6) Low tPLH, µs
tPLH, tPHL = (1.7 ns/pF) CL + 3715 ns tPHL 5.0 — 3.8 7.6
tPLH, tPHL = (0.66 ns/pF) CL + 1467 ns 10 — 1.5 3.0
Clock to Q16 tPLH, µs
tPHL, tPLH = (1.7 ns/pF) CL + 6915 ns tPHL 5.0 — 7.0 14
Reset to Qn tPHL ns
tPHL = (1.7 ns/pF) CL + 1415 ns 5.0 — 1500 3000
tPHL = (0.66 ns/pF) CL + 567 ns 10 — 600 1200
tPHL = (0.5 ns/pF) CL + 425 ns 15 — 450 900
10 200 100 —
15 170 85 —
(50% Duty Cycle) 10 — 3.0 1.5
15 — 5.0 2.0
Clock Rise and Fall Time tTLH, 5.0 —
tTHL 10 No Limit
15
Reset Pulse Width tWH 5.0 1000 500 — ns
10 400 200 —
15 300 150 —
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330
MC14536B
PIN DESCRIPTIONS
INPUTS OSC INHIBIT (Pin 14) — A high level on this pin stops
SET (Pin 1) — A high on Set asynchronously forces the RC oscillator which allows for very low–power standby
Decode Out to a high level. This is accomplished by setting operation. May also be used, in conjunction with an external
an output conditioning latch to a high level while at the same clock, with essentially the same results as the Clock Inhibit
time resetting the 24 flip–flop stages. After Set goes low input.
(inactive), the occurrence of the first negative clock MONO–IN (Pin 15) — Used as the timing pin for the
transition on IN1 causes Decode Out to go low. The on–chip monostable multivibrator. If the Mono–In input is
counter’s flip–flop stages begin counting on the second connected to VSS, the monostable circuit is disabled, and
negative clock transition of IN1. When Set is high, the Decode Out is directly connected to the selected Q output.
on–chip RC oscillator is disabled. This allows for very The monostable circuit is enabled if a resistor is connected
low–power standby operation. between Mono–In and VDD. This resistor and the device’s
RESET (Pin 2) — A high on Reset asynchronously internal capacitance will determine the minimum output
forces Decode Out to a low level; all 24 flip–flop stages are pulse widths. With the addition of an external capacitor to
also reset to a low level. Like the Set input, Reset disables VSS, the pulse width range may be extended. For reliable
the on–chip RC oscillator for standby operation. operation the resistor value should be limited to the range of
IN1 (Pin 3) — The device’s internal counters advance on 5 kΩ to 100 kΩ and the capacitor value should be limited to
the negative–going edge of this input. IN1 may be used as an a maximum of 1000 pf. (See figures 3, 4, 5, and 10).
external clock input or used in conjunction with OUT1 and A, B, C, D (Pins 9, 10, 11, 12) — These inputs select the
OUT2 to form an RC oscillator. When an external clock is flip–flop stage to be connected to Decode Out. (See the truth
used, both OUT1 and OUT 2 may be left unconnected or tables.)
used to drive 1 LSTTL or several CMOS loads.
OUTPUTS
8–BYPASS (Pin 6) — A high on this input causes the first
8 flip–flop stages to be bypassed. This device essentially OUT1, OUT2 (Pin 4, 5) — Outputs used in conjunction
becomes a 16–stage counter with all 16 stages selectable. with IN1 to form an RC oscillator. These outputs are
Selection is accomplished by the A, B, C, and D inputs. (See buffered and may be used for 20 frequency division of an
the truth tables.) external clock.
CLOCK INHIBIT (Pin 7) — A high on this input DECODE OUT (Pin 13) — Output function depends on
disconnects the first counter stage from the clocking source. configuration. When the monostable circuit is disabled, this
This holds the present count and inhibits further counting. output is a 50% duty cycle square wave during free run.
However, the clocking source may continue to run. TEST MODE
Therefore, when Clock Inhibit is brought low, no oscillator The test mode configuration divides the 24 flip–flop
start–up time is required. When Clock Inhibit is low, the stages into three 8–stage sections to facilitate a fast test
counter will start counting on the occurrence of the first sequence. The test mode is enabled when 8–Bypass, Set and
negative edge of the clocking source at IN1. Reset are at a high level. (See Figure 8.)
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331
MC14536B
TRUTH TABLES
Input Input
Stage Selected Stage Selected
8–Bypass D C B A for Decode Out 8–Bypass D C B A for Decode Out
0 0 0 0 0 9 1 0 0 0 0 1
0 0 0 0 1 10 1 0 0 0 1 2
0 0 0 1 0 11 1 0 0 1 0 3
0 0 0 1 1 12 1 0 0 1 1 4
0 0 1 0 0 13 1 0 1 0 0 5
0 0 1 0 1 14 1 0 1 0 1 6
0 0 1 1 0 15 1 0 1 1 0 7
0 0 1 1 1 16 1 0 1 1 1 8
0 1 0 0 0 17 1 1 0 0 0 9
0 1 0 0 1 18 1 1 0 0 1 10
0 1 0 1 0 19 1 1 0 1 0 11
0 1 0 1 1 20 1 1 0 1 1 12
0 1 1 0 0 21 1 1 1 0 0 13
0 1 1 0 1 22 1 1 1 0 1 14
0 1 1 1 0 23 1 1 1 1 0 15
0 1 1 1 1 24 1 1 1 1 1 16
FUNCTION TABLE
Clock OSC Decode
In1 Set Reset Inh Inh Out 1 Out 2 Out
0 0 0 0 No
Change
0 0 0 0 Advance to
next state
X 1 0 0 0 0 1 1
X 0 1 0 0 0 1 0
X 0 0 1 0 — — No
Change
X 0 0 0 1 0 1 No
Change
0 0 0 0 X 0 1 No
Change
1 0 0 0 Advance to
next state
X = Don’t Care
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332
RESET
2 8–BYPASS
6
OSC INHIBIT
14
3 STAGES
STAGES STAGES
T 1 8 T 9 10 THRU 16 17 18 THRU 24
2 THRU 7 15
IN1 23
4 OUT 2 5
333
OUT 1 A 9
S B 10
C C 11 DECODER
Q D 12
MC14536B
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LOGIC DIAGRAM
En R
SET DECODER
1 OUT
7 13
CLOCK
INHIBIT
15 VDD = PIN 16
MONO–IN VSS = PIN 8
MC14536B

(For Circuit Diagram See Figure 11 In Application)
8.0 100
VDD = 15 V VDD = 10 V
50
f AS A FUNCTION

4.0
20 OF RTC
(C = 1000 pF)
0 10
(RS ≈ 2RTC)
10 V 5.0
– 4.0
2.0 f AS A FUNCTION
OF C
– 8.0 1.0 (RTC = 56 kΩ)
5.0 V
0.5 (RS = 120 k)
– 12
– 16 0.1
– 55 – 25 0 25 50 75 100 125 1.0 k 10 k 100 k 1.0 M
*Device Only. RTC, RESISTANCE (OHMS)
TA, AMBIENT TEMPERATURE (°C)*
0.0001 0.001 0.01 0.1
C, CAPACITANCE (µF)
MONOSTABLE CHARACTERISTICS
(For Circuit Diagram See Figure 10 In Application)
100 100
FORMULA FOR CALCULATING tW IN FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS: MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 RX • CX 0.85 tW = 0.00247 RX • CX 0.85
t W, PULSE WIDTH ( µs)
WHERE R IS IN kΩ, CX IN pF. WHERE R IS IN kΩ, CX IN pF.

10 10
RX = 100 kΩ RX = 100 kΩ
50 kΩ 50 kΩ
1.0 10 kΩ 1.0
5 kΩ 10 kΩ
TA = 25°C 5 kΩ TA = 25°C
VDD = 5 V VDD = 10 V
0.1 0.1
1.0 10 100 1000 1.0 10 100 1000
CX, EXTERNAL CAPACITANCE (pF) CX, EXTERNAL CAPACITANCE (pF)
Figure 3. Typical CX versus Pulse Width Figure 4. Typical CX versus Pulse Width
@ VDD = 5.0 V @ VDD = 10 V
100
FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 RX • CX 0.85
WHERE R IS IN kΩ, CX IN pF.
10
RX = 100 kΩ
50 kΩ
1.0
10 kΩ
5 kΩ TA = 25°C
VDD = 15 V
0.1
1.0 10 100 1000
CX, EXTERNAL CAPACITANCE (pF)
Figure 5. Typical CX versus Pulse Width
@ VDD = 15 V
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MC14536B
VDD
0.01 µF
500 µF ID
CERAMIC
SET 20 ns 20 ns
RESET OUT 1
8–BYPASS CL VDD
PULSE IN1 50%
IN1
GENERATOR tWL tWH
C INH SET
MONO IN OUT OUT 1
RESET 90%
OSC INH 2 OUT 50%
CL 8–BYPASS 10%
A PULSE
IN1 tPLH tPHL
B GENERATOR
C INH tTLH tTHL
C DECODE MONO IN OUT
D OUT CL 2
OSC INH
VSS A
B
C DECODE
20 ns 20 ns D OUT CL
90% VSS
50%
10%
50%
DUTY CYCLE
Figure 6. Power Dissipation Test Figure 7. Switching Time Test Circuit and Waveforms
Circuit and Waveform
FUNCTIONAL TEST SEQUENCE VDD
Test function (Figure 8) has been included for the SET

PULSE RESET OUT 1
reduction of test time required to exercise all 24 counter
GENERATOR 8–BYPASS
stages. This test function divides the counter into three IN1
8–stage sections and 255 counts are loaded in each of the C INH
8–stage sections in parallel. All flip–flops are now at a “1”. MONO IN OUT
OSC INH 2
The counter is now returned to the normal 24–stages in
A
series configuration. One more pulse is entered into In1
B
which will cause the counter to ripple from an all “1” state C DECODE
to an all “0” state. D OUT
VSS
Figure 8. Functional Test Circuit
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MC14536B
FUNCTIONAL TEST SEQUENCE

Inputs Outputs Comments
Decade Out
In1 Set Reset 8–Bypass Q1 thru Q24 g are in Reset mode.
All 24 stages
1 0 1 1 0
1 1 1 1 0 Counter is in three 8 stage sections in parallel mode.
0 1 1 1 0 First “1” to “0” transition of clock.
1
0
— 1 1 1 255 “1” to “0” transitions are clocked in the counter.
—
—
0 1 1 1 1 The 255 “1” to “0” transition.
0 0 0 0 1 Counter converted back to 24 stages in series mode.
Set and Reset must be connected together and simultaneously
go from “1” to “0”.
1 0 0 0 1 In1 Switches to a “1”.
0 0 0 0 0 Counter Ripples from an all “1” state to an all “0” state.
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MC14536B
+V
16
6 VDD
8–BYPASS
9 4
A OUT 1
10 B
11 C
12
D
2 OUT 2 5
RESET
14
OSC INH
15
MONO–IN
PULSE 1
SET
GEN. 7
CLOCK INH
3 DECODE OUT 13
PULSE IN1
VSS
GEN.
CLOCK 8
IN1
SET
CLOCK INH
DECODE OUT
POWER UP
NOTE: When power is first applied to the device, Decode Out can be either at a high or low state.
On the rising edge of a Set pulse the output goes high if initially at a low state. The output
remains high if initially at a high state. Because Clock Inh is held high, the clock source on
the input pin has no effect on the output. Once Clock Inh is taken low, the output goes low
on the first negative clock transition. The output returns high depending on the 8–Bypass,
A, B, C, and D inputs, and the clock input period. A 2n frequency division (where n = the
number of stages selected from the truth table) is obtainable at Decode Out. A 20–divided
output of IN1 can be obtained at OUT1 and OUT2.
Figure 9. Time Interval Configuration Using an External Clock, Set,

and Clock Inhibit Functions
(Divide–by–2 Configured)
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MC14536B
+V
16
6 VDD
8–BYPASS
RX 9 4
A OUT 1
10 B
11 C
12
D
PULSE 2 5
RESET OUT 2
GEN. 1
SET
7
CLOCK INH
15
MONO–IN
14
CLOCK INH
3 DECODE OUT 13
CLOCK IN1
VSS
CX 8
IN1
RESET
*tw ≈ .00247 • RX • CX0.85
DECODE OUT tw in µsec

RX in kΩ
CX in pF
*tw
POWER UP
NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Reset
input low enables the chip’s internal counters. After Reset goes low, the 2n/2 negative transition of the clock input causes
Decode Out to go high. Since the Mono–In input is being used, the output becomes monostable. The pulse width of the
output is dependent on the external timing components. The second and all subsequent pulses occur at 2n x (the clock
period) intervals where n = the number of stages selected from the truth table.
Figure 10. Time Interval Configuration Using an External Clock, Reset,

and Output Monostable to Achieve a Pulse Output
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MC14536B
+V
RS
16
6 VDD
8–BYPASS
9 4
A OUT 1
10 B C
11 C
RTC
12
D
PULSE 2 5
RESET OUT 2
GEN. 14
SET
15
CLOCK INH
1
MONO–IN
7
CLOCK INH
3 DECODE OUT 13
IN1
VSS
8
RESET
OUT 1
OUT 2
fosc ^ 2.3 R1tc C

DECODE OUT
Rs ≥ Rtc
F = Hz
tw R = Ohms
POWER UP
C = FARADS
NOTE: This circuit is designed to use the on–chip oscillation function. The oscillator frequency is deter-
mined by the external R and C components. When power is first applied to the device, Decode Out
initializes to a high state. Because this output is tied directly to the Osc–Inh input, the oscillator is
disabled. This puts the device in a low–current standby condition. The rising edge of the Reset pulse
will cause the output to go low. This in turn causes Osc–Inh to go low. However, while Reset is high,
the oscillator is still disabled (i.e.: standy condition). After Reset goes low, the output remains low
for 2n/2 of the oscillator’s period. After the part times out, the output again goes high.
Figure 11. Time Interval Configuration Using On–Chip RC Oscillator and

Reset Input to Initiate Time Interval
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MC14538B
Dual Precision
Retriggerable/Resettable
Monostable Multivibrator
The MC14538B is a dual, retriggerable, resettable monostable

multivibrator. It may be triggered from either edge of an input pulse, http://onsemi.com
and produces an accurate output pulse over a wide range of widths, the
duration and accuracy of which are determined by the external timing MARKING
components, CX and RX. DIAGRAMS
16
Output Pulse Width = (Cx) (Rx) where: PDIP–16
Rx is in k W P SUFFIX MC14538BCP
m CASE 648 AWLYYWW

Cx is in F 1
• Unlimited Rise and Fall Time Allowed on the A Trigger Input SOIC–16
16
14538B
• Pulse Width Range = 10 µs to 10 s D SUFFIX AWLYWW
•
CASE 751B
Latched Trigger Inputs 1
• Separate Latched Reset Inputs TSSOP–16
16
14
• 3.0 Vdc to 18 Vdc Operational Limits DT SUFFIX 538B
• Triggerable from Positive (A Input) or Negative–Going Edge
CASE 948F
1
ALYW
(B–Input) 16
• Capable of Driving Two Low–power TTL Loads or One Low–power 14538B
SOIC–16
Schottky TTL Load Over the Rated Temperature Range DW SUFFIX
• Pin–for–pin Compatible with MC14528B and CD4528B (CD4098) CASE 751G
AWLYYWW
• Use the MC54/74HC4538A for Pulse Widths Less Than 10 µs with
1
Supplies Up to 6 V. 16
SOEIAJ–16
F SUFFIX MC14538B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) AWLYWW
CASE 966
WL or L = Wafer Lot
(DC or Transient) per Pin ORDERING INFORMATION
PD Power Dissipation, 500 mW Device Package Shipping
(8–Second Soldering) MC14538BDT TSSOP–16 96/Rail
may occur.
3. Temperature Derating: MC14538BDW SOIC–16 47/Rail
high–impedance circuit. For proper operation, Vin and Vout should be constrained MC14538BFEL SOEIAJ–16 See Note 1.
to the range VSS v
(Vin or Vout) vVDD. 1. For ordering information on the EIAJ version of
Unused inputs must always be tied to an appropriate logic voltage level (e.g., the SOIC packages, please contact your local

March, 2000 – Rev. 3 MC14538B/D
MC14538B
PIN ASSIGNMENT
VSS 1 16 VDD
CX/RXA 2 15 VSS
RESET A 3 14 CX/RXB
AA 4 13 RESET B
BA 5 12 AB
QA 6 11 BB
QA 7 10 QB
VSS 8 9 QB
BLOCK DIAGRAM
CX RX
VDD
1 2
A
4
Q1 6
B
5 Q1 7
RESET
CX RX
VDD
15 14
A
12
Q2 10
B
11 Q2 9
RESET
13
RX AND CX ARE EXTERNAL COMPONENTS.
VDD = PIN 16
VSS = PIN 8, PIN 1, PIN 15
ONE–SHOT SELECTION GUIDE
100 ns 1 µs 10 µs 100 µs 1 ms 10 ms 100 ms 1s 10 s

MC14528B
MC14536B 23 HR
MC14538B
MC14541B 5 MIN.
MC4538A*
*LIMITED OPERATING VOLTAGE (2 – 6 V)
TOTAL OUTPUT PULSE WIDTH RANGE

RECOMMENDED PULSE WIDTH RANGE
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MC14538B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current, Pin 2 or 14 Iin 15 — ± 0.05 — ± 0.00001 ± 0.05 — ± 0.5 µAdc
Input Current, Other Inputs Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance, Pin 2 or 14 Cin — — — — 25 — — — pF
Input Capacitance, Other Inputs Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
(Per Package) 10 — 10 — 0.010 10 — 300
Q = Low, Q = High 15 — 20 — 0.015 20 — 600
Quiescent Current, Active State IDD 5.0 — 2.0 — 0.04 0.20 — 2.0 mAdc
(Both) (Per Package) 10 — 2.0 — 0.08 0.45 — 2.0
Q = High, Q = Low 15 — 2.0 — 0.13 0.70 — 2.0
Total Supply Current at an external IT 5.0 IT = (3.5 x 10–2) RXCXf + 4CXf + 1 x 10–5 CLf µAdc
load capacitance (CL) and at 10 IT = (8.0 x 10–2) RXCXf + 9CXf + 2 x 10–5 CLf
external timing network (RX, CX) (5.) IT = (1.25 x 10–1) RXCXf + 12CXf + 3 x 10–5 CLf
where: IT in µA (one monostable switching only),
where: CX in µF, CL in pF, RX in k ohms, and
where: f in Hz is the input frequency.
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MC14538B
VDD
Vdc Min
All Types
Typ (7.) Max Unit
tTLH = (1.35 ns/pF) CL + 33 ns 5.0 — 100 200
tTLH = (0.60 ns/pF) CL + 20 ns 10 — 50 100
tTLH = (0.40 ns/pF) CL + 20 ns 15 — 40 80
tTHL = (1.35 ns/pF) CL + 33 ns 5.0 — 100 200
tTHL = (0.60 ns/pF) CL + 20 ns 10 — 50 100
tTHL = (0.40 ns/pF) CL + 20 ns 15 — 40 80
A or B to Q or Q tPHL
Reset to Q or Q ns
Input Rise and Fall Times tr, tf 5 — — 15 µs
Reset 10 — — 5
15 — — 4
B Input 5 — 300 1.0 ms
10 — 1.2 0.1
15 — 0.4 0.05
A Input 5 —
10 No Limit
15
Input Pulse Width tWH, 5.0 170 85 — ns
A, B, or Reset tWL 10 90 45 —
15 80 40 —
Retrigger Time trr 5.0 0 — — ns
10 0 — —
15 0 — —
Output Pulse Width — Q or Q T µs
Refer to Figures 8 and 9
CX = 0.002 µF, RX = 100 kΩ 5.0 198 210 230
10 200 212 232
15 202 214 234
CX = 0.1 µF, RX = 100 kΩ 5.0 9.3 9.86 10.5 ms
10 9.4 10 10.6
15 9.5 10.14 10.7
CX = 10 µF, RX = 100 kΩ 5.0 0.91 0.965 1.03 s
10 0.92 0.98 1.04
15 0.93 0.99 1.06
Pulse Width Match between circuits in 100 5.0 — ± 1.0 ± 5.0 %
the same package. [(T1 – T2)/T1] 10 — ± 1.0 ± 5.0
CX = 0.1 µF, RX = 100 kΩ 15 — ± 1.0 ± 5.0
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MC14538B
OPERATING CONDITIONS
External Timing Resistance
External Timing Capacitance
RX
CX
—
—
5.0
0
—
— No
(8.) kΩ
µF
Limit (9.)
8. The maximum usable resistance RX is a function of the leakage of the capacitor CX, leakage of the MC14538B, and leakage due to board
layout and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 MΩ..
9. If CX > 15 µF, use discharge protection diode per Fig. 11.
VDD VDD
P1
RX
2 (14) ENABLE
+ +
C1 C2
CX Vref1 – Vref2 – R Q 6 (10)
ENABLE OUTPUT
1 (15) LATCH
N1 S Q 7 (9)
VSS CONTROL
4 (12)
A
5 (11)
B
QR QR NOTE: Pins 1, 8 and 15 must
3 (13)
RESET S RESET LATCH R be externally grounded
Figure 1. Logic Diagram

(1/2 of DevIce Shown)
VDD
0.1 µF
500 pF ID
CERAMIC
RX RX′
VSS CX CX′
VSS
Vin CX/RX
A
B Q
CL 20 ns 20 ns
RESET Q VDD
CL 90%
A′ Q′
CL 10%
B′ Q′ Vin 0V
CL
RESET′
VSS
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MC14538B
VDD
INPUT CONNECTIONS
RX RX′ *CL = 50 pF Characteristics Reset A B
CX CX′ tPLH, tPHL, tTLH, tTHL, VDD PG1 VDD
VSS VSS T, tWH, tWL
CX/RX tPLH, tPHL, tTLH, tTHL, VDD VSS PG2
PULSE A
T, tWH, tWL
GENERATOR B Q tPLH(R), tPHL(R), PG3 PG1 PG2
CL tWH, tWL
PULSE RESET Q
GENERATOR CL
A′ Q′ *Includes capacitance of probes, PG1 =
CL wiring, and fixture parasitic.
PULSE B′ Q′
CL NOTE: Switching test waveforms PG2 =
GENERATOR RESET′ for PG1, PG2, PG3 are shown
VSS In Figure 4. PG3 =
Figure 3. Switching Test Circuit
90%
50% 10% 50% VDD
A
tWH tTLH tTHL
tTHL tTLH
B
50% 90% VDD
10%
tWL
tTHL tPHL
RESET
90% VDD
50%
10%
tWL
tPLH tTHL tTLH
T
tPLH tPHL trr
90%
50% 50% 50% 10% 50%
Q
tTLH tTHL
tPHL tPHL tPLH
Q 90%
50% 50% 50% 50%
10%
Figure 4. Switching Test Waveforms

WITH RESPECT TO VALUE AT VDD = 10 V (%)
RELATIVE FREQUENCY OF OCCURRENCE
TA = 25°C
NORMALIZED PULSE WIDTH CHANGE
RX = 100 kΩ 0% POINT PULSE WIDTH RX = 100 kΩ

CX = 0.1 µF VDD = 5.0 V, T = 9.8 ms CX = 0.1 µF
1.0 VDD = 10 V, T = 10 ms 2
VDD = 15 V, T = 10.2 ms
0.8 1
0
0.6 1
0.4 2
0.2
0
–4 –2 0 2 4 5 6 7 8 9 10 11 12 13 14 15
T, OUTPUT PULSE WIDTH (%) VDD, SUPPLY VOLTAGE (VOLTS)
Figure 5. Typical Normalized Distribution Figure 6. Typical Pulse Width Variation as

of Units for Output Pulse Width a Function of Supply Voltage VDD
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MC14538B
1000 FUNCTION TABLE

Inputs Outputs
TOTAL SUPPLY CURRENT ( µA)
RX = 100 kΩ, CL = 50 pF
ONE MONOSTABLE SWITCHING ONLY Reset A B Q Q
100
H H
H L
VDD = 15 V
10 5.0 V H L Not Triggered
10 V H H Not Triggered
H L, H, H Not Triggered
H L L, H, Not Triggered
1.0
L X X L H
X X Not Triggered
0.1
0.001 0.1 1.0 10 100
OUTPUT DUTY CYCLE (%)
Figure 7. Typical Total Supply Current

versus Output Duty Cycle
WITH RESPECT TO 25°C VALUE AT VDD = 10 V (%)
WITH RESPECT TO 25°C VALUE AT VDD = 10 V (%)

RX = 100 kΩ
CX = .002 µF
RX = 100 kΩ 3.0
TYPICAL NORMALIZED ERROR
TYPICAL NORMALIZED ERROR

CX = 0.1 µF VDD = 15 V
2 2.0
1 1.0 VDD = 15 V
VDD = 10 V
0 0
VDD = 5 V VDD = 10 V
–1 – 1.0
–2 – 2.0
VDD = 5.0 V
– 3.0
– 60 – 40 – 20 0 20 40 60 80 100 120 140 – 60 – 40 – 20 0 20 40 60 80 100 120 140

TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)
Figure 8. Typical Error of Pulse Width Figure 9. Typical Error of Pulse Width
Equation versus Temperature Equation versus Temperature
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MC14538B
THEORY OF OPERATION
1 3 4
A
2
RESET
Vref 2 Vref 2 Vref 2 Vref 2

CX/RX Vref 1 Vref 1 Vref 1 Vref 1
T T T
1 Positive edge trigger 4 Positive edge re–trigger (pulse lengthening)

2 Negative edge trigger 5 Positive edge re–trigger (pulse lengthening)
3 Positive edge trigger
Figure 10. Timing Operation
TRIGGER OPERATION RETRIGGER OPERATION

The block diagram of the MC14538B is shown in The MC14538B is retriggered if a valid trigger occurs
Figure 1, with circuit operation following. followed by another valid trigger before the Q output has
As shown in Figure 1 and 10, before an input trigger returned to the quiescent (zero) state. Any retrigger, after the
occurs, the monostable is in the quiescent state with the Q timing node voltage at pin 2 or 14 has begun to rise from
output low, and the timing capacitor CX completely charged Vref 1, but has not yet reached Vref 2, will cause an increase
to VDD. When the trigger input A goes from VSS to VDD in output pulse width T. When a valid retrigger is initiated
(while inputs B and Reset are held to VDD) a valid trigger is , the voltage at CX/RX will again drop to Vref 1 before
recognized, which turns on comparator C1 and N–channel progressing along the RC charging curve toward VDD. The
transistor N1 . At the same time the output latch is set. With Q output will remain high until time T, after the last valid
transistor N1 on, the capacitor CX rapidly discharges toward retrigger.
VSS until Vref1 is reached. At this point the output of
comparator C1 changes state and transistor N1 turns off. RESET OPERATION
Comparator C1 then turns off while at the same time The MC14538B may be reset during the generation of the
comparator C2 turns on. With transistor N1 off, the capacitor output pulse. In the reset mode of operation, an input pulse
CX begins to charge through the timing resistor, RX, toward on Reset sets the reset latch and causes the capacitor to be
VDD. When the voltage across CX equals Vref 2, comparator fast charged to VDD by turning on transistor P1 . When the
C2 changes state, causing the output latch to reset (Q goes voltage on the capacitor reaches Vref 2, the reset latch will
low) while at the same time disabling comparator C2 . This clear, and will then be ready to accept another pulse. It the
ends at the timing cycle with the monostable in the quiescent Reset input is held low, any trigger inputs that occur will be
state, waiting for the next trigger. inhibited and the Q and Q outputs of the output latch will not
In the quiescent state, CX is fully charged to VDD causing change. Since the Q output is reset when an input low level
the current through resistor RX to be zero. Both comparators is detected on the Reset input, the output pulse T can be made
are “off” with total device current due only to reverse significantly shorter than the minimum pulse width
junction leakages. An added feature of the MC14538B is specification.
that the output latch is set via the input trigger without regard POWER–DOWN CONSIDERATIONS
to the capacitor voltage. Thus, propagation delay from Large capacitance values can cause problems due to the
trigger to Q is independent of the value of CX, RX, or the duty large amount of energy stored. When a system containing
cycle of the input waveform.
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MC14538B
the MC14538B is powered down, the capacitor voltage may Dx

discharge from VDD through the standard protection diodes
at pin 2 or 14. Current through the protection diodes should Cx Rx VDD
VSS
be limited to 10 mA and therefore the discharge time of the
VDD supply must not be faster than (VDD). (C) / (10 mA). VDD
For example, if VDD = 10 V and CX = 10 µF, the VDD supply
should discharge no faster than (10 V) x (10 µF) / (10 mA) Q
= 10 ms. This is normally not a problem since power
supplies are heavily filtered and cannot discharge at this rate. Q
When a more rapid decrease of VDD to zero volts occurs, RESET
the MC14538B can sustain damage. To avoid this possibility
use an external clamping diode, DX, connected as shown in
Fig. 11. Figure 11. Use of a Diode to Limit
Power Down Current Surge
CX RX CX RX
RISING–EDGE VDD
VDD
TRIGGER
A Q RISING–EDGE
A Q
TRIGGER
B Q B Q
B = VDD
RESET = VDD RESET = VDD
CX RX CX RX
A = VSS VDD VDD
Q A Q
B Q B Q
FALLING–EDGE
FALLING–EDGE TRIGGER
TRIGGER
RESET = VDD RESET = VDD
Figure 12. Retriggerable Figure 13. Non–Retriggerable

Monostables Circuitry Monostables Circuitry
NC
Q NC
A
B Q NC
CD
VDD
VDD
Figure 14. Connection of Unused Sections
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MC14541B
Programmable Timer
The MC14541B programmable timer consists of a 16–stage binary
counter, an integrated oscillator for use with an external capacitor and
two resistors, an automatic power–on reset circuit, and output control
logic.
Timing is initialized by turning on power, whereupon the power–on
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reset is enabled and initializes the counter, within the specified VDD
range. With the power already on, an external reset pulse can be MARKING
applied. Upon release of the initial reset command, the oscillator will DIAGRAMS
14
oscillate with a frequency determined by the external RC network. The PDIP–14
16–stage counter divides the oscillator frequency (fosc) with the nth P SUFFIX MC14541BCP
AWLYYWW
stage frequency being fosc/2n. CASE 646
1
• Available Outputs 28, 210, 213 or 216 14
• Increments on Positive Edge Clock Transitions SOIC–14
D SUFFIX
14541B
AWLYWW
• Built–in Low Power RC Oscillator (± 2% accuracy over temperature CASE 751A
1
range and ± 20% supply and ± 3% over processing at < 10 kHz) 14
• Oscillator May Be Bypassed if External Clock Is Available (Apply TSSOP–14 14
DT SUFFIX 541B
external clock to Pin 3) CASE 948G ALYW
• External Master Reset Totally Independent of Automatic Reset 1
Operation 14
SOEIAJ–14
• Operates as 2n Frequency Divider or Single Transition Timer F SUFFIX MC14541B
• Q/Q Select Provides Output Logic Level Flexibility CASE 965 AWLYWW
• Reset (auto or master) Disables Oscillator During Resetting to A

1
= Assembly Location
Provide No Active Power Dissipation WL or L = Wafer Lot
• Clock Conditioning Circuit Permits Operation with Very Slow Clock YY or Y = Year
Rise and Fall Times WW or W = Work Week
• Automatic Reset Initializes All Counters On Power Up ORDERING INFORMATION

• Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset Device Package Shipping
Supply Voltage Range = Disabled (Pin 5 = VDD)
Supply Voltage Range = 8.5 Vdc to 18 Vdc with Auto Reset MC14541BCP PDIP–14 2000/Box
Supply Voltage Range = Enabled (Pin 5 = VSS) MC14541BD SOIC–14 55/Rail
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) MC14541BDR2 SOIC–14 2500/Tape & Reel
(DC or Transient) MC14541BF SOEIAJ–14 See Note 1.
Iin Input Current (DC or Transient) ± 10 (per Pin) mA MC14541BFEL SOEIAJ–14 See Note 1.
Iout Output Current (DC or Transient) ± 45 (per Pin) mA 1. For ordering information on the EIAJ version of
TA Ambient Temperature Range – 55 to +125 °C against damage due to high static voltages or electric
TL Lead Temperature 260 °C voltages to this high–impedance circuit. For proper
(8–Second Soldering) operation, Vin and Vout should be constrained to the
(Vin or Vout) VDD.

March, 2000 – Rev. 6 MC14541B/D
MC14541B
PIN ASSIGNMENT
Rtc 1 14 VDD
Ctc 2 13 B
RS 3 12 A
NC 4 11 NC
AR 5 10 MODE
MR 6 9 Q/Q SEL
VSS 7 8 Q
NC = NO CONNECTION
VDD – 55_C 25_C 125_C
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
(VOH = 2.5 Vdc) Source 5.0 – 7.96 — – 6.42 – 12.83 — – 4.49 —
(VOH = 9.5 Vdc) 10 – 4.19 — – 3.38 – 6.75 — – 2.37 —
(VOH = 13.5 Vdc) 15 – 16.3 — – 13.2 – 26.33 — – 9.24 —
(VOL = 0.5 Vdc) 10 4.96 — 4.0 8.0 — 2.8 —
(VOL = 1.5 Vdc) 15 19.3 — 15.6 31.2 — 10.9 —
(Vin = 0)
(Pin 5 is High) 10 — 10 — 0.010 10 — 300
Auto Reset Disabled 15 — 20 — 0.015 20 — 600
Auto Reset Quiescent Current IDDR 10 — 250 — 30 250 — 1500 µAdc
(Pin 5 is low) 15 — 500 — 82 500 — 2000
Supply Current (5.) (6.) ID 5.0 ID = (0.4 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent) 10 ID = (0.8 µA/kHz) f + IDD
15 ID = (1.2 µA/kHz) f + IDD
6. When using the on chip oscillator the total supply current (in µAdc) becomes: IT = ID + 2 Ctc VDD f x 10–3 where ID is in µA, Ctc is in pF,
VDD in Volts DC, and f in kHz. (see Fig. 3) Dissipation during power–on with automatic reset enabled is typically 50 µA @ VDD = 10 Vdc.
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MC14541B
Characteristic
Symbol
tTLH,
ns
Propagation Delay, Clock to Q (28 Output) tPLH µs
tPLH, tPHL = (1.7 ns/pF) CL + 3415 ns tPHL 5.0 — 3.5 10.5
Propagation Delay, Clock to Q (216 Output) tPHL µs
tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns tPLH 5.0 — 6.0 18
tPHL, tPLH = (0.66 ns/pF) CL + 3467 ns 10 — 3.5 10
10 300 100 —
15 225 85 —
Clock Pulse Frequency (50% Duty Cycle) fcl 5.0 — 1.5 0.75 MHz
10 — 4.0 2.0
15 — 6.0 3.0
MR Pulse Width tWH(R) 5.0 900 300 — ns
10 300 100 —
15 225 85 —
Master Reset Removal Time trem 5.0 420 210 — ns
10 200 100 —
15 200 100 —
VDD VDD
PULSE PULSE
RS RS
GENERATOR GENERATOR
AR AR
Q/Q SELECT Q/Q SELECT
MODE Q MODE Q
A CL A CL
B B
MR MR
VSS VSS
(Rtc AND Ctc OUTPUTS ARE LEFT OPEN) 20 ns 20 ns
90% 50%
50%
20 ns 20 ns RS 10%
tPLH tPHL
90% 50%
10% 50% 90%
50%
50% Q 10%
DUTY CYCLE tTLH tTHL
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351
MC14541B
EXPANDED BLOCK DIAGRAM
A 12
B 13
1 OF 4
MUX
8 Q
Rtc 1 210 213 216
8–STAGE 8
Ctc 2 OSC C 2 C 8–STAGE
COUNTER
RS 3 RESET COUNTER
RESET RESET
AUTO RESET POWER–ON

5
RESET
6 10 9
MASTER RESET MODE Q/Q
SELECT
VDD = PIN 14
VSS = PIN 7
FREQUENCY SELECTION TABLE TRUTH TABLE

Number of State
Counter Stages Count
Pin 0 1
A B n 2n
Auto Reset, 5 Auto Reset Auto Reset Disabled
0 0 13 8192
Operating
0 1 10 1024
Master Reset, 6 Timer Operational Master Reset On
1 0 8 256
Q / Q, 9 Output Initially Low Output Initially High
1 1 16 65536 After Reset After Reset
Mode, 10 Single Cycle Mode Recycle Mode
3
TO CLOCK
CIRCUIT
INTERNAL
RESET
2 1
Ctc
RS RTC
Figure 3. Oscillator Circuit Using RC Configuration
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352
MC14541B
8.0 100
VDD = 10 V
VDD = 15 V 50
4.0
f AS A FUNCTION

20
OF RTC
0 10 (C = 1000 pF)
(RS ≈ 2RTC)
10 V 5.0
– 4.0 f AS A FUNCTION
2.0 OF C
– 8.0 (RTC = 56 kΩ)
5.0 V 1.0
(RS = 120 kΩ)
0.5
– 12
– 16 0.1
– 55 – 25 0 25 50 75 100 125 1.0 k 10 k 100 k 1.0 m
TA, AMBIENT TEMPERATURE (°C) RTC, RESISTANCE (OHMS)
0.0001 0.001 0.01 0.1
Figure 4. RC Oscillator Stability C, CAPACITANCE (µF)
Figure 5. RC Oscillator Frequency as a

Function of Rtc and Ctc
With Auto Reset pin set to a “0” the counter circuit is when B is “0”, normal counting is interrupted and the 9th
initialized by turning on power. Or with power already on, counter stage receives its clock directly from the oscillator
the counter circuit is reset when the Master Reset pin is set (i.e., effectively outputting 28).
to a “1”. Both types of reset will result in synchronously The Q/Q select output control pin provides for a choice of
resetting all counter stages independent of counter state. output level. When the counter is in a reset condition and
Auto Reset pin when set to a “1” provides a low power Q/Q select pin is set to a “0” the Q output is a “0”,
operation. correspondingly when Q/Q select pin is set to a “1” the Q
The RC oscillator as shown in Figure 3 will oscillate with output is a “1”.
a frequency determined by the external RC network i.e., When the mode control pin is set to a “1”, the selected
f=
1
2.3 RtcCtc
if (1 kHz v f v 100 kHz) count is continually transmitted to the output. But, with
mode pin “0” and after a reset condition the RS flip–flop (see
Expanded Block Diagram) resets, counting commences,
and RS ≈ 2 Rtc where RS ≥ 10 kΩ and after 2n–1 counts the RS flip–flop sets which causes the
The time select inputs (A and B) provide a two–bit address output to change state. Hence, after another 2n–1 counts the
to output any one of four counter stages (28, 210, 213 and output will not change. Thus, a Master Reset pulse must be
216). The 2n counts as shown in the Frequency Selection applied or a change in the mode pin level is required to reset
Table represents the Q output of the Nth stage of the counter. the single cycle operation.
When A is “1”, 216 is selected for both states of B. However,
DIGITAL TIMER APPLICATION
Rtc When Master Reset (MR) receives a positive pulse, the

1 14 VDD internal counters and latch are reset. The Q output goes high
Ctc
2 13 B and remains high until the selected (via A and B) number of
3 12 A clock pulses are counted, the Q output then goes low and
RS
NC 4 11 N.C. remains low until another input pulse is received.
AR MODE This “one shot” is fully retriggerable and as accurate as the
5 10
MR
6 9
Q/Q
VDD
input frequency. An external clock can be used (pin 3 is the
INPUT clock input, pins 1 and 2 are outputs) if additional accuracy
7 8
OUTPUT is needed.
tMR Notice that a setup time equal to the desired pulse width
output is required immediately following initial power up,
during which time Q output will be high.
t + tMR
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MC14543B
BCD-to-Seven Segment
Latch/Decoder/Driver for
Liquid Crystals
designed for use with liquid crystal readouts, and is constructed with http://onsemi.com
complementary MOS (CMOS) enhancement mode devices. The
circuit provides the functions of a 4–bit storage latch and an 8421 MARKING
BCD–to–seven segment decoder and driver. The device has the DIAGRAMS
capability to invert the logic levels of the output combination. The 16
phase (Ph), blanking (BI), and latch disable (LD) inputs are used to PDIP–16
reverse the truth table phase, blank the display, and store a BCD code, P SUFFIX MC14543BCP
AWLYYWW
respectively. For liquid crystal (LC) readouts, a square wave is applied CASE 648
to the Ph input of the circuit and the electrically common backplane of 1
the display. The outputs of the circuit are connected directly to the 16
segments of the LC readout. For other types of readouts, such as SOIC–16
14543B
light–emitting diode (LED), incandescent, gas discharge, and D SUFFIX AWLYWW
fluorescent readouts, connection diagrams are given on this data sheet. CASE 751B
Applications include instrument (e.g., counter, DVM etc.) display 1
driver, computer/calculator display driver, cockpit display driver, and 16
various clock, watch, and timer uses. SOEIAJ–16
F SUFFIX MC14543B
• Latch Storage of Code CASE 966 AWLYWW
• Blanking Input 1
• Readout Blanking on All Illegal Input Combinations
• Direct LED (Common Anode or Cathode) Driving Capability WL or L = Wafer Lot
• Supply Voltage Range = 3.0 V to 18 V YY or Y = Year
• Capable of Driving 2 Low–power TTL Loads, 1 Low–power Schottky WW or W = Work Week
TTL Load or 2 HTL Loads Over the Rated Temperature Range

• Pin–for–Pin Replacement for CD4056A (with Pin 7 Tied to VSS). ORDERING INFORMATION
• Chip Complexity: 207 FETs or 52 Equivalent Gates
Vin Input Voltage Range, All Inputs – 0.5 to VDD + 0.5 V
Iin DC Input Current per Pin ± 10 mA MC14543BF SOEIAJ–16 See Note 1.
PD Power Dissipation, 500 mW MC14543BFEL SOEIAJ–16 See Note 1.

TA Operating Temperature Range – 55 to +125 °C the SOIC packages, please contact your local
IOHmax Maximum Continuous Output 10 mA This device contains protection circuitry to guard
IOLmax Drive Current (Source or Sink) (per Output) against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap-
POHmax Maximum Continuous Output 70 mW
POLmax Power (Source or Sink) (4.) (per Output)
voltages to this high–impedance circuit. For proper
2. Maximum Ratings are those values beyond which damage to the device operation, Vin and Vout should be constrained to the
may occur. range VSS v v
(Vin or Vout) VDD.
3. Temperature Derating: Unused inputs must always be tied to an appropriate
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C logic voltage level (e.g., either VSS or VDD). Unused out-
4. POHmax = IOH (VOH – VDD) and POLmax = IOL (VOL – VSS) puts must be left open.

March, 2000 – Rev. 3 MC14543B/D
MC14543B
PIN ASSIGNMENT
LD 1 16 VDD
C 2 15 f
B 3 14 g
D 4 13 e
A 5 12 d
PH 6 11 c
BI 7 10 b
VSS 8 9 a
TRUTH TABLE
Inputs Outputs
LD BI Ph* D C B A a b c d e f g Display
X 1 0 X X X X 0 0 0 0 0 0 0 Blank
1 0 0 0 0 0 0 1 1 1 1 1 1 0 0
1 0 0 0 0 0 1 0 1 1 0 0 0 0 1
1 0 0 0 0 1 0 1 1 0 1 1 0 1 2
1 0 0 0 0 1 1 1 1 1 1 0 0 1 3
1 0 0 0 1 0 0 0 1 1 0 0 1 1 4
1 0 0 0 1 0 1 1 0 1 1 0 1 1 5
1 0 0 0 1 1 0 1 0 1 1 1 1 1 6
1 0 0 0 1 1 1 1 1 1 0 0 0 0 7
1 0 0 1 0 0 0 1 1 1 1 1 1 1 8
1 0 0 1 0 0 1 1 1 1 1 0 1 1 9
1 0 0 1 0 1 0 0 0 0 0 0 0 0 Blank
1 0 0 1 0 1 1 0 0 0 0 0 0 0 Blank
1 0 0 1 1 0 0 0 0 0 0 0 0 0 Blank
1 0 0 1 1 0 1 0 0 0 0 0 0 0 Blank
1 0 0 1 1 1 0 0 0 0 0 0 0 0 Blank
1 0 0 1 1 1 1 0 0 0 0 0 0 0 Blank
0 0 0 X X X X ** **
† † † † Inverse of Output Display
Combinations as above
Above
X = Don’t care
† = Above Combinations
* = For liquid crystal readouts, apply a square wave to Ph
For common cathode LED readouts, select Ph = 0
For common anode LED readouts, select Ph = 1
** = Depends upon the BCD code previously applied when LD = 1
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355
MC14543B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (5.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 0.5 Vdc) 10 — — — – 10.1 — — —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 9.5 Vdc) 10 — — — 10.1 — — —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4
Iout = 0 µA 15 — 20 — 0.015 20 — 600
buffers switching)
Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.
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356
MC14543B
Output Rise Time

tTLH
VDD Min Typ Max Unit
ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 100 200
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 50 100
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 40 80
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTHL = (0.55 ns/pF) CL + 12.5 ns 15 — 40 80
Turn–Off Delay Time tPLH ns
tPLH = (1.7 ns/pF) CL + 520 ns 5.0 — 605 1210
tPLH = (0.66 ns/pF) CL + 217 ns 10 — 250 500
tPLH = (0.5 ns/pF) CL + 160 ns 15 — 185 370
Turn–On Delay Time tPHL ns
tPHL = (1.7 ns/pF) CL + 420 ns 5.0 — 505 1650
tPHL = (0.66 ns/pF) CL + 172 ns 10 — 205 660
tPHL = (0.5 ns/pF) CL + 130 ns 15 — 155 495
Setup Time tsu 5.0 350 — ns
10 450 —
15 500 —
Hold Time th 5.0 40 — ns
10 30 —
15 20 —
Latch Disable Pulse Width (Strobing Data) tWH 5.0 250 125 — ns
10 100 50 —
15 80 40 —
LOGIC DIAGRAM
BI 7
VDD = PIN 16
VSS = PIN 8
9 a
A 5
10 b
B 3 11 c
12 d
13 e
C 2
15 f
14 g
D 4
LD 1 PHASE 6
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357
MC14543B
0 24
VDD = 5.0 Vdc VDD = 15 Vdc

POHmax = 70 mWdc
IOH, SOURCE CURRENT (mAdc)
IOL , SINK CURRENT (mAdc)

– 6.0 18
VDD = 10 Vdc VDD = 10 Vdc

– 12 12
– 18 6.0
VDD = 15 Vdc VDD = 5.0 Vdc POLmax = 70 mWdc
VSS = 0 Vdc VSS = 0 Vdc
– 24 0
– 16 – 12 – 8.0 – 4.0 0 0 4.0 8.0 12 16
(VOH – VDD), SOURCE DEVICE VOLTAGE (Vdc) (VOL – VSS), SINK DEVICE VOLTAGE (Vdc)

Characteristics Characteristics
(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high.

20 ns 20 ns
VDD
C 90%
50%
10% VSS
tPHL tPLH
VOH
90% 50%
g 10% VOL
tTHL tTLH
(b) Inputs D, Ph, and BI low, and Inputs A and B high.

20 ns
VDD
LD 90%
50%
10% VSS
tsu
Inputs BI and Ph low, and Inputs D and LD high. th
VDD
f in respect to a system clock. C 50% 50%
VSS
VOH
20 ns 20 ns g
VDD VOL
A, B, AND C 90% 50%
10% 1 VSS
2f (c) Data DCBA strobed into latches
50% DUTY CYCLE
VDD
VOH LD 50%
ANY OUTPUT VSS
VOL tWH
Figure 3. Dynamic Power Dissipation Figure 4. Dynamic Signal Waveforms

Signal Waveforms
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358
MC14543B
LIQUID CRYSTAL (LC) READOUT INCANDESCENT READOUT
APPROPRIATE
MC14543B ONE OF SEVEN SEGMENTS VOLTAGE
OUTPUT
Ph COMMON
BACKPLANE
MC14543B
SQUARE WAVE OUTPUT
(VSS TO VDD) Ph
VSS
LIGHT EMITTING DIODE (LED) READOUT GAS DISCHARGE READOUT

APPROPRIATE
VDD VOLTAGE
COMMON COMMON
CATHODE LED ANODE LED
MC14543B
OUTPUT
Ph
MC14543B
OUTPUT
MC14543B
Ph
VSS OUTPUT
Ph
VDD
NOTE: Bipolar transistors may be added for gain (for VDD v 10 V or Iout ≥ 10 mA). VSS
CONNECTIONS TO SEGMENTS
a
f g b
e c
d
VDD = PIN 16
VSS = PIN 8
DISPLAY
0 1 2 3 4 5 6 7 8 9
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359
MC14549B, MC14559B
Successive Approximation
Registers
The MC14549B and MC14559B successive approximation
registers are 8–bit registers providing all the digital control and storage
necessary for successive approximation analog–to–digital conversion
systems. These parts differ in only one control input. The Master Reset http://onsemi.com
(MR) on the MC14549B is required in the cascaded mode when more
than 8 bits are desired. The Feed Forward (FF) of the MC14559B is
used for register shortening where End–of–Conversion (EOC) is MARKING
required after less than eight cycles. DIAGRAMS
Applications for the MC14549B and MC14559B include 16
analog–to–digital conversion, with serial and parallel outputs. PDIP–16
P SUFFIX MC145XXBCP
• Totally Synchronous Operation CASE 648 AWLYYWW
• Single Supply Operation
• Serial Output
• Retriggerable
16
• Compatible with a Variety of Digital and Analog Systems such as the SOIC–16 145XXB
MC1408 8–Bit D/A Converter DW SUFFIX
• All Control Inputs Positive–Edge Triggered CASE 751G
AWLYYWW
• Capable of Driving 2 Low–Power TTL Loads, 1 Low–Power Schottky 1
TTL Load or 2 HTL Loads Over the Rated Temperature Range

• Chip Complexity: 488 FETs or 122 Equivalent Gates
WL or L = Wafer Lot
YY or Y = Year
Vin Input Voltage Range, All Inputs – 0.5 to VDD + 0.5 V
Iin DC Input Current, per Pin ±10 mA Device Package Shipping

PD Power Dissipation, 500 mW MC14549BCP PDIP–16 25/Rail
Tstg Storage Temperature Range – 65 to +150 °C MC14559BCP PDIP–16 25/Rail
1. Maximum Ratings are those values beyond which damage to the device MC14559BDWR2 SOIC–16 1000/Tape & Reel
may occur.
either VSS or VDD).

March, 2000 – Rev. 3 MC14549B/D
MC14549B, MC14559B
PIN ASSIGNMENT
Q4 1 16 VDD
Q5 2 15 Q3
Q6 3 14 Q2
Q7 4 13 Q1
Sout 5 12 Q0
D 6 11 EOC
C 7 10 *
VSS 8 9 SC
*For MC14549B Pin 10 is MR input.

For MC14559B Pin 10 is FF input.
TRUTH TABLES
MC14549B MC14559B
SC SC(t–1) MR MR(t–1) Clock Action SC SC(t–1) EOC Clock Action
X X X X None X X X None
X X 1 X Reset 1 0 0 Start
1 0 0 0 Start Conversion
Conversion X 1 0 Continue
1 X 0 1 Start Conversion
Conversion 0 0 0 Continue
1 1 0 0 Continue Conversion
Conversion 0 X 1 Retain
0 X 0 X Continue Conversion
Previous Result
Operation 1 X 1 Start
X = Don’t Care t–1 = State at Previous Clock Conversion
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361
MC14549B, MC14559B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage (3.) “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
(VOL = 0.5 Vdc) Q Outputs 10 3.2 — 2.6 4.5 — 1.8 —
(VOL = 1.5 Vdc) 15 8.4 — 6.8 17.6 — 4.8 —
(VOL = 0.4 Vdc) Sink 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) Pin 5, 11 only 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Per Package) 10 — 10 — 0.010 10 — 300
(Clock = 0 V, 15 — 20 — 0.015 20 — 600
Other Inputs = VDD
or 0 V, Iout = 0 µA)
buffers switching)
Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL = 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.
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362
MC14549B, MC14559B
Output Rise Time

tTLH
VDD Min Typ Max Unit
ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 180
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Clock to Q tPHL
Clock to Sout
Clock to EOC
SC, D, FF or MR Setup Time tsu 5.0 250 125 — ns
10 100 50 —
15 80 40 —
10 270 135 —
15 200 100 —
Pulse Width — D, SC, FF or MR tWH 5.0 500 250 — ns
10 200 100 —
15 160 80 —
Clock Rise and Fall Time tTLH, 5.0 — 15 µs
tTHL 10 — 1.0
15 — — 0.5
10 — 3.0 1.5
15 — 4.0 2.0
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363
MC14549B, MC14559B
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
VDD
Q7
Q6
C CL
Q5
CL
Q4
SC CL
PROGRAMMABLE Q3
PULSE CL
Q2
GENERATOR FF(MR) CL
Q1
CL
Q0 CL
D
EOC
CL
Sout CL
CL 1
VSS fcl
tWH(cl)
50%
C
tsu
50%
SC
tsu tsu tWH(D)
D
50%
tPLH tPHL
50% 90% 10%
Q7
tTLH tTHL tPLH
50% 90%
Sout 10%
tTLH
NOTE: Pin 10 = VSS
TIMING DIAGRAM
CLOCK
SC
D
Q7
ÉÉ
ÉÉ
ÉÉ
Q6
ÉÉ
Q5
ÉÉ
Q4
ÉÉ
Q3
ÉÉ
Q2
ÉÉ
Q1
ÉÉ
Q0
ÉÉ
EOC
ÉÉ
Sout INH Q7 Q6 INH Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q8* INH
— Don’t care condition

INH — Indicates Serial Out is inhibited low.
* — Q8 is ninth–bit of serial information available from 8–bit register.
NOTE: Pin 10 = VSS
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364
MC14549B, MC14559B
Both the MC14549B and MC14559B can be operated in conversion, tie Q1 to FF; the part will respond as shown in
either the “free run” or “strobed operation” mode for the timing diagram less two bit times. Not that Q1 and Q0
conversion schemes with any number of bits. Reliable will still operate and must be disregarded.
cascading and/or recirculating operation can be achieved if For 8–bit operation, FF is tied to VSS.
the End of Convert (EOC) output is used as the controlling For applications with more than 8 but less than 16 bits, use
function, since with EOC = 0 (and with SC = 1 for the basic connections shown in Figure 1. The FF input of the
MC14549B but either 1 or 0 for MC14559B) no stable state MC14559B is used to shorten the setup. Tying FF directly
exists under continual clocked operation. The MC14559B to the least significant bit used in the MC14559B allows
will automatically recirculate after EOC = 1 during EOC to provide the cascading signal, and results in smooth
externally strobed operation, provided SC = 1. transition of serial information from the MC14559B to the
All data and control inputs for these devices are triggered MC14549B. The Serial Out (Sout) inhibit structure of the
into the circuit on the positive edge of the clock pulse. MC14559B remains inactive one cycle after EOC goes high,
Operation of the various terminals is as follows: while Sout of the MC14549B remains inhibited until the
C = Clock — A positive–going transition of the Clock is second clock cycle of its operation.
required for data on any input to be strobed into the circuit. Qn = Data Outputs — After a conversion is initiated the
SC = Start Convert — A conversion sequence is initiated Q’s on succeeding cycles go high and are then conditionally
on the positive–going transition of the SC input on reset dependent upon the state of the D input. Once
succeeding clock cycles. conditionally reset they remain in the proper state until the
D = Data in — Data on this input (usually from a circuit is either reset or reinitiated.
comparator in A/D applications) is also entered into the EOC = End of Convert — This output goes high on the
circuit on a positive–going transition of the clock. This input negative–going transition of the clock following FF = 1 (for
is Schmitt triggered and synchronized to allow fast response the MC14559B) or the conditional reset of Q0. This allows
and guaranteed quality of serial and parallel data. settling of the digital circuitry prior to the End of Conversion
MR = Master Reset (MC14549B Only) — Resets all indication. Therefore either level or edge triggering can
output to 0 on positive–going transitions of the clock. If indicate complete conversion.
removed while SC = 0, the circuit will remain reset until SC Sout = Serial Out — Transmits conversion in serial
= 1. This allows easy cascading of circuits. fashion. Serial data occurs during the clock period when the
FF = Feed Forward (MC14559B Only) — Provides corresponding parallel data bit is conditionally reset. Serial
register shortening by removing unwanted bits from a Out is inhibited on the initial period of a cycle, when the
system. circuit is reset, and on the second cycle after EOC goes high.
For operation with less than 8 bits, tie the output following This provides efficient operation when cascaded.
the least significant bit of the circuit to EOC. E.g., for a 6–bit
FROM A/D EXTERNAL 1/4 MC14001

COMPARATOR CLOCK
SERIAL OUT
(CONTINUAL
UPDATE EVERY
D Sout D Sout
C C 13 CLOCK CYCLES)
SC MC14559B SC MC14549B
* FF MR
Q7 Q6 Q5 Q4 •• Q0 EOC Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC
** {
NC
MSB LSB
TO D/A AND PARALLEL DATA
TO D/A AND
PARALLEL DATA
FREE RUN MODE
EXTERNAL STROBE
* FF allows EOC to activate as if in 4–stage register.
** Cascading using EOC guaranteed; no stable unfunctional state.
†Completion of conversion automatically re–initiates cycle in free run mode.
Figure 1. 12–Bit Conversion Scheme
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365
MC14549B, MC14559B
Externally Controlled 6–Bit ADC (Figure 2) Continuously Cycling 12–Bit ADC (Figure 4)
Several features are shown in this application: Because each successive approximation register (SAR)
• Shortening of the register to six bits by feeding the has a capability of handling only an eight–bit word, two
seventh output bit into the FF input. must be cascaded to make an ADC with more than eight bits.
• Continuous conversion, if a continuous signal is applied When it is necessary to cascade two SAR’s, the second
to SC. SAR must have a stable resettable state to remain in while
• Externally controlled updating (the start pulse must be awaiting a subsequent start signal. However, the first stage
shorter than the conversion cycle). must not have a stable resettable state while recycling,
• The EOC output indicating that the parallel data are valid because during switch–on or due to outside influences, the
and that the serial output is complete. first stage has entered a reset state, the entire ADC will
remain in a stable non–functional condition.
Continuously Cycling 8–Bit ADC (Figure 3) This 12–bit ADC is continuously recycling. The serial as
This ADC is running continuously because the EOC well as the parallel outputs are updated every thirteenth
signal is fed back to the SC input, immediately initiating a clock pulse. The EOC pulse indicates the completion of the
new cycle on the next clock pulse. 12–bit conversion cycle, the end of the serial output word,
and the validity of the parallel data output.
C
SC
MC14559B Sout
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC
TO DAC
Figure 2. Externally Controlled 6–Bit ADC
C
SC
MC14559B Sout
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC
TO DAC
Figure 3. Continuously Cycling 8–Bit ADC
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366
MC14549B, MC14559B
Sout
C Sout C
SC SC Sout
MC14559B MC14549B
MR
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC
TO DAC TO DAC
EOC
Figure 4. Continuously Cycling 12–Bit ADC
Externally Controlled 12–Bit ADC (Figure 5) Additional Motorola Parts for Successive
In this circuit the external pulse starts the first SAR and Approximation ADC
simultaneously resets the cascaded second SAR. When Q4 Monolithic digital–to–analog converters — The
of the first SAR goes high, the second SAR starts MC1408/1508 converter has eight–bit resolution and is
conversion, and the first one stops conversion. EOC available with 6, 7, and 8–bit accuracy. The
indicates that the parallel data are valid and that the serial amplifier–comparator block — The MC1407/1507
output is complete. Updating the output data is started with contains a high speed operational amplifier and a high speed
every external control pulse. comparator with adjustable window.
With these two linear parts it is possible to construct
SA–ADCs with an accuracy of up to eight bits, using as the
register one MC14549B or one MC14559B. An additional
CMOS block will be necessary to generate the clock
frequency.
Additional information on successive approximation
ADC is found in Motorola Application Note AN–716.
C Sout C
SC SC Sout
MC14559B MC14549B
MR
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC
TO DAC TO DAC
EOC Sout
Figure 5. Externally Controlled 12–Bit ADC
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367
MC14551B
Quad 2-Channel Analog

Multiplexer/Demultiplexer
The MC14551B is a digitally–controlled analog switch. This device
implements a 4PDT solid state switch with low ON impedance and
very low OFF Leakage current. Control of analog signals up to the
complete supply voltage range can be achieved. http://onsemi.com
• Triple Diode Protection on All Control Inputs

MARKING
DIAGRAMS
• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V
Note: VEE must be VSS v PDIP–16
16
• Linearized Transfer Characteristics P SUFFIX MC14551BCP

AWLYYWW
• Low Noise — 12 nV√Cycle, f ≥ 1.0 kHz typical CASE 648
• For Low RON, Use The HC4051, HC4052, or HC4053 High–Speed

1
CMOS Devices 16
• Switch Function is Break Before Make SOIC–16
14551B
D SUFFIX AWLYWW
CASE 751B
1
MAXIMUM RATINGS (2.) 16

F SUFFIX MC14551B
VDD DC Supply Voltage Range – 0.5 to + 18.0 V CASE 966 AWLYWW
(Referenced to VEE, VSS ≥ VEE)
1
Vin, Vout Input or Output Voltage (DC or – 0.5 to VDD + 0.5 V
Transient) (Referenced to VSS for A = Assembly Location
Control Input & VEE for Switch I/O) WL or L = Wafer Lot
Iin Input Current (DC or Transient), ± 10 mA YY or Y = Year
per Control Pin WW or W = Work Week
Isw Switch Through Current ± 25 mA

PD Power Dissipation, per Package (3.) 500 mW ORDERING INFORMATION
TA Ambient Temperature Range – 55 to + 125 _C Device Package Shipping
Tstg Storage Temperature Range – 65 to + 150 _C MC14551BCP PDIP–16 2000/Box
TL Lead Temperature 260 _C MC14551BD SOIC–16 48/Rail
v v
to the range VSS (Vin or Vout) VDD for control inputs and VEE ≤ (Vin or Vout) ≤
VDD for Switch I/O.
either VSS, VEE or VDD). Unused outputs must be left open.

March, 2000 – Rev. 3 MC14551B/D
MC14551B
PIN ASSIGNMENT
W1 1 16 VDD
X0 2 15 W0
X1 3 14 W
X 4 13 Z
Y 5 12 Z1
Y0 6 11 Z0
VEE 7 10 Y1
VSS 8 9 CONTROL
9 CONTROL
W 14
15 W0
1 W1 X 4
2 X0 COMMONS
SWITCHES 3 X1 OUT/IN
IN/OUT 6 Y0 Y 5
10 Y1
11 Z0 Z 13
12 Z1
VDD = Pin 16 Control ON

VSS = Pin 8 0 W0 X0 Y0 Z0
VEE = Pin 7
1 W1 X1 Y1 Z1
NOTE: Control Input referenced to VSS, Analog Inputs and

Outputs reference to VEE. VEE must be VSS. v
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MC14551B
Characteristic Symbol VDD Test Conditions

– 55_C
Min Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit

Power Supply Voltage VDD — VDD – 3.0 ≥ VSS ≥ 3.0 18 3.0 — 18 3.0 18 V
Range VEE
Quiescent Current Per IDD 5.0 Control Inputs: Vin = — 5.0 — 0.005 5.0 — 150 µA
Package 10 VSS or VDD, — 10 — 0.010 10 — 300
15 Switch I/O: VEE v VI/O — 20 — 0.015 20 — 600
v VDD, and ∆Vswitch
v 500 mV (5.)
Total Supply Current ID(AV) 5.0 TA = 25_C only (The µA
Quiescent, Per Package) 15 (Vin – Vout)/Ron, is
not included.)
CONTROL INPUT (Voltages Referenced to VSS)
Low–Level Input Voltage VIL 5.0 Ron = per spec, — 1.5 — 2.25 1.5 — 1.5 V
10 Ioff = per spec — 3.0 — 4.50 3.0 — 3.0
15 — 4.0 — 6.75 4.0 — 4.0
High–Level Input Voltage VIH 5.0 Ron = per spec, 3.5 — 3.5 2.75 — 3.5 — V
10 Ioff = per spec 7.0 — 7.0 5.50 — 7.0 —
15 11 — 11 8.25 — 11 —
Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µA
SWITCHES IN/OUT AND COMMONS OUT/IN — W, X, Y, Z (Voltages Referenced to VEE)
Peak Voltage Into or Out
of the Switch
Output Offset Voltage VOO — Vin = 0 V, No Load — — — 10 — — — µV
ON Resistance Ron 5.0 ∆Vswitchv 500 mV (5.), — 800 — 250 1050 — 1200 Ω
10 Vin = VIL or VIH — 400 — 120 500 — 520
15 (Control), and Vin = 220 — 80 280 — 300
0 to VDD (Switch)
∆ON Resistance Between ∆Ron 5.0 — 70 — 25 70 — 135 Ω
Any Two Channels 10 — 50 — 10 50 — 95
Off–Channel Leakage Ioff 15 Vin = VIL or VIH — ± 100 — ± 0.05 ± 100 — ± 1000 nA
Channel or Any One
Channel
Capacitance, Switch I/O CI/O — Switch Off — — — 10 — — — pF
Capacitance, Common O/I CO/I — — — — 17 — — — pF
Capacitance, Feedthrough CI/O — Pins Not Adjacent — — — 0.15 — — — pF
(Channel Off) — Pins Adjacent — — — 0.47 — — —
5. For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
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370
MC14551B
v
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C, VEE
VSS)
VDD – VEE
Propagation Delay Times tPLH, tPHL ns
Switch Input to Switch Output (RL = 10 kΩ)
tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns 5.0 — 35 90
tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns 15 — 12 30
Control Input to Output (RL = 10 kΩ) tPLH, tPHL ns
VEE = VSS (Figure 4) 5.0 — 350 875
10 — 140 350
15 — 100 250
Second Harmonic Distortion — 10 — 0.07 — %
RL = 10 kΩ, f = 1 kHz, Vin = 5 Vp–p
Bandwidth (Figure 5) BW 10 — 17 — MHz
RL = 1 kΩ, Vin = 1/2 (VDD – VEE) p–p,
20 Log (Vout / Vin) = – 3 dB, CL = 50 pF
Off Channel Feedthrough Attenuation, Figure 5 — 10 — – 50 — dB
fin = 55 MHz
Channel Separation (Figure 6) — 10 — – 50 — dB
fin = 3 MHz
Crosstalk, Control Input to Common O/I, Figure 7 — 10 — 75 — mV
R1 = 1 kΩ, RL = 10 kΩ,
Control tr = tf = 20 ns
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371
MC14551B
VDD
VDD VDD
IN/OUT OUT/IN
VEE
VDD
LEVEL
CONVERTED
IN/OUT OUT/IN
CONTROL
CONTROL
VEE
Figure 1. Switch Circuit Schematic
16 VDD
CONTROL 9 LEVEL
CONTROL
CONVERTER
8 VSS 7 VEE
W0 15
14 W
W1 1
X0 2
4 X
X1 3
Y0 6
5 Y
Y1 10
Z0 11
13 Z
Z1 12
Figure 2. MC14551B Functional Diagram
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372
MC14551B
TEST CIRCUITS
ON SWITCH
CONTROL
PULSE
SECTION
GENERATOR
OF IC CONTROL Vout
LOAD
V RL CL
SOURCE
VDD VEE VEE VDD
Figure 3. ∆V Across Switch Figure 4. Propagation Delay Times,

Control to Output
Control input used to turn ON or OFF

the switch under test.
RL
ON
CONTROL Vout CONTROL
RL CL = 50 pF OFF
Vout
RL CL = 50 pF
Vin
VDD – VEE VDD – VEE Vin
2 2

Feedthrough Attenuation (Adjacent Channels Used for Setup)

VDD
VEE
CONTROL
SECTION OTHER
CONTROL Vout
OF IC CHANNEL(S) VEE
RL CL = 50 pF VDD
R1
VEE
VDD
Figure 7. Crosstalk, Control Input Figure 8. Off Channel Leakage

to Common O/I
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 kΩ
VDD RANGE X/Y
PLOTTER
VEE = VSS
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373
MC14551B

350 350
300 300
RON, “ON” RESISTANCE (OHMS)

250 250
200 200
150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
– 55°C
50 – 55°C 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10
Figure 10. VDD @ 7.5 V, VEE @ – 7.5 V Figure 11. VDD @ 5.0 V, VEE @ – 5.0 V
700 350
TA = 25°C
600 300
500 250 VDD = 2.5 V
400 200
300 150
5.0 V
TA = 125°C
200 100 7.5 V
25°C
100 – 55°C 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10
Figure 12. VDD @ 2.5 V, VEE @ – 2.5 V Figure 13. Comparison at 25_C, VDD @ – VEE
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374
MC14551B
Figure A illustrates use of the on–chip level converter margin at each peak. If voltage transients above VDD and/or
detailed in Figure 2. The 0–to–5 volt Digital Control signal below VEE are anticipated on the analog channels, external
is used to directly control a 9 Vp–p analog signal. diodes (Dx) are recommended as shown in Figure B. These
The digital control logic levels are determined by VDD diodes should be small signal types able to absorb the
and VSS. The VDD voltage is the logic high voltage; the VSS maximum anticipated current surges during clipping.
high at the control inputs; VSS = GND = 0 V = logic low. VDD and VEE is 18.0 volts. Most parameters are specified
The maximum analog signal level is determined by VDD up to 15 volts which is the recommended maximum
and VEE. The VDD voltage determines the maximum difference between VDD and V EE.
recommended peak above VSS. The VEE voltage Balanced supplies are not required. However, V SS must
determines the maximum swing below VSS. For the be greater than or equal to VEE. For example, VDD =
example, VDD – VSS = 5 volt maximum swing above VSS; + 10 volts, VSS = + 5 volts, and VEE = – 3 volts is acceptable.
VSS – VEE = 5 volt maximum swing below VSS. The See the table below.
example shows a ± 4.5 volt signal which allows a 1/2 volt
+5 V –5 V
VDD VSS VEE

+ 4.5 V
ANALOG SIGNAL I/O 9 Vp–p
COMMON
GND
O/I ANALOG SIGNAL
EXTERNAL MC14551B
CMOS 0–TO–5 V DIGITAL
CONTROL – 4.5 V
DIGITAL CONTROL SIGNAL
CIRCUITRY
VDD VDD
Dx Dx
SWITCH COMMON
I/O O/I
Dx Dx
VEE VEE
Figure B. External Schottky or Germanium Clipping Diodes
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
POSSIBLE SUPPLY CONNECTIONS
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
VDD ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
VSS VEE
Control Inputs
Logic High/Logic Low Maximum Analog Signal Range
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
In Volts In Volts In Volts In Volts In Volts
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
+8 0 –8 + 8/0 + 8 to – 8 = 16 Vp–p
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
+5 0 – 12 + 5/0 + 5 to – 12 = 17 Vp–p
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
+5 0 0 + 5/0 + 5 to 0 = 5 Vp–p
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
+5
ÎÎÎÎÎÎÎ
0 –5 + 5/0 + 5 to – 5 = 10 Vp–p
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
+ 10
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ –5 + 10/ + 5 + 10 to – 5 = 15 Vp–p
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375
MC14553B
3-Digit BCD Counter

The MC14553B 3–digit BCD counter consists of 3 negative edge
triggered BCD counters that are cascaded synchronously. A quad latch
at the output of each counter permits storage of any given count. The
information is then time division multiplexed, providing one BCD
number or digit at a time. Digit select outputs provide display control.
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All outputs are TTL compatible.
An on–chip oscillator provides the low–frequency scanning clock
which drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays, MARKING
digital panel meters, and as a building block for general logic DIAGRAMS
16
applications. PDIP–16
• TTL Compatible Outputs P SUFFIX MC14553BCP
AWLYYWW
• On–Chip Oscillator
CASE 648
1
• Cascadable
• Clock Disable Input
• Pulse Shaping Permits Very Slow Rise Times on Input Clock 16
• Output Latches 14553B

SOIC–16
• Master Reset DW SUFFIX
CASE 751G
AWLYYWW
1
Symbol Parameter Value Unit A = Assembly Location
WL or L = Wafer Lot
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V WW or W = Work Week
(DC or Transient)
Iin Input Current ±10 mA
Iout Output Current +20 mA
(DC or Transient) per Pin Device Package Shipping
PD Power Dissipation, 500 mW MC14553BCP PDIP–16 25/Rail

may occur.

March, 2000 – Rev. 3 MC14553B/D
MC14553B
BLOCK DIAGRAM
4 3
CIA CIB Q0 9
12 CLOCK Q1 7
Q2 6
10 LE
Q3 5
O.F. 14
11 DIS
DS1 2
DS2 1
13 MR
DS3 15
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Inputs
Master
Reset Clock Disable LE Outputs
0 0 0 No Change
0 0 0 Advance
0 X 1 X No Change
0 1 0 Advance
0 1 0 No Change
0 0 X X No Change
0 X X Latched
0 X X 1 Latched
1 X X 0 Q0 = Q1 = Q2 = Q3 = 0
X = Don’t Care
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377
MC14553B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
(VOH = 4.6 Vdc) Source — 5.0 – 0.25 — – 0.2 – 0.36 — 0.14 —
(VOH = 9.5 Vdc) Pin 3 10 – 0.62 — – 0.5 – 0.9 — 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — 1.1 —
(VOH = 4.6 Vdc) Source — 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 — mAdc
(VOH = 9.5 Vdc) Other 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) Outputs 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink — IOL 5.0 0.5 — 0.4 0.88 — 0.28 — mAdc
(VOL = 0.5 Vdc) Pin 3 10 1.1 — 0.9 2.25 — 0.65 —
(VOL = 1.5 Vdc) 15 1.8 — 1.5 8.8 — 1.20 —
(VOL = 0.4 Vdc) Sink — Other 5.0 3.0 — 2.5 4.0 — 1.6 — mAdc
(VOL = 0.5 Vdc) Outputs 10 6.0 — 5.0 8.0 — 3.5 —
(VOL = 1.5 Vdc) 15 18 — 15 20 — 10 —
(Vin = 0)
(Per Package) 10 — 10 — 0.020 10 — 300
MR = VDD 15 — 20 — 0.030 20 — 600
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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378
MC14553B
Characteristic
Figure
2a
Symbol
tTLH,
ns
Clock to BCD Out 2a tPLH, 5.0 — 900 1800 ns
tPHL 10 — 500 1000
15 — 200 400
Clock to Overflow 2a tPHL 5.0 — 600 1200 ns
10 — 400 800
15 — 200 400
Reset to BCD Out 2b tPHL 5.0 — 900 1800 ns
10 — 500 1000
15 — 300 600
Clock to Latch Enable Setup Time 2b tsu 5.0 600 300 — ns
Master Reset to Latch Enable Setup Time 10 400 200 —
15 200 100 —
Removal Time 2b trem 5.0 – 80 – 200 — ns
Latch Enable to Clock 10 – 10 – 70 —
15 0 – 50 —
Clock Pulse Width 2a tWH(cl) 5.0 550 275 — ns
10 200 100 —
15 150 75 —
Reset Pulse Width 2b tWH(R) 5.0 1200 600 — ns
10 600 300 —
15 450 225 —
Reset Removal Time — trem 5.0 – 80 – 180 — ns
10 0 – 50 —
15 20 – 30 —
Input Clock Frequency 2a fcl 5.0 — 1.5 0.9 MHz
10 — 5.0 2.5
15 — 7.0 3.5
Input Clock Rise Time 2b tTLH 5.0 No ns
10 Limit
15
Disable, MR, Latch Enable — tTLH, 5.0 — — 15 µs
Rise and Fall Times tTHL 10 — — 5.0
15 — — 4.0
Scan Oscillator Frequency 1 fosc 5.0 — 1.5/C1 — Hz
(C1 measured in µF) 10 — 4.2/C1 —
15 — 7.0/C1 —
http://onsemi.com
379
MC14553B
1000
100
101
899
900
901
990
991
992
993
994
995
996
997
998
999
10
12
13
14
15
16
17
86
87
88
89
90
91
92
93
94
95
96
97
98
99
11
1
2
3
4
5
6
7
8
9
UNITS CLOCK
UNITS Q0
UNITS Q1
UNITS Q2
UNITS Q3
TENS CLOCK
TENS Q0
TENS Q3
UP AT 80 UP AT 980
HUNDREDS
CLOCK
HUNDREDS Q0
HUNDREDS Q3
UP AT 800
DISABLE (DISABLES CLOCK WHEN HIGH)
OVERFLOW
MASTER
RESET
SCAN
OSCILLATOR
DIGIT SELECT 1
UNITS
DIGIT SELECT 2 TENS
DIGIT SELECT 3 HUNDREDS
Figure 1. 3–Digit Counter Timing Diagram (Reference Figure 3)
16 VDD
(a)
PULSE Q3 20 ns
1000
C tWL(cl)
999
GENERATOR Q2 CL 20 ns
90%
Q1 CL CLOCK 50%
10%
LE Q0 CL tPLH
O.F. CL tPHL 1/fcl
DIS DS1 CL BCD OUT 10% 90% 50% tPHL
DS2 tTLH tTHL
MR DS3 OVERFLOW 50%
8 VSS
tTLH
90%
VDD CLOCK 50%
(b) 10%
GENERATOR Q3 tsu trem
C
1 Q2 CL
Q1 CL LATCH 50%
GENERATOR
LE Q0 CL ENABLE
2 tPHL, tPLH
O.F. CL tsu
GENERATOR MR DS1 CL
3 BCD OUT 50%
DS2
DIS DS3
tPHL
VSS
MASTER RESET 50%
tWH(R)
Figure 2. Switching Time Test Circuits and Waveforms
http://onsemi.com
380
MC14553B
The MC14553B three–digit counter, shown in Figure 3, The Master Reset input, when taken high, initializes the
consists of three negative edge–triggered BCD counters three BCD counters and the multiplexer scanning circuit.
which are cascaded in a synchronous fashion. A quad latch While Master Reset is high the digit scanner is set to digit
at the output of each of the three BCD counters permits one; but all three digit select outputs are disabled to prolong
storage of any given count. The three sets of BCD outputs display life, and the scan oscillator is inhibited. The Disable
(active high), after going through the latches, are time input, when high, prevents the input clock from reaching the
division multiplexed, providing one BCD number or digit at counters, while still retaining the last count. A pulse shaping
a time. Digit select outputs (active low) are provided for circuit at the clock input permits the counters to continue
display control. All outputs are TTL compatible. operating on input pulses with very slow rise times.
An on–chip oscillator provides the low frequency Information present in the counters when the latch input
scanning clock which drives the multiplexer output selector. goes high, will be stored in the latches and will be retained
The frequency of the oscillator can be controlled externally while the latch input is high, independent of other inputs.
by a capacitor between pins 3 and 4, or it can be overridden Information can be recovered from the latches after the
and driven with an external clock at pin 4. Multiple devices counters have been reset if Latch Enable remains high
can be cascaded using the overflow output, which provides during the entire reset cycle.
one pulse for every 1000 counts.
C1A
LATCH ENABLE 4
10 SCAN PULSE
R C1
OSCILLATOR 3 GENERATOR
C1B
CLOCK
12 R SCANNER
Q0
PULSE C Q1 QUAD
SHAPER Q2 LATCH
R ÷ 10
Q3 9
UNITS Q0
11
DISABLE
(ACTIVE
HIGH) MULTIPLEXER
7
Q0 Q1
C
Q1 QUAD BCD
Q2 LATCH OUTPUTS
R ÷ 10
Q3 (ACTIVE
TENS
HIGH)
6
Q2
Q0
C
Q1 QUAD 5
Q3
Q2 LATCH
R
÷ 10 Q3
HUNDREDS
2 1 15
DS1 DS2 DS3
13 14 (LSD) DIGIT SELECT (MSD)
MR OVERFLOW (ACTIVE LOW)
(ACTIVE HIGH)
Figure 3. Expanded Block Diagram
http://onsemi.com
381
STROBE
RESET
10 13 10 13
LE MR 4 LE MR 4
12 C1A 0.001 12 C1 A
CLOCK CLK CLK 3
INPUT 3 µF
MC14553B C1B MC14553B C1 B
11 11 14
DIS 14 DIS
O.F. O.F.
Q3 Q2 Q1 Q0 DS3 DS2 DS1 Q3 Q2 Q1 Q0 DS3 DS2 DS1
5 6 7 9 15 1 2 5 6 7 9 15 1 2
5 9
A a
3 10
B b
2 11
VDD C c
4 12
D MC14543B d
6 13
Ph e
1 15
382
VDD LD f
7 g 14
BI
MC14553B
http://onsemi.com
Figure 4. Six–Digit Display
5 9
A a
3
B b 10
2 11
C c
4 12
D MC14543B d
6 13
Ph e
1 15
VDD LD f
7 14
BI g
LSD DISPLAYS ARE LOW CURRENT LEDs MSD

(I peak < 10 mA PER SEGMENT)
MC14555B, MC14556B
Dual Binary to 1-of-4

Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2, http://onsemi.com
Q3). The MC14555B has the selected output go to the “high” state,
and the MC14556B has the selected output go to the “low” state. MARKING
Expanded decoding such as binary–to–hexadecimal (1–of–16), etc., DIAGRAMS
can be achieved by using other MC14555B or MC14556B devices. 16
Applications include code conversion, address decoding, memory PDIP–16
P SUFFIX MC1455XBCP
selection control, and demultiplexing (using the Enable input as a data AWLYYWW
CASE 648
input) in digital data transmission systems.
1
• Active High or Active Low Outputs SOIC–16
1455XB
• Expandable D SUFFIX AWLYWW
CASE 751B
1
• Capable of Driving Two Low–Power TTL Loads or One Low–Power SOEIAJ–16
Schottky TTL Load Over the Rated Temperature Range F SUFFIX MC1455XB
CASE 966 AWLYWW
X = Specific Device Code

Symbol Parameter Value Unit WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
(DC or Transient)
Iin, Iout Input or Output Current ± 10 mA ORDERING INFORMATION
TA Ambient Temperature Range – 55 to +125 °C MC14555BD SOIC–16 48/Rail

Tstg Storage Temperature Range – 65 to +150 °C MC14555BDR2 SOIC–16 2500/Tape & Reel
TL Lead Temperature 260 °C MC14555BF SOEIAJ–16 See Note 1.
may occur.
applications of any voltage higher than maximum rated voltages to this MC14556BF SOEIAJ–16 See Note 1.
to the range VSS v (Vin or Vout) vVDD. MC14556BFEL SOEIAJ–16 See Note 1.

March, 2000 – Rev. 3 MC14555B/D
MC14555B, MC14556B
PIN ASSIGNMENTS
MC14555B MC14556B
EA 1 16 VDD EA 1 16 VDD
AA 2 15 EB AA 2 15 EB
BA 3 14 AB BA 3 14 AB
Q0A 4 13 BB Q0A 4 13 BB
Q1A 5 12 Q0B Q1A 5 12 Q0B
Q2A 6 11 Q1B Q2A 6 11 Q1B
Q3A 7 10 Q2B Q3A 7 10 Q2B
VSS 8 9 Q3B VSS 8 9 Q3B
TRUTH TABLE
Inputs Outputs
Enable Select MC14555B MC14556B
E B A Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0 0 0 0 0 0 1 1 1 1 0
0 0 1 0 0 1 0 1 1 0 1
0 1 0 0 1 0 0 1 0 1 1
0 1 1 1 0 0 0 0 1 1 1
1 X X 0 0 0 0 1 1 1 1
X = Don’t Care
BLOCK DIAGRAM
MC14555B MC14556B
2 A Q0 4 2 A Q0 4
Q1 5 Q1 5
3 B 3 B
Q2 6 Q2 6
1 E 1 E
Q3 7 Q3 7
14 A Q0 12 14 A Q0 12
Q1 11 Q1 11
13 B 13 B
Q2 10 Q2 10
15 E 15 E
Q3 9 Q3 9
VDD = PIN 16
VSS = PIN 8
http://onsemi.com
384
MC14555B, MC14556B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
http://onsemi.com
385
MC14555B, MC14556B
Characteristic
Symbol
tTLH,
ns
Propagation Delay Time — A, B to Output tPLH, ns
Propagation Delay Time — E to Output tPLH, ns
INPUT E LOW
20 ns 20 ns INPUT A HIGH, INPUT E LOW
20 ns 20 ns
VDD
90%
50% VDD
90%
A INPUTS 10% VSS INPUT B 50%
1
(50% DUTY CYCLE) 10% VSS
2f VDD tPHL tPLH
90% VOH
OUTPUT Q3 50%
B INPUTS VSS
MC14556B 10%
(50% DUTY CYCLE) V
VOH tTHL tTLH OL
tPLH tPHL
VOH
OUTPUT Q1 VOL OUTPUT Q3 90%
50%
MC14555B 10% VOL
All 8 outputs connect to respective CL loads.
f in respect to a system clock. tTLH tTHL
Figure 1. Dynamic Power Dissipation Signal Waveforms Figure 2. Dynamic Signal Waveforms
LOGIC DIAGRAM
(1/2 of Dual)
* Q0
*
Q1
* Q2
* Q3
*Eliminated for MC14555B
http://onsemi.com
386
MC14557B
1-to-64 Bit Variable Length

Shift Register
The MC14557B is a static clocked serial shift register whose length
may be programmed to be any number of bits between 1 and 64. The
number of bits selected is equal to the sum of the subscripts of the
enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus http://onsemi.com
one. Serial data may be selected from the A or B data inputs with the
A/B select input. This feature is useful for recirculation purposes. A
Clock Enable (CE) input is provided to allow gating of the clock or MARKING
negative edge clocking capability. DIAGRAMS
The device can be effectively used for variable digital delay lines or 16
simply to implement odd length shift registers. PDIP–16
P SUFFIX MC14557BCP
• 1–64 Bit Programmable Length CASE 648 AWLYYWW
• Q and Q Serial Buffered Outputs 1

• Asynchronous Master Reset
16
• All Inputs Buffered
• No Limit On Clock Rise and Fall Times SOIC–16 14557B
• Supply Voltage Range = 3.0 Vdc to 18 Vdc DW SUFFIX
• Capable of Driving Two Low–power TTL Loads or one Low–power
CASE 751G
AWLYYWW
1
16

F SUFFIX MC14557B

(DC or Transient) A = Assembly Location
WL or L = Wafer Lot
Iin, Iout Input or Output Current ±10 mA YY or Y = Year
may occur. MC14557BDWR2 SOIC–16 1000/Tape & Reel

March, 2000 – Rev. 3 MC14557B/D
MC14557B
PIN ASSIGNMENT
L2 1 16 VDD
L1 2 15 L4
RESET 3 14 L8
CLOCK 4 13 L16
CE 5 12 L32
B 6 11 Q
A 7 10 Q
VSS 8 9 A/B SEL
BLOCK DIAGRAM
3 RESET
4 CLOCK
5 CE
6 B Q 10
7 A
9 A/B SELECT
2 L1
1 L2
15 L4 Q 11
14 L8
13 L16
12 L32
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Inputs Output
Rst A/B Clock CE Q
0 0 0 B
0 1 0 A
0 0 1 B
0 1 1 A
1 X X X 0
Q is the output of the first selected shift
register stage.
X = Don’t Care
LENGTH SELECT TRUTH TABLE

L32 L16 L8 L4 L2 L1 Register Length
0 0 0 0 0 0 1 Bit
0 0 0 0 0 1 2 Bits
Bit
0 0 0 0 1 0 3 Bits
0 0 0 0 1 1 4 Bits
0 0 0 1 0 0 5 Bits
0 0 0 1 0 1 6 Bits

1 0 0 0 0 0 33 Bits
Bit
1 0 0 0 0 1 34 Bits

1 1 1 1 0 0 61 Bits
1 1 1 1 1 1 62 Bits
1 1 1 1 1 0 63 Bits
1 1 1 1 0 1 64 Bit
Bits
NOTE: Length equals the sum of the binary length control
subscripts plus one.
http://onsemi.com
388
MC14557B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.020 10 — 300
15 — 20 — 0.030 20 — 600
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
http://onsemi.com
389
MC14557B
Characteristic
Rise and Fall Time, Q or Q Output
Symbol
tTLH,
ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5 — 100 200
Propagation Delay, Clock or CE to Q or Q tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPHL 5 — 300 600
Propagation Delay, Reset to Q or Q tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPHL 5 — 300 600
Pulse Width, Clock tWH(cl) 5 200 95 — ns
10 100 45 —
15 75 35 —
Pulse Width, Reset tWH(rst) 5 300 150 — ns
10 140 70 —
15 100 50 —
Clock Frequency (50% Duty Cycle) fcl 5 — 3.0 1.7 MHz
10 — 7.5 5.0
15 — 13.0 6.7
Setup Time, A or B to Clock or CE tsu ns
Worst case condition: L1 = L2 = L4 = L8 = 5 700 350 —
L16 = L32 = VSS (Register Length = 1) 10 290 130 —
15 145 85 —
Best case condition: L32 = VDD, L1 through L16 = 5 400 45 —
Don’t Care (Any register length from 33 to 64) 10 165 5 —
15 60 0 —
Hold Time, Clock or CE to A or B th ns
Best case condition: L1 = L2 = L4 = L8 = L16 = 5 200 – 150 —
L32 = VSS (Register Length = 1) 10 100 – 60 —
15 10 – 50 —
Worst case condition: L32 = VDD, L1 through L16 = 5 400 50 —
Don’t Care (Any register length from 33 to 64) 10 185 25 —
15 85 22 —
Rise and Fall Time, Clock tr, 5 —
tf 10 No Limit
15
Rise and Fall Time, Reset or CE tr, 5 — — 15 µs
tf 10 — — 5
15 — — 4
Removal Time, Reset to Clock or CE trem 5 160 80 — ns
10 80 40 —
15 70 35 —
http://onsemi.com
390
MC14557B
TIMING DIAGRAM
VDD
50%
CLOCK tWH(cl) VSS
1/fcl VDD
50%
A INPUT trem VSS
tsu
VDD
th 50%
RESET VSS
tTLH tTHL PWR
1–bit length: VOH
90%
CE = 0 50%
A/B = 1 Q 10% VOL
L1 = L2 = L4 = L8 = L16 = L32 = 0 tPLH tPHL tPHL
http://onsemi.com
391
5
CE
4
CLOCK
3
RESET
7 C R C R C R C R
A 32 BIT 16 BIT 8 BIT 4 BIT
6
B
A/B 9 12 13 14 15
392
SELECT L32 L16 L8 L4
MC14557B
LOGIC DIAGRAM
http://onsemi.com
C R C R C R 10
Q
2 BIT 1 BIT 1 BIT
11
Q
1 2 VDD = PIN 16
L2 L1 VSS = PIN 8
MC14562B
128-Bit Static Shift

Register
The MC14562B is a 128–bit static shift register constructed with
single monolithic structure. Data is clocked in and out of the shift
register on the positive edge of the clock input. Data outputs are http://onsemi.com
available every 16 bits, from 16 through bit 128. This complementary
MOS shift register is primarily used where low power dissipation
and/or high noise immunity is desired. MARKING
14
PDIP–14
• Cascadable to Provide Longer Shift Register Lengths P SUFFIX MC14562BCP
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 646 AWLYYWW

WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
(DC or Transient)
(8–Second Soldering) MC14562BCP PDIP–14 25/Rail
may occur.

March, 2000 – Rev. 3 MC14562B/D
MC14562B
PIN ASSIGNMENT
Q64 1 14 VDD
Q96 2 13 Q32
Q128 3 12 DATA
NC 4 11 NC
CLOCK 5 10 Q16
Q112 6 9 Q48
VSS 7 8 Q80
NC = NO CONNECTION
BLOCK DIAGRAM
Q16 10
12 DATA Q32 13
Q48 9
Q64 1
Q80 8
5 CLOCK Q96 2
Q112 6
Q128 3
Pins 4 and 11 VDD = PIN 14

not used. VSS = PIN 7
LOGIC DIAGRAM
CLOCK 5
DATA IN 12
D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q
C C C C C C C C C C
1 2 3 16 17 32 33 48 49 64
10 Q16
D Q D Q D Q D Q D Q D Q D Q D Q
C C C C C C C C 13 Q32
65 80 81 96 97 112 113 128
9 Q48
1 Q64
8 Q80
2 Q96
6 Q112
3 Q128
http://onsemi.com
394
MC14562B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 05 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.020 10 — 300
15 — 20 — 0.030 20 — 600
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
http://onsemi.com
395
MC14562B
Characteristic
Symbol
tTLH,
ns
Clock to Q tPHL
(50% Duty Cycle) 10 220 110 —
15 150 75 —
10 — 5.6 3.0
15 — 8.0 4.0
Data to Clock Setup Time tsu(1) 5.0 – 20 – 170 — ns
10 – 10 – 64 —
15 0 – 60 —
tsu(0) 5.0 – 20 – 91 — ns
10 – 10 – 58 —
15 0 – 48 —
Data to Clock Hold Time th(1) 5.0 350 263 — ns
10 165 109 —
15 155 100 —
th(0) 5.0 350 267 — ns
10 200 140 —
15 140 93 —
Clock Input Rise and Fall Times tr, tf 5.0 — — 15 µs
10 — — 5
15 — — 4
http://onsemi.com
396
MC14562B
VDD
Q16
DATA Q32
Q48
Q64
Q80
CLOCK Q96
Q112
Q128
7 VSS CL CL CL CL CL CL CL CL
ID 500 µF
fo VDD
CLOCK
VSS
DATA VDD
(f = 1/2 fo)
VSS
http://onsemi.com
397
MC14562B
TIMING DIAGRAM
PIN PULSE 1 PULSE 16 PULSE 32 PULSE 128

NO.’S
CLOCK 5
DATA IN 12
Q16 10
Q32 13
Q28 3
AC TEST WAVEFORMS
PULSE 1 PULSE 2 PULSE 16 PULSE 17

90% VDD
CLOCK 50% 50% 50% 50%
10%
VSS
tWH tr
tWL tf
VDD
DATA IN 50% 50%
VSS
tsu(0)
th(0)
VDD
50% 10% 90%
Q16
VSS
tPHL
tTHL
PULSE 1 PULSE 2 PULSE 16 PULSE 17
VDD
CLOCK 50% 50% 50% 50%
VSS
tWH
tWL
VDD
DATA IN 50% 50%
VSS
tsu(1)
th(1)
VDD
Q16 50% 90%
10%
VSS
tPLH
tTHL
NOTE: The remaining Data–Bit Outputs (Q32, Q48, Q64, Q80, Q96, Q112 and Q128) will occur at Clock Pulse 32, 48, 64, 80,
96, 112, 128 in the same relationship as Q16.
http://onsemi.com
398
MC14569B
Programmable Divide-By-N
Dual 4-Bit Binary/BCD
Down Counter
The MC14569B is a programmable divide–by–N dual 4–bit binary
or BCD down counter constructed with MOS P–channel and http://onsemi.com
N–channel enhancement mode devices (complementary MOS) in a
monolithic structure.
This device has been designed for use with the MC14568B phase MARKING
comparator/counter in frequency synthesizers, phase–locked loops, DIAGRAMS
and other frequency division applications requiring low power 16
dissipation and/or high noise immunity. PDIP–16
MC14569BCP
• Speed–up Circuitry for Zero Detection P SUFFIX
CASE 648 AWLYYWW
• Each 4–Bit Counter Can Divide Independently in BCD or Binary 1
Mode
• Can be Cascaded With MC14526B for 16
Frequency Synthesizer Applications TSSOP–16 14
• All Outputs are Buffered DT SUFFIX 569B
• Schmitt Triggered Clock Conditioning CASE 948F ALYW
16
SOIC–16 14569B
Symbol Parameter Value Unit DW SUFFIX
VDD DC Supply Voltage Range – 0.5 to +18.0 V CASE 751G
AWLYYWW
(DC or Transient) 1
Iin, Iout Input or Output Current ±10 mA A = Assembly Location

YY or Y = Year
WW or W = Work Week

may occur. MC14569BDT TSSOP–16 96/Rail
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14569BDW SOIC–16 47/Rail

March, 2000 – Rev. 3 MC14569B/D
MC14569B
PIN ASSIGNMENT
ZERO 1 16 VDD
DETECT
CTL1 2 15 Q
P0 3 14 P7
P1 4 13 P6
P2 5 12 P5
P3 6 11 P4
CASCADE 7 10 CTL2
FEEDBACK
VSS 8 9 CLOCK
BLOCK DIAGRAM
P0 P1 P2 P3 CTL1 CTL2 P4 P5 P6 P7
CTL = Low for Binary Count
3 4 5 6 2 10 11 12 13 14
CTL = High for BCD Count VDD = PIN 16
VSS = PIN 8
9 BINARY/BCD CLOCK BINARY/BCD 15

CLOCK Q
COUNTER #1 LOAD COUNTER #2
CASCADE 7 1 ZERO
FEEDBACK ZERO DETECT ENCODER
DETECT
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400
MC14569B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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401
MC14569B
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
VDD
Vdc Min
All Types
Typ (6.) Max Unit
10 — 50 100
15 — 40 80
10 — 50 100
15 — 40 80
Turn–On Delay Time tPLH ns
Zero Detect Output 5.0 — 420 700
10 — 175 300
15 — 125 250
Q Output 5.0 — 675 1200 ns
10 — 285 500
15 — 200 400
Turn–Off Delay Time tPHL ns
Zero Detect Output 5.0 — 380 600
10 — 150 300
15 — 100 200
Q Output 5.0 — 530 1000 ns
10 — 225 400
15 — 155 300
10 150 45 —
15 115 30 —
10 — 9.5 5.1
15 — 13.0 7.8
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 NO LIMIT µs
10
15
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402
MC14569B
SWITCHING WAVEFORMS
20 ns
20 ns
90%
CLOCK 50% fin = fmax
10%
tWH
tPLH tPHL
90%
Q 50%
10%
tTLH tTHL
Figure 1.
20 ns
20 ns
90%
CLOCK 50%
10%
tWH
tPHL
tPLH
90%
ZERO DETECT 10%
tTLH tTHL
Figure 2.
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403
MC14569B
PIN DESCRIPTIONS
INPUTS CONTROLS
P0, P1, P2, P3 (Pins 3, 4, 5, 6) — Preset Inputs. Cascade Feedback (Pin 7) — This pin is normally set
Programmable inputs for the least significant counter. May high. When low, loading of the preset inputs (P0 through P7)
be binary or BCD depending on the control input. is inhibited, i.e., P0 through P7 are “don’t cares.” Refer to
P4, P5, P6, P7 (Pins 11, 12, 13, 14) — Preset Inputs. Table 1 for output characteristics.
Programmable inputs for the most significant counter. May CTL1 (Pin 2) — This pin controls the counting mode of
be binary or BCD depending on the control input. the least significant counter. When set high, counting mode
Clock (Pin 9) — Preset data is decremented by one on is BCD. When set low, counting mode is binary.
each positive transition of this signal. CTL2 (Pin 10) — This pin controls the counting mode of
the most significant counter. When set high, counting mode
OUTPUTS is BCD. When set low, counting mode is binary.
Zero Detect (Pin 1) — This output is normally low and
goes high for one clock cycle when the counter has SUPPLY PINS
decremented to zero. VSS (Pin 18) — Negative Supply Voltage. This pin is
Q (Pin 15) — Output of the last stage of the most usually connected to ground.
significant counter. This output will be inactive unless the VDD (Pin 16) — Positive Supply Voltage. This pin is
preset input P7 has been set high. connected to a positive supply voltage ranging from 3.0
volts to 18.0 volts.
The MC14569B is a programmable divide–by–N dual one pulse appears on the Zero Detect output. (See Timing
4–bit down counter. This counter may be programmed (i.e., Diagram.) The Q output is the output of the last stage of the
preset) in BCD or binary code through inputs P0 to P7. For most significant counter (See Tables 1 through 5, Mode
each counter, the counting sequence may be chosen Controls.)
independently by applying a high (for BCD count) or a low When cascading the MC14569B to the MC14526B, the
(for binary count) to the control inputs CTL1 and CTL2. Cascade Feedback input, Q, and Zero Detect outputs must
The divide ratio N (N being the value programmed on the be respectively connected to “0”, Clock, and Load of the
preset inputs P0 to P7) is automatically loaded into the following counter. If the MC14569B is used alone, Cascade
counter as soon as the count 1 is detected. Therefore, a Feedback must be connected to VDD.
division ratio of one is not possible. After N clock cycles,
18
CL = 50 pF
16
f, FREQUENCY (MHz), TYPICAL
14
12 VDD = 15 V
10
8.0 10 V
6.0
4.0 5.0 V
2.0
0
– 40 – 20 0 + 20 + 40 + 60 + 80 + 100
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404
MC14569B
Table 1. Mode Controls (Cascade Feedback = Low)

Counter Control Values Divide Ratio
CTL1 CTL2 Zero Detect Q
0 0 256 256
0 1 160 160
1 0 160 160
1 1 100 100
NOTE: Data Preset Inputs (P0–P7) are “Don’t Cares” while Cascade Feedback is
Low.
Table 2. Mode Controls (CTL1 = Low, CTL2 = Low, Cascade Feedback = High)
Preset Inputs Divide Ratio
Zero
P7 P6 P5 P4 P3 P2 P1 P0 Detect Q Comments
0 0 0 0 0 0 0 0 256 256 Max Count
0 0 0 0 0 0 0 1 X X Illegal State
0 0 0 0 0 0 1 0 2 X Min Count
0 0 0 0 0 0 1 1 3 X
X
X
X
0 0 0 0 1 1 1 1 15 X
0 0 0 1 0 0 0 0 16 X
X
X
X
0 0 1 0 0 0 0 0 32 X
X
X
X
0 1 0 0 0 0 0 0 64 X
X
X
X
0 1 1 1 1 1 1 1 127 X
1 0 0 0 0 0 0 0 128 128 Q Output Active

1 0 0 0 1 0 0 0 136 136

1 1 1 1 1 1 1 1 255 255
27 26 25 24 23 22 21 20
128 64 32 16 8 4 2 1 Bit Value
Counter #2 Counter #1 Counting
Binary Binary Sequence
X = No Output (Always Low)
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405
MC14569B
Table 3. Mode Controls (CTL1 = High, CTL2 = Low, Cascade Feedback = High)
Preset Inputs Divide Ratio
Zero
0 0 0 0 0 0 0 0 160 160 Max Count
0 0 0 0 0 0 1 0 2 X Min Count
0 0 0 0 0 0 1 1 3 X
X
X
X
0 0 0 0 1 0 0 1 9 X
0 0 0 1 0 0 0 0 10 X
X
X
X
0 0 0 1 1 0 0 1 19 X
0 0 1 0 0 0 0 0 20 X
X
X
X
0 0 1 1 0 0 0 0 30 X
X
X
X
0 1 0 0 0 0 0 0 40 X
X
X
X
0 1 0 1 0 0 0 0 50 X
X
X
X
0 1 1 0 0 0 0 0 60 X
X
X
X
0 1 1 1 0 0 0 0 70 X
X
X
X
1 0 0 0 0 0 0 0 80 80 Q Output Active

1 0 0 1 0 0 0 0 90 90

1 1 1 1 0 0 0 0 150 150

1 1 1 1 1 0 0 1 159 159
80 40 20 10 8 4 2 1 Bit Value
Binary BCD Sequence
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406
MC14569B
Table 4. Mode Controls (CTL1 = Low, CTL2 = High, Cascade Feedback = High)
Preset Values Divide Ratio
Zero
0 0 0 0 0 0 0 0 160 160 Max Count
0 0 0 0 0 0 1 0 2 X Min Count
0 0 0 0 0 0 1 1 3 X
X
X
X
0 0 0 0 1 1 1 1 15 X
0 0 0 1 0 0 0 0 16 X
X
X
X
0 0 0 1 1 1 1 1 31 X
0 0 1 0 0 0 0 0 32 X
X
X
X
0 0 1 1 0 0 0 0 48 X

0 1 0 0 0 0 0 0 64 X

0 1 0 1 0 0 0 0 80 X

0 1 1 1 0 0 0 0 112 X

1 0 0 0 0 0 0 0 128 128 Q Output Active

1 0 0 1 0 0 0 0 144 144

1 0 0 1 1 1 1 1 159 159
27 26 25 24 23 22 21 20
128 64 32 16 8 4 2 1 Bit Value
BCD Binary Sequence
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407
MC14569B
Table 5. Mode Controls (CTL1 = High, CTL2 = High, Cascade Feedback = High)
Preset Values Divide Ratio
Zero
0 0 0 0 0 0 0 0 100 100 Max Count
0 0 0 0 0 0 0 1 X X illegal state
0 0 0 0 0 0 1 0 2 X Min Count
0 0 0 0 0 0 1 1 3 X
X
X
X
0 0 0 0 1 0 0 1 9 X
0 0 0 1 0 0 0 0 10 X
X
X
X
0 0 1 1 0 0 0 0 30 X
X
X
X
0 1 0 0 0 0 0 0 40 X
X
X
X
0 1 0 1 0 0 0 0 50 X
X
X
X
0 1 1 1 0 0 0 0 70 X
X
X
X
1 0 0 0 0 0 0 0 80 80 Q Output Active

1 0 0 1 0 0 0 0 90 90

1 0 0 1 1 0 0 1 99 99
80 40 20 10 8 4 2 1 Bit Value
BCD BCD Sequence
TIMING DIAGRAM MC14569B
CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DIVIDE
BY 2
DIVIDE
ZERO BY 3
DETECT
OUTPUT DIVIDE
BY 4
DIVIDE
BY 12
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MC14569B
LOGIC DIAGRAM
2
CTL1
DP Q
PE
D C
DP Q
3 PE
P0 D C
4 DP Q
P1 PE
D C
DP Q PE
5 D C
P2
DP Q
PE
6 D C
P3
DP Q
PE
D C
DP Q
PE
D C
DP Q
PE
D C
IU
VDD
CASCADE 7
FEEDBACK VDD
9
CLOCK
1
ZERO
DETECT
11 DP D C
P4
Q PE
12 DP D C
P5
Q PE
13 DP D C
P6
Q PE
14 DP D C
P7
Q PE
10 15
CTL2
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409
MC14569B
CF CF CF
fin C Q C Q4 C Q4 Q1/C2
MC14522B MC14522B
MC14569B OR OR MC14568B
ZERO DETECT PE MC14526B “0” PE MC14526B “0” PE “0”
DP0 – – – – – – DP3 DP0 – – – – – – DP3 DP0 – – – – – – DP3
LSD MSD fout
Figure 3. Cascading MC14568B and MC14522B or MC14526B with MC14569B
fout
(40 kHz) PCin PCout VCO
C1 G VSS (144 – 146 MHz)
CT1 F VSS
VSS “0” Q1/C2
PE
VDD
DP0 – – – – DP3
MC14011
Q CF
MC14569B C
ZERO DETECT
MIXER
2k
2M
CRYSTAL
Frequencies shown in parenthesis are given as an example OSCILLATOR
(143.5 MHz)
Figure 4. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer

(Channel Spacing 10 kHz)
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410
MC14572UB
Hex Gate
The MC14572UB hex functional gate is constructed with MOS
monolithic structure. These complementary MOS logic gates find
primary use where low power dissipation and/or high noise immunity
is desired. The chip contains four inverters, one NOR gate and one
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NAND gate.
• Single Supply Operation DIAGRAMS
• NOR Input Pin Adjacent to VSS Pin to Simplify Use As An Inverter PDIP–16
MC14572UBCP
P SUFFIX
• NAND Input Pin Adjacent to VDD Pin to Simplify Use As An CASE 648 AWLYYWW
Inverter 1
• NOR Output Pin Adjacent to Inverter Input Pin For OR Application 16
• NAND Output Pin Adjacent to Inverter Input Pin For AND SOIC–16
14572U
Application D SUFFIX AWLYWW
CASE 751B
SOEIAJ–16
F SUFFIX MC14572UB
CASE 966 AWLYWW
1

TA Ambient Temperature Range – 55 to +125 °C MC14572UBCP PDIP–16 2000/Box
Tstg Storage Temperature Range – 65 to +150 °C MC14572UBD SOIC–16 48/Rail

TL Lead Temperature 260 °C MC14572UBDR2 SOIC–16 2500/Tape & Reel
2. Maximum Ratings are those values beyond which damage to the device MC14572UBF SOEIAJ–16 See Note 1.
may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 1. For ordering information on the EIAJ version of
This device contains protection circuitry to guard against damage due to high ON Semiconductor representative.

MC14572UB
PIN ASSIGNMENT
OUTA 1 16 VDD
INA 2 15 IN 2F
OUTB 3 14 IN 1F
INB 4 13 OUTF
OUTC 5 12 INE
IN 1C 6 11 OUTE
IN 2C 7 10 IND
VSS 8 9 OUTD
LOGIC DIAGRAM
2 1
4 3
6
5
7
10 9
12 11
14
13
15
VDD = PIN 16
VSS = PIN 8
CIRCUIT SCHEMATIC
VDD VDD
VDD
7
2 1 13
6 14
5
VSS
15
VSS VSS
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412
MC14572UB
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.0 — 2.25 1.0 — 1.0
(VO = 9.0 or 1.0 Vdc) 10 — 2.0 — 4.50 2.0 — 2.0
(VO = 13.5 or 1.5 Vdc) 15 — 2.5 — 6.75 2.5 — 2.5
(VO = 0.5 or 4.5 Vdc) 5.0 4.0 — 4.0 2.75 — 4.0 —
(VO = 1.0 or 9.0 Vdc) 10 8.0 — 8.0 5.50 — 8.0 —
(VO = 1.5 or 13.5 Vdc) 15 12.5 — 12.5 8.25 — 12.5 —
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15
15 — 1.0 — 0.0015 1.0 — 30
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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413
MC14572UB
Output Rise Time

tTLH
ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 180
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
VDD VDD
INPUT
INPUT 16 16
7
2 PULSE
PULSE GENERATOR
OUTPUT 6 OUTPUT
GENERATOR 1 5
8 VSS CL 8 VSS CL
VDD
20 ns 20 ns
16 VDD
90% 90%
INPUT 14 INPUT 50% 50%
10% 10% VSS
15 OUTPUT
PULSE tPHL
13 tPLH
GENERATOR
8 VSS CL 90% 90% VOH
OUTPUT 50% 50%
10% 10%
VOL
tf tr
Figure 1. Switching Time Test Circuits and Waveforms
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414
MC14584B
Hex Schmitt Trigger
The MC14584B Hex Schmitt Trigger is constructed with MOS
dissipation and/or high noise immunity is desired. The MC14584B
may be used in place of the MC14069UB hex inverter for enhanced
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noise immunity to “square up” slowly changing waveforms.
MARKING
• Capable of Driving Two Low–power TTL Loads or One Low–power DIAGRAMS
• Double Diode Protection on All Inputs PDIP–14
MC14584BCP
• Can Be Used to Replace MC14069UB P SUFFIX
CASE 646 AWLYYWW
• For Greater Hysteresis, Use MC14106B which is Pin–for–Pin 1
Replacement for CD40106B and MM74Cl4 14
SOIC–14
14584B
D SUFFIX AWLYWW
CASE 751A
VDD DC Supply Voltage Range – 0.5 to +18.0 V TSSOP–14 14
DT SUFFIX 584B
CASE 948G ALYW
(DC or Transient)
(DC or Transient) per Pin 14
PD Power Dissipation, 500 mW SOEIAJ–14
per Package (Note 3.) F SUFFIX MC14584B
CASE 965 AWLYWW
1
WL or L = Wafer Lot
YY or Y = Year
2. Maximum Ratings are those values beyond which damage to the device WW or W = Work Week
may occur.
applications of any voltage higher than maximum rated voltages to this MC14584BCP PDIP–14 2000/Box
to the range VSS v (Vin or Vout) vVDD. MC14584BD SOIC–14 55/Rail
either VSS or VDD). Unused outputs must be left open. MC14584BDR2 SOIC–14 2500/Tape & Reel


March, 2000 – Rev. 3 MC14584B/D
MC14584B
PIN ASSIGNMENT
IN 1 1 14 VDD
OUT 1 2 13 IN 6
IN 2 3 12 OUT 6
OUT 2 4 11 IN 5
IN 3 5 10 OUT 5
OUT 3 6 9 IN 4
VSS 7 8 OUT 4
LOGIC DIAGRAM
1 2
3 4
5 6
9 8
11 10
13 12
VDD = PIN 14
VSS = PIN 7
EQIVALENT CIRCUIT SCHEMATIC

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416
MC14584B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
Vin = 0 “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15
15 — 1.0 — 0.0015 1.0 — 30
buffers switching)
Hysteresis Voltage VH (7.) 5.0 0.27 1.0 0.25 0.6 1.0 0.21 1.0 Vdc
10 0.36 1.3 0.3 0.7 1.2 0.25 1.2
15 0.77 1.7 0.6 1.1 1.5 0.50 1.4
Threshold Voltage VT+ Vdc
Positive–Going 5.0 1.9 3.5 1.8 2.7 3.4 1.7 3.4
10 3.4 7.0 3.3 5.3 6.9 3.2 6.9
15 5.2 10.6 5.2 8.0 10.5 5.2 10.5
Negative–Going VT– 5.0 1.6 3.3 1.6 2.1 3.2 1.5 3.2 Vdc
10 3.0 6.7 3.0 4.6 6.7 3.0 6.7
15 4.5 9.7 4.6 6.9 9.8 4.7 9.9
IT(CL) = IT(50 pF) + (CL – 50) Vfk
7. VH = VT+ – VT– (But maximum variation of VH is specified as less than VT + max – VT – min).
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MC14584B
VDD
10 — 50 100
15 — 40 80
10 — 50 100
15 — 40 80
Propagation Delay Time tPLH, tPHL 5.0 — 125 250 ns
10 — 50 100
15 — 40 80
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418
MC14584B
VDD 20 ns 20 ns
14 VDD
INPUT 90%
PULSE OUTPUT 50%
GENERATOR 10% VSS
INPUT
CL tPHL tPLH
7 VSS 90% VOH
OUTPUT 50%
10% VOL
tf tr
Vin Vout
VH VDD VH VDD
VT+ VT+
Vin VT– Vin VT–
VSS VSS
VDD VDD
Vout Vout
VSS VSS
(a) Schmitt Triggers will square up inputs with slow (b) A Schmitt trigger offers maximum noise immunity
rise and fall times. in gate applications.
Figure 2. Typical Schmitt Trigger Applications
VDD
0
0 VT– VT+ VDD
VH
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419
MC14585B
4-Bit Magnitude
Comparator
The MC14585B 4–Bit Magnitude Comparator is constructed with
complementary MOS (CMOS) enhancement mode devices. The
circuit has eight comparing inputs (A3, B3, A2, B2, A1, B1, A0, B0),
three cascading inputs (A < B, A = B, and A > B), and three outputs (A http://onsemi.com
< B, A = B, and A > B). This device compares two 4–bit words (A and
B) and determines whether they are “less than”, “equal to”, or “greater MARKING
than” by a high level on the appropriate output. For words greater than DIAGRAMS
4–bits, units can be cascaded by connecting outputs (A > B), (A < B), 16
and (A = B) to the corresponding inputs of the next significant PDIP–16
P SUFFIX MC14585BCP
comparator. Inputs (A < B), (A = B), and (A > B) on the least AWLYYWW
CASE 648
significant (first) comparator are connected to a low, a high, and a low,
respectively. 1
Applications include logic in CPU’s, correction and/or detection of 16
instrumentation conditions, comparator in testers, converters, and SOIC–16
14585B
D SUFFIX AWLYWW
controls. CASE 751B
• Expandable 16
• Applicable to Binary or 8421–BCD Code SOEIAJ–16
MC14585B
•
F SUFFIX
Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 966 AWLYWW
1
Schottky TTL Load over the Rated Temperature Range
• Can be Cascaded – See Fig. 3 A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
(DC or Transient) Device Package Shipping
Iin, Iout Input or Output Current ±10 mA MC14585BCP PDIP–16 2000/Box

per Package (Note 3.) MC14585BDR2 SOIC–16 2500/Tape & Reel
TA Ambient Temperature Range – 55 to +125 °C MC14585BF SOEIAJ–16 See Note 1.

Tstg Storage Temperature Range – 65 to +150 °C 1. For ordering information on the EIAJ version of
TL Lead Temperature 260 °C the SOIC packages, please contact your local
may occur.

March, 2000 – Rev. 3 MC14585B/D
MC14585B
PIN ASSIGNMENT
B2 1 16 VDD
A2 2 15 A3
(A = B)out 3 14 B3
(A u B)in 4 13 (A u B)out
(A t B)in 5 12 (A t B)out
(A = B)in 6 11 B0
A1 7 10 A0
VSS 8 9 B1
BLOCK DIAGRAM
4 (A > B)in
6 (A = B)in
5 (A < B)in (A > B)out 13
10 A0
11 B0
7 A1 (A = B)out 3
9 B1
2 A2
1 B2 (A < B)out 12
15 A3
14 B3
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE (x = Don’t Care)

Inputs
Comparing Cascading Outputs
A3, B3 A2, B2 A1, B1 A0, B0 A<B A=B A>B A<B A=B A>B
A3 > B3 x x x x x x 0 0 1
A3 = B3 A2 > B2 x x x x x 0 0 1
A3 = B3 A2 = B2 A1 > B1 x x x x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 > B0 x x x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 0 x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 1 x 0 1 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 0 x 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 1 x 1 1 0
A3 = B3 A2 = B2 A1 = B1 A0 < B0 x x x 1 0 0
A3 = B3 A2 = B2 A1 < B1 x x x x 1 0 0
A3 = B3 A2 < B2 x x x x x 1 0 0
A3 < B3 x x x x x x 1 0 0
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MC14585B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
(Vin = 0)
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
buffers switching)
IT(CL) = IT(50 pF) + (CL – 50) Vfk
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MC14585B
Characteristic
Symbol
tTLH,
ns
Turn–On, Turn–Off Delay Time tPLH, ns
20 ns
20 ns
VDD
A3
1 VSS
2f VDD
B3
VSS
20 ns 20 ns
VOH
(A > B)out VDD
90%
VOL 50%
B0
VOH 10% VSS
(A = B)out tPLH tPHL
VOL VOH
90%
VOH 50%
(A < B)out
(A < B)out 10% VOL
VOL
tTLH tTHL
Inputs (A>B) and (A=B) high, and inputs B2, A2, B1,
A1, B0, A0 and (A<B) low. Inputs (A>B) and (A=B) high, and inputs B3, A3, B2,
f in respect to a system clock. A2, B1, A1, A0, and (A<B) low.
Figure 1. Dynamic Power Dissipation Figure 2. Dynamic Signal Waveforms

Signal Waveforms
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MC14585B
WORD
B = B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
WORD
A= A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
VSS VDD VSS
(A<B)
(A=B)
(A>B)
B3 A3 B2 A2 B1 A1 B0 A0
OUTPUT MC14585B
(A<B)
(A=B)
(A>B)
INPUTS
MC14585B
MC14585B
WORD B = B11, B10, ..., B0.

WORD A = A11, A10, ..., A0.
(A<B)
(A=B)
(A>B)
OUTPUTS
Figure 3. Cascading Comparators
LOGIC DIAGRAM
15
A3
14
B3
2
A2
1
B2
7 12
A1 (A < B)out
9
B1
10
A0
11
B0
5
(A < B)in
3
6 (A = B)out
(A = B)in
13
4 (A > B)out
(A > B)in
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MC14598B
8-Bit Bus-Compatible
Latches
The MC14598B is an 8–bit latch addressed with an external binary
address. The 8 latch–outputs are high drive, three–state and bus line
compatible. The drive capability allows direct applications with MPU
systems such as the Motorola 6800 family. http://onsemi.com
The latches of the MC14598B are accessed via the Address pins,
A0, A1, and A2.
All 8 outputs from the latches are available in parallel when Enable
is in the low state. Data is entered into a selected latch from the Data
pin when the Strobe is high. Master reset is available on both parts.
• Serial Data Input
• Three–State Bus Compatible Parallel Outputs
• Three–State Control Pin (Enable) TTL Compatible Input
• Open Drain Full Flag (Multiple Latch Wire–O Ring) MARKING
• Master Reset 18
DIAGRAMS
• Level Shifting Inputs on All Except Enable PDIP–18
MC14598BCP
• Diode Protection — All Inputs P SUFFIX
CASE 707
AWLYYWW
• Supply Voltage Range — 3.0 Vdc to 18 Vdc 1
• Capable of Driving TTL Over Rated Temperature Range
With Fanout as Follows: A = Assembly Location
1 TTL Load WL or L = Wafer Lot
4 LSTTL Loads YY or Y = Year
WW or W = Work Week

Vin Input Voltage Range, – 0.5 to VDD + 0.5 V MC14598BCP PDIP–18 20/Rail
Enable (DC or Transient)
Vin Input Voltage Range, All Other – 0.5 to VDD + 12 V
Inputs (DC or Transient)
Vout Output Voltage Range, – 0.5 to VDD + 0.5 V
(DC or Transient)
against damage due to high static voltages or electric
TL Lead Temperature 260 °C voltages to this high–impedance circuit. For proper
(8–Second Soldering) operation, Vin and Vout should be constrained to the
(Vin or Vout) VDD.

March, 2000 – Rev. 3 MC14598B/D
MC14598B
PIN ASSIGNMENT
D0 1 18 VDD
RESET 2 17 D1
DATA 3 16 D2
ENABLE 4 15 D3
NC 5 14 D4
STROBE 6 13 D5
A0 7 12 D6
A1 8 11 D7
VSS 9 10 A2
BLOCK DIAGRAMS
MC14598B ENABLE
OUTPUT
4
TRUTH TABLE
RESET 2
DATA 3 1 D0 Enable Outputs
STROBE 6 17 D1 1 High Impedance
THREE
16 D2 0 Dn
A0 7 8 STATE
OUTPUT 15 D3
A1 8 ADDRESS LATCHES Dn = State of nth latch
BUFFERS 14 D4
A2 10 DECODER 13 D5
NC = NO CONNECTION
12 D6
VDD = 18 11 D7
VSS = 9
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MC14598B
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (3.) Max Min
125_C
Max Unit
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage (4.) — Enable “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 0.8 — 1.1 0.8 — 0.8
(VO = 9.0 or 1.0 Vdc) 10 — 1.6 — 2.2 1.6 — 1.6
(VO = 13.5 or 1.5 Vdc) 15 — 2.4 — 3.4 2.4 — 2.4
(VO = 0.5 or 4.5 Vdc) 5.0 2.0 — 2.0 1.9 — 2.0 —
(VO = 1.0 or 9.0 Vdc) 10 6.0 — 6.0 3.1 — 6.0 —
(VO = 1.5 or 13.5 Vdc) 15 10 — 10 4.3 — 10 —
Other Inputs
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current Source IOH mAdc
(Full — Sink Only)
(VOH = 4.6 Vdc) 5.0 – 1.0 – – 1.0 – 2.0 — – 1.0 —
(VOH = 9.5 Vdc) 10 — — — – 6.0 — — —
(VOH = 13.5 Vdc) 15 — — — – 12 — — —
(VOL = 0.5 Vdc) 10 — — — 6.0 — — —
(VOL = 1.5 Vdc) 15 — — — 12 — — —
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current at an IT 5.0 IT = (2.0 µA/kHz) f + IDD µAdc
**External Load Capacitance of 10 IT = (4.0 µA/kHz) f + IDD
**130 pF (4.) IT = (6.0 µA/kHz) f + IDD
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MC14598B
SWITCHING CHARACTERISTICS (5.) (TA = 25_C, CL = 130 pF + 1 TTL Load)
VDD
Vdc Min
All Types
Typ (6.) Max Unit
Enable to Output tPHL 5.0 — 160 320
10 — 125 250
15 — 100 200
Strobe to Output 5.0 — 200 400
10 — 100 200
15 — 80 160
Reset to Output 5.0 — 175 350
10 — 90 180
15 — 70 140
Pulse Width tWH, ns
Enable tWL 5.0 320 160 —
10 240 120 —
15 160 80 —
Strobe 5.0 200 100 —
10 100 50 —
15 80 40 —
Increment 5.0 200 100 —
10 100 50 —
15 80 40 —
Reset 5.0 300 150 —
10 160 80 —
15 100 50 —
Setup Time tsu ns
Data 5.0 100 50 —
10 50 25 —
15 35 20 —
Address 5.0 200 100 —
10 100 50 —
15 70 35 —
Hold Time th ns
Data 5.0 100 50 —
10 50 25 —
15 35 20 —
Address 5.0 100 50 —
10 50 25 —
15 35 20 —
10 20 – 15 —
15 20 – 10 —
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MC14598B
MC14598B FUNCTION DIAGRAM
RESET 2 VDD
DATA 3
TO OTHER 1 D0
LATCHES
STROBE 6
ENABLE 4 VSS
EACH LATCH
TO OTHER
LATCHES ZERO
SELECT 17 D1
A0 7 16 D2
15 D3
ADDRESS ADDITIONAL 7 LATCHES 14 D4
A1 8 DECODER 13 D5
12 D6
11 D7
A2 10
(M.S.B)
MC14598B TIMING DIAGRAM
90%
50% 10%
tTHL tPLH
D7 1 50% 90%
10%
tPLH tPHL tTLH
RESET
20 ns
tW 90%
A0, A1, A2 50% 10%
tsu th
DATA
tsu th
90% 90%
STROBE 10% 50% 10%
20 ns 20 ns tW
ENABLE *
tW
*1.4 V with VDD = 5.0 V

NOTES:
1. High–impedance output state (another device controls bus).
2. Output Load as for MC14597B.
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MC14598B
LATCH TRUTH TABLE TRUTH TABLE FOR MC14597B

Address Other Address
Strobe Reset Latch Latches Increment Enable Reset Counter Full
0 1 * * X 1 Count Up —
1 1 Data * X 1 No Change —
X 0 0 0 X 1 0 Reset to Zero Set to One
*= No change in state of latch X 0 1 No Change Set to One
X = Don’t care If at To Zero on

X 1 1 ADDRESS 7 Falling Edge
of STROBE
X = Don’t care
TEST LOAD
ALL OUTPUTS
+5.0 V
RL = 2.5 k
Dn
130 pF 11.7 k
Circuit diagrams external to or containing Motorola The information contained herein is for guidance only,
products are included as a means of illustration only. with no warranty of any type, expressed or implied.
Complete information sufficient for construction purposes Motorola reserves the right to make any changes to the
may not be fully illustrated. Although the information herein information and the product(s) to which the information
has been carefully checked and is believed to be reliable. applies and to discontinue manufacture of the product(s) at
Motorola assumes no responsibility for inaccuracies. any time.
Information herein does not convey to the purchaser any
license under the patent rights of Motorola or others.
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CHAPTER 7
CMOS Reliability
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RELIABILITY usually expressed in percent failures per thousand hours.
Paramount in the mind of every semiconductor user is the Other forms include FIT (Failures in Time = (%/103 hrs) x
question of device performance versus time. After the 10–4 = 10–9 failures per hour) and MTTF (Mean Time To
applicability of a particular device has been established, its Failure) or MTBF (Mean Time Between Failures), both
effectiveness depends on the length of troublefree service it being equal to 1/λ and having units of hours.
can offer. The reliability of a device is exactly that — an Since reliability evaluations usually involve only samples
expression of how well it will serve the customer. The of an entire population of devices, the concepts of the
following discussion will attempt to present an overview of Central Limit Theorem apply and λ is calculated using x2
ON Semiconductor’s reliability efforts. distribution through the equation:
BASIC CONCEPTS λ vx 2 (x, 2r + 2)

2nt
It is essential to begin with an explanation of the various
100 – CL
parameters of Reliability. These are probably summarized where x =
100
best in the Bathtub Curve (Figure 1). The reliability
performance of a device is characterized by three phases: CL = Confidence Limit in percent
infant mortality, useful life, and wearout. When a device is r = Number of rejects
produced, there is often a small distribution of failure n = Number of devices
mechanisms which will exhibit themselves under relatively t = Duration of test
moderate stress levels and therefore appear early. This The confidence limit is the degree of conservatism desired
period of early failures, termed infant mortality is reduced in the calculation. The Central Limit Theorem states that the
significantly through proper manufacturing controls and values of any sample of units out of a large population will
screening techniques. The most effective period is that in produce a normal distribution. A 50% confidence limit is
which only occasional random failure mechanisms appear. termed the best estimate and is the mean of this distribution.
The useful life typically spans a long period of time with a A 90% confidence limit is a very conservative value and
very low failure rate. The final period is that in which the results in a higher λ which represents the point at which 90%
devices literally wear out due to continuous phenomena of the area of the distribution is to the left of that value
which existed at the time of manufacture. Using strictly (Figure 2). The term (2r + 2) is called the degrees of freedom
controlled design techniques and selectivity in applications, and is an expression of the number of rejects in a form
this period is shifted well beyond the lifetime required by the suitable to x2 tables.
user.
50% CL
FREQUENCY
90% CL
INFANT MORTALITY
FAILURE RATE
(SUCH AS EARLY
BURN–IN FAILURES)
λ, FAILURE RATE
WEAROUT
USEFUL LIFE FAILURES
Figure 2.
The number of rejects is a critical factor since the

10 100 1000 10,000 100,000 1,000,000
definition of rejects often differs between manufacturers.
TIME (HOURS)
While ON Semiconductor uses data sheet limits to
Figure 1. determine failures, sometimes rejects are counted only if
they are catastrophic. Due to the increasing chance of a test
Both the infant mortality and random failure rate regions not being representative of the entire population, as sample
can be described through the same types of calculations. size and test time are decreased, the x2 calculation produces
During this time the probability of having no failures to a surprisingly high values of λ for short test durations even
specific point in time can be expressed by the equation: though the true long term failure rate may be quite low. For
Po = e– λ t this reason relatively large amounts of data must be gathered
where λ is the failure rate and t is time. Since λ is changing to demonstrate the real long term failure rate.
rapidly during infant mortality, the expression does not Since this would require years of testing on thousands of
become useful until the random period, where λ is relatively devices, methods of accelerated testing have been
constant. In this equation λ is failures per unit of time. It is developed.
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432
Years of semiconductor device testing has shown that devices will be used (Figure 3). For Discrete products, 0.7
temperature will accelerate failures and that this behavior eV is generally applied.
fits the form of the Arrhenius equation: To accomplish this, the time in device hours (t1) and
R (t) = R0(t)e – θ/kT temperature (T1) of the test are plotted as point P1. A vertical
line is drawn at the temperature of interest (T2) and a line
where R(t) = Reaction rate as a function of time and
with a 1.0 eV slope is drawn through point P1.
temperature
Its intersection with the vertical line defines point P2, and
R0 = A constant
determines the number of equivalent device hours (t2). This
t = Time
number may then be used with the x2 formula to determine
θ = Activation energy in electron volts
the failure rate at the temperature of interest. Assuming T1
k = Boltzman’s constant
of 125_C at t1 of 10,000 hours, a t2 of 7.8 million hours
T = Temperature in degrees Kelvin
results at a T2 of 50_C. If one reject results in the 10,000
To provide time–temperature equivalents this equation is device hours of testing at 125_C, the failure rate at that
applied to failure rate calculations in the form: temperature will be 0.1%/1,000 hours using a 60%
t = t0e θ/kT confidence level. One reject at the equivalent 7.8 million
where t = time device hours at 50_C will result in a 0.0008%/1,000 hour
t0 = A constant failure rate, as illustrated in Figure 4.
The Arrhenius equation essentially states that reaction Three parameters determine the failure rate quoted by the
rate increases exponentially with temperature. This manufacturer: the failure rate at the test temperature, the
produces a straight line when plotted in log–linear paper activation energy employed, and the difference between the
with a slope expressed by Θ. Θ may be physically test temperature and the temperature of the quoted λ. A term
interpreted as the energy threshold of a particular reaction or often used in this manipulation is the “acceleration factor”
failure mechanism. The activation energy exhibited by which is simply the equivalent device hours at the lower
semiconductors varies from about 0.3 eV. Although the temperature divided by the actual test device hours.
relationships do not prohibit devices from having poor Every device will eventually fail, but with the present
failure rates and high activation energies, good performance techniques in Semiconductor design and applications, the
usually does not imply a high Θ. Studies by Bell Telephone wearout phase is extended far beyond the lifetime required.
Laboratories have indicated that an overall Θ for During wearout, as in infant mortality, the failure rate is
semiconductors is 1.0 eV. This value has been accepted by changing rapidly and therefore loses its value. The
the Rome Air Development Command for parameter used to describe performance in this area is
time–temperature acceleration in powered burn–in. Data “Median Life” and is the point at which 50% of the devices
taken by ON Semiconductor on Integrated Circuits have have failed. There are currently only few significant wearout
verified this number and it is therefore applied as our mechanisms: electromigration of circuit metallization,
standard time–temperature regression for extrapolation of electrolytic corrosion in plastic devices and metal fatigue for
high temperature failure rates to temperatures at which the Power devices.
1.2 1.6 2.0 2.4 2.8 3.2 3.6 1.2 1.6 2.0 2.4 2.8 3.2 3.6
1000 k 100 100 k
100 k 10
λ , FAILURE RATE (%/1000 HOURS)
10 k 1.0
t2
TIME (HOURS)
P2
1.0 k
λ2
100
0.01
10
t1
P1 λ1
1.0 eV
1.0
SLOPE
0.0001
0.1
T1 T2 0.00001
500 200 100 50 0
TEMPERATURE (°C) 500 200 100 50 0
Figure 3. Normalized Time–Temperature TEMPERATURE (°C)
Regressions for Various Activation Energy Values Figure 4. Failure Rate
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433
For increased flexibility in working with a broad range of where
device hours, the time–temperature regression lines have TJ = maximum junction temperature
been normalized to 500_C and the time scale omitted, TA = maximum ambient temperature
permitting the user to define the scale based on his own PD = calculated maximum power dissipation
requirements. including effects of external loads (see
Power Dissipation in section III).
THERMAL MANAGEMENT
θJC = average thermal resistance, junction to case
Circuit performance and long–term circuit reliability are θCA = average thermal resistance, case to ambient
affected by die temperature. Normally, both are improved by θJA = average thermal resistance, junction to
keeping the IC junction temperatures low. ambient
Electrical power dissipated in any integrated circuit is a
This ON Semiconductor recommended formula has been
source of heat. This heat source increases the temperature of
approved by RADC or DESC for calculating a “practical”
the die relative to some reference point, normally the
maximum operating junction temperature for
ambient temperature of 25_C in still air. The temperature
MIL–M–38510 (JAN) devices.
increase, then, depends on the amount of power dissipated
Only two terms on the right side of equation (1) can be
in the circuit and on the net thermal resistance between the
varied by the user — the ambient temperature, and the
heat source and the reference point.
device case–to–ambient thermal resistance, θCA. (To some
The temperature at the junction is a function of the
extent the device power dissipation can also be controlled,
packaging and mounting system’s ability to remove heat
but under recommended use the VCC supply and loading
generated in the circuit — from the junction region to the
dictate a fixed power dissipation.) Both system air flow and
ambient environment. The basic formula for converting
the package mounting technique affect the θCA thermal
power dissipation to estimated junction temperature is:
resistance term. θJC is essentially independent of air flow
TJ = TA + PD(θJC + θCA) (1) and external mounting method, but is sensitive to package
or TJ = TA + PD(θJA)
(2) material, die bonding method, and die area.
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Thermal Resistance in Still Air
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Package Description
θJC (_C/Watt)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
No. Body Body Body Die Die Area Flag Area
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
Leads Style Material WxL Bonds (Sq. Mils) (Sq. Mils) Avg. Max.
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
14 DIL Epoxy 1/4″ x 3/4″ Epoxy 4096 6,400 38 61
16 DIL Epoxy 1/4″ x 3/4″ Epoxy 4096 12,100 34 54
NOTES:
1. All plastic packages use copper lead frames.
2. Body style DIL is “Dual–In–Line.”
3. Standard Mounting Method: Dual–In–Line Socket or P/C board with no contact between bottom of package and socket or P/C board.
Figure 5. Thermal Resistance Values for Standard I/C Packages
For applications where the case is held at essentially a These figures show the proportionate increase in the
fixed temperature by mounting on a large or junction temperature of each dual in–line package as the air
temperature–controlled heat sink, the estimated junction passes over each device. For higher rates of air flow the
temperature is calculated by: change in junction temperature from package to package
ÎÎÎÎÎÎ
TJ = TC + PD(θJC) (3) down the airstream will be lower due to greater cooling.
ÎÎÎÎÎÎ
where TC = maximum case temperature and the other
Power Dissipation Junction Temperature Gradient
ÎÎÎÎÎÎ
parameters are as previously defined. (mW) (_C/Package)
The maximum and average θJC resistance values for
ÎÎÎÎÎÎ
200 0.4
standard IC packages are given in Figure 5.
ÎÎÎÎÎÎ
250 0.5
AIR FLOW
ÎÎÎÎÎÎ
300 0.63
The majority of users employ some form of air–flow
ÎÎÎÎÎÎ
400 0.88
cooling. As air passes over each device on a printed circuit
board, it absorbs heat from each package. This heat gradient Devices mounted on 0.062″ PC board with Z axis spacing of 0.5″.
Air flow is 500 Ifpm along the Z axis.
from the first package to the last package is a function of the
air flow rate and individual package dissipations. Figure 6 Figure 6. Thermal Gradient of Junction Temperature
provides gradient data at power levels of 200 mW, 250 mW, (16–Pin Dual–in–Line Package)
300 mW, and 400 mW with an air flow rate of 500 Ifpm.
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OPTIMIZING THE LONG TERM RELIABILITY OF Table 1 is graphically illustrated in Figure 7 which shows
PLASTIC PACKAGES that the reliability for plastic and ceramic devices are the
Todays plastic integrated circuit packages are as reliable same until elevated junction temperatures induces
as ceramic packages under most environmental conditions. intermetallic failures in plastic devices. Early and mid–life
However when the ultimate in system reliability is required, failure rates of plastic devices are not effected by this
thermal management must be considered as a prime system intermetallic mechanism.
design goal.
Modern plastic package assembly technology utilizes
gold wire bonded to aluminum bonding pads throughout the
electronics industry. When exposed to high temperatures for
FAILURE RATE OF PLASTIC = CERAMIC
protracted periods of time an intermetallic compound can UNTIL INTERMETALLIC FAILURES OCCUR
form in the bond area resulting in high impedance contacts
NORMALIZED FAILURE RATE

and degradation of device performance. Since the formation
of intermetallic compounds is directly related to device
junction temperature, it is incumbent on the designer to
TJ = 130°C
TJ = 120°C
TJ = 110°C
TJ = 100°C
TJ = 90 °C
TJ = 80 °C
determine that the device junction temperatures are
consistent with system reliability goals.
Predicting Bond Failure Time:

Based on the results of almost ten (10) years of +125_C 1
operating life testing, a special arrhenius equation has been
developed to show the relationship between junction
temperature and reliability. 1 10 100 1000
TIME, YEARS
11554.267
Eq. (1) T = (6.376 x 109)e
273.15 + TJ Figure 7. Failure Rate versus Time
Where: T = Time in hours to 0.1% bond failure Junction Temperature
T = (1 failure per 1,000 bonds).
TJ = Device junction temperature, _C.
And:
Eq. (2) TJ = TA + PDθJA = TA + ∆TJ
Procedure
Where: TJ = Device junction temperature, _C. After the desired system failure rate has been established
TA = Ambient temperature, _C. for failure mechanisms other than intermetallics, each
PD = Device power dissipation in watts. device in the system should be evaluated for maximum
θJA = Device thermal resistance, junction to air, junction temperature. Knowing the maximum junction
_C/Watt. temperature, refer to Table 1 or Equation 1 to determine the
∆TJ = Increase in junction temperature due to continuous operating time required to 0.1% bond failures
on–chip power dissipation. due to intermetallic formation. At this time, system
Table 1 shows the relationship between junction reliability departs from the desired value as indicated in
temperature, and continuous operating time to 0.1%. bond Figure 7.
failure, (1 failure per 1,000 bonds). Air flow is one method of thermal management which
should be considered for system longevity. Other commonly
Table 1. Device Junction Temperature versus Time
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
used methods include heat sinks for higher powered devices,
to 0.1% Bond Failures refrigerated air flow and lower density board stuffing. Since
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎ
Junction
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Temperature _C Time, Hours Time, Years
θCA is entirely dependent on the application, it is the
responsibility of the designer to determine its value. This can
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
80 1,032,200 117.8 be achieved by various techniques including simulation,
modeling, actual measurement, etc.
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
90 419,300 47.9
100 178,700 20.4 The material presented here emphasizes the need to
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎ
110
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
120
79,600
37,000
9.4
4.2
consider thermal management as an integral part of system
design and also the tools to determine if the management
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
methods being considered are adequate to produce the
130 17,800 2.0
desired system reliability.
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
140 8,900 1.0
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PD, MAXIMUM POWER DISSIPATION PER PACKAGE (mW)
PD, MAXIMUM POWER DISSIPATION PER PACKAGE (mW)

150°C 150°C
137°C 500 500
135°C
TJ , JUNCTION TEMPERATURE ( °C)
TJ , JUNCTION TEMPERATURE ( °C)

139°C 134°C
125°C TJ SOIC 400 125°C
129°C 130°C 400
121°C
PD TJ SOIC PD
TJ PDIP 300 300
100°C 99°C PDIP & SOIC 100°C PDIP & SOIC
– 7 mW/°C 98°C – 7 mW/°C
200 89°C 200
81°C
75°C 75°C TJ PDIP
100 100
58°C
50°C 50°C
25°C 65°C 125°C 25°C 65°C 125°C
TA, AMBIENT TEMPERATURE TA, AMBIENT TEMPERATURE
Figure 8. Junction Temperature for Worst Case Figure 9. Junction Temperature for Typical
CMOS Logic Device CMOS Logic Device
This graph illustrates junction temperature for the worst case CMOS This graph illustrates junction temperature for a CMOS Logic device
Logic device (MC14007UB) — smallest die area operating at (MC14053B) — average die area operating at maximum power
maximum power dissipation limit in still air. The solid line indicates dissipation limit in still air. The solid line indicates the junction
the junction temperature, TJ, in a Dual–In–Line (PDIP) package and temperature, TJ, in a Dual–In–Line (PDIP) package and in a Small
in a Small Outline IC (SOIC) package versus ambient temperature, Outline IC (SOIC) package versus ambient temperature, TA. The
TA. The dotted line indicates maximum allowable power dissipation dotted line indicates maximum allowable power dissipation derated
derated over the ambient temperature range, 25_C to 125_C. over the ambient temperature range, 25_C to 125_C.
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CHAPTER 8
Equivalent Gate Count
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EQUIVALENT GATE COUNT
The following is a list of equivalent gate counts for some of ON Semiconductor’s CMOS devices. In general for CMOS,
the number of equivalent gates is equal to the total number of transistors on chip divided by four. This list includes only those
devices with equivalent gate counts known at the time of this printing.
EQUIVALENT EQUIVALENT
DEVICE GATE COUNT DEVICE GATE COUNT
MC14001B 8 MC14081B 10
MC14001UB 4 MC14082B 8
MC14007UB 1.5 MC14093B 18
MC14008B 40 MC14094B 79
MC14011B 8 MC14099B 70
MC14011UB 4 MC14174B 43.5
MC14012B 7 MC14175B 39.5
MC14013B 16 MC14490 136.5
MC14014B 74 MC14503B 17
MC14015B 53 MC14504B 37.5
MC14016B 8 MC14511B 54
MC14017B 62.5 MC14512B 17.25
MC14018B 38.25 MC14514B 59
MC14020B 84 MC14515B 67
MC14021B 74 MC14516B 61
MC14023B 9 MC14517B 119
MC14024B 59 MC14518B 43.5
MC14025B 9 MC14520B 43.5
MC14028B 26 MC14526B 86
MC14029B 65.5 MC14528B 24
MC14040B 73 MC14532B 38.5
MC14042B 17.5 MC14536B 103
MC14046B 35 MC14538B 38
MC14049UB 3 MC14541B 93
MC14049B 9 MC14543B 52
MC14050B 6 MC14549B 122
MC14051B 48.5 MC14551B 35
MC14052B 38.5 MC14553B 147.5
MC14053B 38 MC14555B 21
MC14060B 73.5 MC14556B 25
MC14066B 13 MC14557B 232.5
MC14067B 65 MC14559B 122
MC14069UB 3 MC14562B 206
MC14071B 10 MC14569B 156
MC14073B 10.5 MC14572UB 4
MC14076B 32.5 MC14584B 18
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CHAPTER 9
Packaging Information Including Surface Mounts
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PACKAGE DIMENSIONS
The standard package availability for each device is indicated on the front page of the individual data sheets. Dimensions
for the packages are given in this chapter. Surface mount packages may be special ordered by specifying the following suffixes:
“D” (narrow SOIC), “DW” (wide SOIC), or “DT” (TSSOP). For example, to order a quad NOR gate, use MC14001BD.
14-Pin Packages
PDIP–14
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE M NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
N F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
–T– J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING
PLANE L 0.290 0.310 7.37 7.87
K J M ––– 10_ ––– 10_
H G D 14 PL M N 0.015 0.039 0.38 1.01
0.13 (0.005) M
SOIC–14
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
–A– Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B– P 7 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
G R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
–T– F 0.40 1.25 0.016 0.049
K M J G 1.27 BSC 0.050 BSC
SEATING D 14 PL
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
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14-Pin Packages (continued)
TSSOP–14
DT SUFFIX
PLASTIC PACKAGE
CASE 948G–01
ISSUE O
14X K REF NOTES:
0.10 (0.004) M T U S V S Y14.5M, 1982.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
N (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE INTERLEAD
2X L/2 FLASH OR PROTRUSION. INTERLEAD FLASH OR
M PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
–U– N PROTRUSION. ALLOWABLE DAMBAR
PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
IDENT. F EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1 7 6. TERMINAL NUMBERS ARE SHOWN FOR
DETAIL E REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
0.15 (0.006) T U S
A K
MILLIMETERS INCHES
ÉÉÉ
ÇÇÇ
–V– K1 DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
ÇÇÇ
ÉÉÉ
B 4.30 4.50 0.169 0.177
J J1 C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N–N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C –W– K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
–T– SEATING D G H DETAIL E
PLANE
SOEIAJ–14
F SUFFIX
PLASTIC PACKAGE NOTES:
CASE 965–01 Y14.5M, 1982.
ISSUE O 3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
14 8 LE REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
Q1 INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
E HE M_ TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
1 7 L BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P MILLIMETERS INCHES
Z
DIM MIN MAX MIN MAX
D A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
VIEW P b 0.35 0.50 0.014 0.020
e A c 0.18 0.27 0.007 0.011
c D 9.90 10.50 0.390 0.413
E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
HE 7.40 8.20 0.291 0.323
0.50 0.50 0.85 0.020 0.033
b A1 LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
0.13 (0.005) M 0.10 (0.004) Q1 0.70 0.90 0.028 0.035
Z ––– 1.42 ––– 0.056
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16-Pin Packages
PDIP–16
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01
SOIC–16
D SUFFIX
PLASTIC PACKAGE
CASE 751B–05
–A– ISSUE J
NOTES:
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
–B– MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 _ B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
–T– SEATING G 1.27 BSC 0.050 BSC
PLANE
M J J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
D 16 PL M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019
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SOEIAJ–16
F SUFFIX NOTES:
PLASTIC PACKAGE Y14.5M, 1982.
CASE 966–01 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
ISSUE O MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
16 9 LE 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
Q1 5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
E HE M_ DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
1 8 L RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
DETAIL P TO BE 0.46 ( 0.018).
Z MILLIMETERS INCHES
D DIM MIN MAX MIN MAX
A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
VIEW P
e A b 0.35 0.50 0.014 0.020
c c 0.18 0.27 0.007 0.011
D 9.90 10.50 0.390 0.413
E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
HE 7.40 8.20 0.291 0.323
A1 L 0.50 0.85 0.020 0.033
b LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
0.13 (0.005) M 0.10 (0.004) Q1 0.70 0.90 0.028 0.035
Z ––– 0.78 ––– 0.031
TSSOP–16
DT SUFFIX
PLASTIC PACKAGE NOTES:
CASE 948F–01 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ISSUE O 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
16X K REF FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
0.10 (0.004) M T U S V S (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
0.15 (0.006) T U S FLASH OR PROTRUSION. INTERLEAD FLASH OR
K PROTRUSION SHALL NOT EXCEED
ÉÉ
ÇÇÇ
0.25 (0.010) PER SIDE.
K1 5. DIMENSION K DOES NOT INCLUDE DAMBAR
ÇÇÇ
ÉÉ
16 9 PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
2X L/2 J1 EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
B SECTION N–N REFERENCE ONLY.
L –U– 7. DIMENSION A AND B ARE TO BE DETERMINED
J AT DATUM PLANE –W–.
PIN 1
IDENT. MILLIMETERS INCHES
DIM MIN MAX MIN MAX
1 8
A 4.90 5.10 0.193 0.200
N B 4.30 4.50 0.169 0.177
0.25 (0.010) C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
0.15 (0.006) T U S
F 0.50 0.75 0.020 0.030
A M
G 0.65 BSC 0.026 BSC
–V– H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
N J1 0.09 0.16 0.004 0.006
F K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
DETAIL E M 0_ 8_ 0_ 8_
C –W–
0.10 (0.004)
–T– SEATING H DETAIL E
PLANE D G
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SOIC–16
DW SUFFIX
PLASTIC PACKAGE
CASE 751G–03
D A ISSUE B
q
16 9
NOTES:
M
1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
B
PER ASME Y14.5M, 1994.

H
h X 45 _
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
M
E
8X
PROTRUSION.
0.25
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
1 8 OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16X B B MILLIMETERS
DIM MIN MAX
A 2.35 2.65
0.25 M T A S B S
A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 10.15 10.45
E 7.40 7.60
A
e 1.27 BSC
H 10.05 10.55
L
SEATING h 0.25 0.75
14X e PLANE
L 0.50 0.90
A1
T C q 0_ 7_
18-Pin Package
PDIP–18
P SUFFIX
PLASTIC PACKAGE
CASE 707–02
ISSUE C
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
18 10 MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
B 2. DIMENSION L TO CENTER OF LEADS WHEN
1 9 FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
A MILLIMETERS INCHES
DIM MIN MAX MIN MAX
L A 22.22 23.24 0.875 0.915
C B 6.10 6.60 0.240 0.260
C 3.56 4.57 0.140 0.180
D 0.36 0.56 0.014 0.022
F 1.27 1.78 0.050 0.070
N K G 2.54 BSC 0.100 BSC
J H 1.02 1.52 0.040 0.060
F D SEATING M J 0.20 0.30 0.008 0.012
PLANE K 2.92 3.43 0.115 0.135
H G L 7.62 BSC 0.300 BSC
M 0_ 15_ 0_ 15 _
N 0.51 1.02 0.020 0.040
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24-Pin Packages
PDIP–24
P SUFFIX
PLASTIC PACKAGE
CASE 709–02
ISSUE C NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
24 13 MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
1 12 FLASH.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 31.37 32.13 1.235 1.265
A C L B 13.72 14.22 0.540 0.560
C 3.94 5.08 0.155 0.200
N D 0.36 0.56 0.014 0.022
F 1.02 1.52 0.040 0.060
K G 2.54 BSC 0.100 BSC
H 1.65 2.03 0.065 0.080
H F M J J 0.20 0.38 0.008 0.015
SEATING K 2.92 3.43 0.115 0.135
G D PLANE
L 15.24 BSC 0.600 BSC
M 0_ 15_ 0_ 15 _
N 0.51 1.02 0.020 0.040
SOIC–24
DW SUFFIX
PLASTIC PACKAGE
CASE 751E–04
ISSUE E
–A–
24 13 NOTES:
Y14.5M, 1982.
–B– 12X P MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
0.010 (0.25) M B M
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
1 12 PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
24X D J
MILLIMETERS INCHES
0.010 (0.25) M T A S B S
DIM MIN MAX MIN MAX
A 15.25 15.54 0.601 0.612
F B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
R X 45 _ D 0.35 0.49 0.014 0.019
F 0.41 0.90 0.016 0.035
G 1.27 BSC 0.050 BSC
C J 0.23 0.32 0.009 0.013
K 0.13 0.29 0.005 0.011
–T– M 0_ 8_ 0_ 8_
SEATING M P 10.05 10.55 0.395 0.415
PLANE 22X G K R 0.25 0.75 0.010 0.029
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ON SEMICONDUCTOR MAJOR WORLDWIDE SALES OFFICES
UNITED STATES CANADA INTERNATIONAL (continued)
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DL131/D
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CMOS Logic Data
ON Semiconductor
ON Semiconductor
CMOS Logic Data

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PUBLICATION ORDERING INFORMATION

PUBLICATION ORDERING INFORMATION

Chapter 2 — Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 3 — Reliability Audit Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chapter 4 — B and UB Series Family Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chapter 5 — CMOS Handling and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Chapter 6 — CMOS Logic Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 7 — CMOS Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

Chapter 8 — Equivalent Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

Chapter 9 — Packaging Information Including Surface Mounts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

Device Function Page

Pull 500* piece sample from lot following Group A

ADD 500 CYCLES

SCRAP SCRAP SCRAP

3.0 TEST CONDITIONS AND COMMENTS

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

VIL = 1.5 V Vout = 0.5 V Vout

FIRST STAGE VIL = 1.5 V SECOND STAGE

ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ

PROPAGATION DELAY AND RISE TIME

Figure 2. Networks for Minimizing ESD and Reducing

POWER SUPPLIES the possibility of latch–up related failures. This system

Figure 4. Secondary Breakdown Characteristics

Figure 5. Battery Backup Interface

INPUTS VDD = 5.0 Vdc

All inputs, while in the recommended operating range

Vout , OUTPUT VOLTAGE (V)

R2 7.5 pF For these reasons, all unused inputs should be connected

VDD VDD P–CHANNEL N–CHANNEL VSS

Figure 11. CMOS Wafer Cross Section

Figure 12. Latch Up Circuit Schematic

B-Suffix Series CMOS Gates

MC14081B Quad 2–Input AND Gate

MC14082B Dual 4–Input AND Gate

 Semiconductor Components Industries, LLC, 2000 32 Publication Order Number:

MC14001B MC14011B MC14071B MC14081B

MC14025B MC14023B MC14073B MC14082B

IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD

MC14071B MC14073B MC14081B MC14082B

ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ

B–SERIES GATE SWITCHING TIMES

Figure 1. Switching Time Test Circuit and Waveforms

MC14001B, MC14071B MC14025B

MC14023B, MC14073B MC14011B, MC14081B

TYPICAL B–SERIES GATE CHARACTERISTICS

N–CHANNEL DRAIN CURRENT (SINK) P–CHANNEL DRAIN CURRENT (SOURCE)

ID , DRAIN CURRENT (mA)

Figure 2. VGS = 5.0 Vdc Figure 3. VGS = – 5.0 Vdc

ID , DRAIN CURRENT (mA)

Figure 4. VGS = 10 Vdc Figure 5. VGS = – 10 Vdc

ID , DRAIN CURRENT (mA)

Figure 6. VGS = 15 Vdc Figure 7. VGS = – 15 Vdc

TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)

VOLTAGE TRANSFER CHARACTERISTICS

V out , OUTPUT VOLTAGE (Vdc)

Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc

Figure 10. VDD = 15 Vdc

Vout VDD Vout VDD

VIL VIH VIL VIH

Figure 11. DC Noise Immunity