VLSI DESIGN Laboratory

Xilinx ISE Design Suite - INSTRUCTIONS

1. Create a new empty Folder in D: or E: drive (this folder named “VLSILAB\ECE6_current

year\GROUP_X” is already created by your teacher. „X‟ stands for the respective group, for
example A or B or C).
2. Create a new sub folder in GROUP_X. The name of this new folder should be XY where „Y‟ is the
number allotted to each sub group, for example, A3, B7, C5, etc.
3. Create a new folder in „XY‟. Name it X_VHDL, where X stands for your GROUP A or B, as
applicable.

4. Double click the icon available on the desktop.

5.

CLICK

6.

__________________________________________________________________________________
This is a property of the compiler. No part of this document may be reproduced or transmitted in any form or Compiled by: Dr. S. Kumar
by any means, electronic or mechanical, including photocopying, recording or by any information storage and Dept of Electronics Engg. ISM Dhanbad.
retrieval system, without permission from the compiler. © 2012 by Dr. Subindu Kumar. All Rights Reserved
 VLSI DESIGN Laboratory
Xilinx ISE Design Suite - INSTRUCTIONS

7.

8.

(a) (b)

(c)

__________________________________________________________________________________
This is a property of the compiler. No part of this document may be reproduced or transmitted in any form or Compiled by: Dr. S. Kumar
by any means, electronic or mechanical, including photocopying, recording or by any information storage and Dept of Electronics Engg. ISM Dhanbad.
retrieval system, without permission from the compiler. © 2012 by Dr. Subindu Kumar. All Rights Reserved
 VLSI DESIGN Laboratory
Xilinx ISE Design Suite - INSTRUCTIONS

9.

10.

11.

__________________________________________________________________________________
This is a property of the compiler. No part of this document may be reproduced or transmitted in any form or Compiled by: Dr. S. Kumar
by any means, electronic or mechanical, including photocopying, recording or by any information storage and Dept of Electronics Engg. ISM Dhanbad.
retrieval system, without permission from the compiler. © 2012 by Dr. Subindu Kumar. All Rights Reserved
 VLSI DESIGN Laboratory
Xilinx ISE Design Suite - INSTRUCTIONS

12.

13.

Type this and save

__________________________________________________________________________________
This is a property of the compiler. No part of this document may be reproduced or transmitted in any form or Compiled by: Dr. S. Kumar
by any means, electronic or mechanical, including photocopying, recording or by any information storage and Dept of Electronics Engg. ISM Dhanbad.
retrieval system, without permission from the compiler. © 2012 by Dr. Subindu Kumar. All Rights Reserved
 VLSI DESIGN Laboratory
Xilinx ISE Design Suite - INSTRUCTIONS

14.

Double click

15.

Double click

__________________________________________________________________________________
This is a property of the compiler. No part of this document may be reproduced or transmitted in any form or Compiled by: Dr. S. Kumar
by any means, electronic or mechanical, including photocopying, recording or by any information storage and Dept of Electronics Engg. ISM Dhanbad.
retrieval system, without permission from the compiler. © 2012 by Dr. Subindu Kumar. All Rights Reserved
 VLSI DESIGN Laboratory
Xilinx ISE Design Suite - INSTRUCTIONS

16.

17.

(a) Right click

(b) Left click

__________________________________________________________________________________
This is a property of the compiler. No part of this document may be reproduced or transmitted in any form or Compiled by: Dr. S. Kumar
by any means, electronic or mechanical, including photocopying, recording or by any information storage and Dept of Electronics Engg. ISM Dhanbad.
retrieval system, without permission from the compiler. © 2012 by Dr. Subindu Kumar. All Rights Reserved
 VLSI DESIGN Laboratory
Xilinx ISE Design Suite - INSTRUCTIONS

18.

After defining
the clock click
“Apply” and
then “OK”

For port „a‟ For port „b‟

DO NOT GIVE ANY CLOCK TO PORT ‘c’

19.

20.

21.

Save the file as

__________________________________________________________________________________
This is a property of the compiler. No part of this document may be reproduced or transmitted in any form or Compiled by: Dr. S. Kumar
by any means, electronic or mechanical, including photocopying, recording or by any information storage and Dept of Electronics Engg. ISM Dhanbad.
retrieval system, without permission from the compiler. © 2012 by Dr. Subindu Kumar. All Rights Reserved
 VLSI DESIGN Laboratory
Xilinx ISE Design Suite - INSTRUCTIONS

22. View RTL schematic

__________________________________________________________________________________
This is a property of the compiler. No part of this document may be reproduced or transmitted in any form or Compiled by: Dr. S. Kumar
by any means, electronic or mechanical, including photocopying, recording or by any information storage and Dept of Electronics Engg. ISM Dhanbad.
retrieval system, without permission from the compiler. © 2012 by Dr. Subindu Kumar. All Rights Reserved