Problema 1.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sumres is
port( A,B : in std_logic_vector (3 downto 0);
ci : in std_logic;
EN : in std_logic;
S : out std_logic_vector (3 downto 0);
Co : out std_logic);
end sumres;

architecture solucion of sumres is

begin

process (EN,A,B)
begin
if (EN= ‘1’) then S<=A+B;
elsif (EN= ‘0’) then S=<A-B;
end if;
end process;

end solucion;

El circuito funciona como restador para EN=1

El circuito funciona como sumador para EN=0

Problema 2.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity comparador is
port( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector(3 downto 0);
IGU : out std_logic;
MAY : out std_logic;
MEN : out std_logic;
end comparador;

architecture behavioral of comparador is

begin
IGU <= ‘1’ when A = B else ‘0’;
MAY <= ‘1’ when A > B else ‘0’;
MEN <= ‘1’ when A < B else ‘0’;
end architecture;
Problema 3.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity pregunta3 is port (

x1,x2,x3,x4: in std_logic ;
f1,f2: out std_logic);
end pregunta3;

architecture behavioral of pregunta3 is begin

f1<=(x1 and(not 3))or(x2 and(not x3))or((not x3)and(not x4))or(x1 and x2)or
(x1 and(not x4));
f2<=(x1 or(not x3))and(x1 or x2 or(not x4))and(x2 or(not x3) or(not x4));
end architecture behavioral;
Problema 4.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity pregunta4 is port(

x1,x2,x3,x4: in std_logic;
fi,f2: out std_logic);
end pregunta4;

architecture behavioral of pregunta4 is begin

f1<=((x1 and x3)or(not x1 and not x3))or((x2 and x4)or(not x2 and not x4));
f2<=(x1 and x2 and not x3 and not x4)or(not x1 and not x2 and x3 and x4)
or(x1 and not x2 and not x3 and x4)or(not x1 and x2 and x3 and not x4);

end architecture behavioral;