8085A/8085A-2 SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSORS = Single +5V Power Supply = Four Vectored Interrupt Inputs (One is = 100% Software Compatible with 8080A en pis an Cok = 1.3 us Instruction Cycle (8085A); ‘ompatibie Interrupt 0.8 us (8085A-2) = Serial In/Serial Out Port = On-Chip Clock Generator (with External _ Crystal, LC or RC Network) . ain eeusaa and Double Precision = On-Chip System Controller; Advanced Cycle Status Information Available for = Direct Addressing Capability to 64k Large System Control Bytes of Memory The intel® 8085A is a complete 8 bit parallel Central Processing Unit (CPU). Its instruction sets 100% software compatible with the 8080A microprocessor, and itis designed to improve the present 8080A's performance by higher system speed. Its high level of system integration allows a minimum system of three IC's [B085A (CPU), 8156 (RAM/1O} and6355/8755A, [ROM/PROM/0}] while maintaining total system expandabilty. The BOBSA-2 Is a faster version of the BOB5A, ‘The 8085A incorporat ofthe features that the 6224 (clock generator) and 8228 (system controller) provided for the high level of system integration. .ddress is split between the 8 bit address bus and the & bit data bus. The ‘on-chip address latches of 8155/8156/8355/8755A memory products allow a direct intertace with the BOB5A, __ Figure 2. 8085A Pin Figure 1. 6085A CPU Functional Block Diagram ‘Configuration 610 powers8085A/8085A-2 Table 1. Pin Description Symbol [Type ‘ame ad Funetion ‘Symbol Wee ‘Wame and Function Aehts ° ‘during RESET. 4 ‘Adress Bus: The most significant {bite of the memory address or the 8 bits of the UO address, Stated uring Hold and Halt modes and READY Wultiplexed Addross/Data Buc Lower 8 bits ofthe memory address (or VO address) appear on the Dus suring the fet clock cycle (Teta) fof amachine eel. t then becomes ‘tho data bus during the second and third clock cycles. 1 Ready: 1 READY is high during a read of writ cyte it indicates that the memory or peripheralisready to ‘20nd oF receive data I READY ie Tow, the cpu will wait an intogral ‘umber of clock eyeles for READY to go high botore completing the ead or write cycle. READY must Conform to specified etupand holt times (HOLD NE ° “Address Latch Enable ‘uring the fst clock stato of ama- chine cycloand enabies theadress te getiatched ito t of periphoras. The fang edge of [ALE is sotto guarantee setup and hho tines forthe acaross informa tion. The fang edge of ALE can ‘also be used to strobe the status information, ALE is never @-stated nvchip latch 0.81, andiony 0 Machine Cycle Status: 8 Status tom 8; ° x x * = stato (high impedance) X= unspecified 1 can be used ae an advanced RAW satus. 1O/M, Sp and S; become ‘alld ai the bogianing of a machine Cycle and remain stable throughout tho cycle, The falling edge of ALE may be used to latch the state of thate kes, ° x x Momory write Momory read vo write WO read Opcode fetch Opeode tater Interrupt Acknowledge Hatt Hold Reset Hold Indices that another mesior Is requesting the uso ofthe address fand data buses, The cpu, upon receiving the hold request, will Felingulsh the use of tho bus as '800n a8 the completion of the cur rent bus transfer Internal process ing can continue. The processor Coan regain the bus only ator the HOLD te removed. When the HOLD is acknowledged, the Address, Data FD, WA, and IMM tines are Stated. HLA Hold Acknowledge: indicates that the epu has recaived the HOLD ro- (quest and that it wil oinquish the Bus In the next clock cya. HLDA 088 low after the Hold request is Temoved. The cpu takes thebus one half clock cycle after HLDA goes tov NTR Read Control: A low jovel on AB Indicates the selected memory oF WO device ie tobe aad and that tho Data Bus is avaliable for the dat transfer, S-tated during Hold and Halt modes snd during RESET. Interrupt Request: used as @ general purpose interrupt. It is ‘Sampled only during the next tothe last clock cycle of an instruction ‘and during Hold and Hel states it Js activa, the Program Counter (PC) ‘wil be inhibited from Inerementing land an INTA wil be issued. During this cycle a RESTART of CALL ine struction can be Ingorted tojump to the intorupt service routine. The INTR is enabled anc labled by software. tie disabled by Reset and Immediately ater an interupt ac cepted. ‘Wate Control: A low level on WAL Indicates the dataon the Data Susie to be written Into the selected ‘memory oF 0 location. Datals set ling edge of WR. 3- Stated during Hold and Halt modes tp at the land during RESET. Taterupt Acknowledge: lsusedin- stead of (and has the same ting 23) RD curing the Instruction cycle ator an INTA ls aocopted. It can be {Used to activa an 82594 Intorupt chip or some other interupt port. ners RST 6S RST 75 Restart interrupta: These three in puts have the same timing as INTL except they cause an internal RESTART to be automatically insorted, “The priory of these intorupte Ie ‘ordered as shown in Table 2. Theee Interrupts have 8 higher priority than INTR. tn alton, they may Be individual matkes out Using the SIM Instruction. ettintel 8085A/8085A-2 Table 1. Pin Description (Continued) ‘Symbol - ‘Tyee ‘Name and Function ‘Symbol Tyee ‘Name and Function TRAP ' Trap interrupt ie a non- Reset out | 0 | Resetout: Reset Outindicates cpu rmaskable RESTART intorrupt, Its Doing reset. Can be used ‘ecognizea at the same time a a a eysiom resot. The signal Is INTRorRSTS5-7.5. Ite unetfectes synchronized to the processor by any mask oF interrupt Enable clock and lasts an intogral number has the highest prot of any itor. of clock periods. pt (S20 Table 2) XX T [iG and xg: Are connected to & TRESETIN | 1 | Rost in: Sets the Program Goun- crystal, LC, or RC network to drive ter to zar0 and resets the Interrupt the internal clock gonarator.X; can Enable and HLDA flip-iops. The algo be an external clock input rom data and adcrese buses and the ‘logle gate The Input frequoncy Is ‘contro ines are $-stated during ‘vided by 2 to give the processar's RESET and because of the Internal operating frequency. asynchronous nature of RESET, the rg 5 Ghee Cock outpatoruneas any processors Internal registers and fiags may be altered by RESET with unpredictable results. AESETINisa tem clock. The perlod of CLIC Is twice the X,, Xp Input periog. | ‘Schmitttriggered input, allowing a0 1] Seria nput Bata Line: The deta on connection to an R-C network for {Ws ine loaded Into accumulator | power-on RESET delay. The cpu is Dit whenever @ RIM instruction Is held in the raset condition 88 Tong srecuted. as RESET W is applies, 's00 (© | Sertat Output Data Line: The out. PULSOD is et or rosot as epecilog bythe SIM instruction. Ves Power: +5 vot supply Ves Ground: Reference Table 2. interrupt Priority, Restart Address, and Sensitivity ‘Address Branched To (1) Name | Prlority | When Interrupt Occurs ‘Type Trigger TRAP, 1 2H Rising edge AND high level unt RST TS 2 SCH Rising edge (latched), RST 6S 3 34H High level untii sampled. FSTS5, 4 20H High level until sampled. INTR 3 See Note (2) High level until sampled. Notes: 1. The procestor pushes the PC on the stack before branching to the indletad adress. 2. The address branched fo depends onthe instruction provided to the cpu when the Interupt is acknowledge. e12 pena