316 CHAPTER 10.

FIRST-ORDER TRANSIENTS

INVA B1 B2 ... Bn-1 INVB

A B l l l l C D
--- --- --- … ---
n n n n

Figure 10.71:

a) The delay is equivalent for each length of wire, so the total delay is twice that of
a single wire of length - < . Using the result from Problem 4 we can easily see the
following.
 
  (   

   
  
(  ( 
 b 
 b

 % %
b

b 
  
b)    ( 
 
 
(  ( 

  

 b 
 b



b b 
c) The

that minimizes   we must also minimize
   
  
(  (
 .

 (
  


  
(


, `

   `  

Solving for


,
 
ANS:: (a)   ^(   

b   b 
   
  
(  (
 (b)   
 

 % %

b b
    (
 (c)   , `
( 
 
 
(


 b   b 



`  ,





b b

Problem 10.7 Figure 10.72 shows a buffer  driving a large load capacitor . The

buffer is built using an inverter pair as in Figure 10.57c. The width to length ratio of each
NMOS transistor in the buffer is <  and the resistors have a value ( . Accordingly,
the gate capacitance seen at the input of the buffer is given by
<     . The buffer
satisfies a static discipline with voltage thresholds given by ]  ]   ] and ] 

]   ] . The supply voltage is ]  . Assume that the internal buffer delay (as defined

in Problem 10.2c) is zero. Assume that there is a 0 to 1 transition at the input at time
  .

a) Compute the propagation delay for the buffer  driving the load for the


rising transition at the input .

b) Now consider Figure 10.73. This figure shows the use of a second buffer with
larger transistors and smaller valued load resistors (   ) interposed between the
first buffer and the load capacitor. Compute the propagation delay for the buffer